Prototyping of Control Algorithms in Matlab/Simulink

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1 Prttpng f Cntrl Algrthms n Matlab/Smuln Rafał GRYGIEL and Marcn PACHOLCZYK Insttute f Autmatc Cntrl Slesan Unverst f echnlg Glwce Pland e-mal: rafal.grgel@plsl.pl marcn.pachlcz@plsl.pl ABSRAC he artcle presents basc prncples f mdel-based desgn methdlg an nterestng new technque n the desgn f embedded sstems. he authrs use Matlab/Smuln sstem and MPC555 mcrcntrller t demnstrate a desgn f a dscrete PID cntrller and an ptmal LQ cntrller. Kewrds: Cntrl Prttpng SIL PIL HIL V-ccle PID LQ Matlab/Smuln.. IRODUCIO he brad avalablt f dgtal cntrl sstems based n mcrcntrllers (embedded sstems) n ndustral as well as cnsumer prducts stmulates develpment f varus mre perfect hardware platfrms desgnated t perfrm numerus cntrl tass. he desgn f a cntrl sstem s usuall dvded n tw parts - develpment f dedcated hardware and sftware cntrllng the specfc behavr f the sstem under cnsderatn. In recent decades we culd bserve a wdespread transtn frm prgrammng n assembler languages t prgrammng n hgh level languages mstl C/C++. hs transtn enabled greater ndependence frm the hardware platfrm and facltated cde re-use. At the mment we are facng anther majr change n the phlsph f prgrammng f the embedded sstems whch s mdel-based desgn. Hardware Fg.. Mdel-based desgn the V dagram. Mdel-based desgn assumes even greater degree f abstractn wth respect t C/C++ f created sftware cde. It assumes the smplest pssble transtn frm the smulatn mdel encded n the frm f a blc dagram t the eecutable cde fr the selected target hardware platfrm. he artcle presents the capabltes f the Matlab/Smuln envrnment fr the mplementatn f the basc assumptns f such a prgrammng mdel. he desgn f dscrete PID and ptmal LQ cntrllers fr an bject wth step respnse mdeled as frst rder nerta wth lag s presented as an eample. Mdel-based desgn n Matlab/Smuln he Matlab/Smuln envrnment tradtnall used fr the smulatn f sstems dnamcs s nw equpped n tls meetng the prncpal bjectves f mdel-based desgn. Smulatn mdel n the frm f Smuln blc dagram can be supplemented wth addtnal blcs representng I/O peratns allwng the measurement and cntrl t be mplemented n the real bject. In the 008b versn f Matlab t s pssble t use Freescale MPC5 (3-bts) and Infnen C6 (6-bts) mcrcntrllers. Bth mcrcntrllers feature the CA bus cmmnl used n autmtve ndustr. Successve stages f the mdel-based desgn are ften presented n the frm f V dagram r ccle (Fg. ). After desgn f functnal bjectves f the prpsed cntrl algrthm and ther verfcatn durng smulatn studes the desgner can graduall prceed wth the transtn t the target hardware platfrm. Befre mplementatn f the cntrl algrthm n the target platfrm a prcess called rapd cntrl prttpng can be perfrmed. hs means a stuatn n whch the cntrl algrthm smulated n real tme usng a PC hardware affect the real bject wth use f specalzed equpment enablng cmmuncatn between PC hardware and the bject. One f the man advantages f the mdel-based desgn sstems s the autmatc generatn f cde (usuall n C language) fr the target platfrm based n a blc dagram used durng smulatn supplemented b addtnal blcs representng I/O functns. he autmatcall generated cde can be verfed durng Sftware n the Lp (SIL) smulatn r Prcessr n the Lp csmulatn (PIL) Fg.. In the frst case the cde cmpled fr the target platfrm s used n the smulatn n a wrapper allwng the eecutn f a fregn cde n Smuln. In the case f PIL sme parts f the smulatn are eecuted n the target platfrm whch requres cnnectn between the PC runnng Matlab /Smuln and the target hardware (RS3 r CA). he net step wll be t transfer the whle cntrl algrthm t the target hardware and Hardware-n-the-Lp (HIL Fg. 3) testng. HIL s the case n whch cntrl algrthm runnng n the target platfrm s tested aganst bject smulated n Matlab/Smuln. After thrugh revew f

2 desgned cntrl strateg and calbratn cntrl algrthm parameters ne can buld fnal prttpe f the devce. he fllwng sectns present cnsecutve steps f the desgn. In the end a HIL testng s perfrmed usng MPC555 mcrcntrller and the CA bus. where: Ah Aν F e g e b dν h = = 0 he cntrl tas s t fllw the reference r t = r t. acheve the bjectve f such value fllwng cntrl PID and LQ cntrllers wll be used. Fg.3. HIL testng. 3. COROL SYSEMS Fg.. SIL smulatn and PIL csmulatn.. DESCRIPIO OF HE COROL SYSEM he bject f cntrl s a cntnuus lnear dnamc sstem wth sngle nput u(t) and sngle utput (t): ( t) = A ( t) + bu ( t) () t t Where (t) s m-dmensnal vectr f the state. State matr A f sze m b m and m-dmensnal cntrl b and utput d vectr are assumed cnstant. he cntrl sgnal u(t) s btaned frm zer-rder hld (ZOH) wth samplng perd h: u ( t ) = u () Fr t ( h h + h] = 0... whse nput s dscrete utput sgnal f the cntrller u. Its value changed n dscrete mments f tme. Output f the bject s als sampled wth perd h. Fr the mments f samplng we btan the fllwng dscrete mdel: F g = + + u (3) PID Cntrller Dscrete PID cntrller s defned b the transfer functn: K reg U ( z) h z D z ( z) = = P + + (4) E( z) I z h z where h s the samplng perd and P I D are gan ntegratn and dfferentatn cnstants respectvel. In ths paper cntrller settngs based n cntnuus apprmatn f dscrete-tme sstem cnsstng f zer-rder hld cntrl bject and samplng element are used. In addtn step respnse f the bject Eq. () s apprmated b frst-rder nerta wth dela: sτ G ( s) = e (5) + s Parameters f G(s) ma be determned b varus methds based n pen lp Eq. () step respnse. One f them s the methd f tw pnts based n tw tme pnts t and t fr whch the step respnse reaches respectvel 8.3% and 63.% f the stead state value: = 5 t t τ = t. (6) In ths paper QDR (Quarter Deca Rat) [ ] cntrller settngs gven n able are used. Zer-rder hld and samplng has been taen nt accunt n the fllwng wa [3 4]: h L = τ + (7)

3 hs crrespnds t the apprmatn f h/ dela ntrduced b ZOH and n cntrast t slutn presented n [5] guarantees the crrect behavr f the cntrl sstem. P PI PID LQ Cntrller able : QDR PID cntrller settngs P 09 I D 333 L L 05 L he purpse f cntrl s t eep as clse as pssble t r. fulfll the requrements we use a cntrl law whch was derved b mnmzatn f squared perfrmance nde defned fr the cntrl sgnal ncrements u : lm ( + ρ ) ρ 0 (8) = 0 I = e + u Fg.4. Schematc dagram f the LQ cntrl sstem. Where e = s the dfference between current sstem utput and desred new stead state resultng frm change f the reference value r. In stead state the fllwng descrptn s true: = F + gu and n ts bass the ncrements can be defned: = = + u = u u u = u + u (9) (0) ang dependences Eq. (0) nt accunt n the equatns e = and f the f errr state f the bject we btan the fllwng qualt nde: lm ( + Q + ρ u ) = 0 I = + = = lm ( Q + qu + qu ) = 0 () Q = F QF q = F Qg q = g Qg + ρ whch s the classcal LQ prblem the slutn f whch taes the frm: c = ˆ () where: c u q = q + F Kg + g Kg depends n pstvel defned slutn K f the Rccat equatn: K = Q + FKF ( q + F KG)( q + F KG) q + g Kg he stead state (9) sgnals u have the frm: ( I F ) r g u = = r = r where l ( I ) F g (3) mplement the cntrl law t s necessar t nw the estmate f the state ˆ f the sstem Eq. (3). We used the full-rder bserver wth structure based n the dscrete Kalman flter: ( ( F )) ˆ Fˆ g + d ˆ + g = f + = + u u ( ) ˆ + ( g ) = F d F g d u + f f f (4) Where f was chsen s that the Eq. (4) was asmpttcall stable. he elements f vectr f are therefre set n such a wa that the matr: F = F d F (5) f f had real r cnjugate cmple egen values lcated nsde the unt crcle: f λ F < (6) Snce the egen values f matrces have apprprate values than the state f the bserver ˆ satsfactrl qucl cnverges t the state f the bserved sstem. he blc dagram f the cntrl sstem ncludng sgnals ensurng transtn t the new stead state Eq. (3) s shwn n Fg. 4. Fg. 6 presents blc dagram f PID cntrl sstem mplemented n MPC555 mcrcntrller and Fg. 7 shws LQ cntrl sstem wth apprprate Kalman flter.

4 4. IMPLEMEAIO I SIMULIK (MPC555) Fg.5. Plant and reference mplementatn n PC. Fg.7. LQ cntrller mplementatn n MPC555. Fg.6. PID cntrller mplementatn n MPC555. he bject Eq. () has been mplemented n Matlab/Smuln envrnment (Fg. 5) tgether wth the elements respnsble fr recevng the cntrl sgnal and sendng the bject utput sgnal and the reference value t the MPC555 mcrcntrller. he zer-rder hld (ZOH) and samplng elements are als shwn. he smulatn s carred ut n real tme whch s ensured b Rblc [6] changng the default smulatn thread prrt t tme-crtcal 5. EXAMPLES present eamples f tme curses f sgnals n dscrete-tme cntrl sstems we have chsen a cntrl path f the fllwng frm: K ( s) =. (7) + ( s) me curses f sgnals n PID cntrl sstem tuned usng QDR parameters fr tw samplng perds h=0.0 and h=0. are shwn n Fg. 8. Fr shrt samplng perd h=0.0 (Fg. 8a) besdes large magntudes f cntrl sgnal u(t) a hgh frequenc dstrtns f that sgnal caused b errrs resultng frm t slw cmmuncatn ver CA bus can be seen. Lnger samplng perd (Fg. 8b) resulted n smaller mamal value f cntrl sgnal. Mrever snce CA transmssn s less tme-crtcal than befre there are n vsble dstrtns n ts tme curse. he crrect tunng f PID cntrller (tang samplng perd nt accunt) resulted n crrect tme curse f the cntrlled sgnal (t) n bth cases. In Fg. 9 eample tme curses f sgnals fr LQG cntrller. In ths case there s nl ne tunable parameter λ. Small value f λ (Fg.9a) results n fast cnvergence f (t) t the new stead state wth versht and relatvel hgh mamal value f the cntrl sgnal u(t). Hgher λ results n smaller u(t) and aperdc cnvergence f (t) t the stead state. a) b) Fg.8. me realzatn wth PID cntrller fr a) h=00; b) h=0.

5 Despte f lac f ntegratve element n the LQ cntrl lp there s n stead state errr. It s guaranteed b the feed-frward structure shwn n Fg. 4. Of curse n case f dscrepanc between the mdel used fr cntrller snthess and the real bject especall ts gan the stead state errr wuld be nevtable. he pssble slutn t ths prblem culd be ntrductn f ntegratve element wth small tme cnstant havng pssbl mnmal nfluence n transent respnses f the sstem. a) b) 6. COCLUSIOS In cnsdered sftware-hardware structure ne have t deal wth prblems related t practcal aspects f such hardware based smulatns. hse are especall quantzatn f sgnals naccuraces resultng frm fed-pnt representatns r desnchrnzatn f samples and buffer Fg.9. me realzatn n LQ structure fr h=0. and a) λ=0.00; b) λ=0.5 verflws related t CA transmssn. Hwever n Matlab/Smuln envrnment ver ppular especall n techncal unverstes wrldwde t s reasnabl eas d desgn and test man aspects f cntrl algrthm and test t n real-tme n the target platfrm hardware. A scentst r a cntrl engneer can cncentrate n develpng cntrl strateg n famlar envrnment wthut the need fr translatng the desgn t the target platfrm C cde. ACKOWLEDGEMES hs wr has been supprted b Mnstr f Scence and Hgher Educatn funds n the ears as develpment prject OR REFERECES [] G. Gdwn S. Graebe M. Salgad: Cntrl Sstem Desgn Prentce Hall 00 [] C. A. Smth A. B. Crrp Prncples and Practces f Autmatc Prcess Cntrl Jhn Wle & Sns 006 [3] R. Grgel and M. Blachuta: On sutablt f the lagdela apprmatn fr perfrmance predctn f sampled-data LQG cntrl sstems 9th IEEE Internatnal Cnference n Methds and Mdels n Autmatn and Rbtcs MMAR 003 Szczecn Pland 003 [4] M. Błachuta R. Grgel On the Effect f Ant-alasng Flters n Sampled-Data PID Cntrl Prc. 009 Chnese Cntrl and Decsn Cnference Guln Chna 7-9 June 009 [5] S. Hara Y. Yamamt H. Fuja: Mdern and Classcal Analss/Snthes Methds n Sampled-Data Cntrl - A bref Overvew wth umercal eamples Prc. f the 35th Cnference n Decsn and Cntrl Kbe 996 [6] tm dwnladed n /03/009.