PLCC/LCC/JLCC GND I/O2 I/O3 I/O4 I/O5 VCC VCC I/O17 I/O16 I/O15 I/O14 I/O13 I/O12

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1 Features High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 46 Product Terms ns Maximum Pin-to-pin Delay for 5V Operation Low-power Edge-sensing L Option with < ma Standby Current 24 Flexible Output Macrocells 48 Flip-flops Two per Macrocell 72 Sum Terms All Flip-flops, I/O Pins Feed in Independently D- or T-type Flip-flops Product Term or Direct Input Pin Clocking Registered or Combinatorial Internal Feedback Backward Compatible with ATV25B/BQL and ATV25H/L Software Advanced Electrically-erasable Technology Reprogrammable % Tested 44-lead Surface Mount Package Block Diagram ATF25C CPLD Family Datasheet ATF25C ATF25CL ATF25CQ ATF25CQL Preliminary Description The ATF25C is the highest-density PLD available in a 44-pin package. With its fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATF25C is a high-performance CMOS (electrically-erasable) programmable logic device (PLD) that utilizes Atmel s proven electrically-erasable technology. Pin Configurations Pin Name Function Logic Inputs CLK/ Pin Clock and Input I/O Bi-directional Buffers I/O,2,4... Even I/O Buffers I/O,3,5... Odd I/O Buffers GND Ground VCC +5V Supply I/O I/O I/O2 I/O3 I/O4 I/O5 VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O DIP I/O6 I/O7 I/O8 I/O9 I/O I/O GND I/O23 I/O22 I/O2 I/O2 I/O9 I/O8 I/O2 I/O3 I/O4 I/O5 VCC VCC I/O7 I/O6 I/O5 I/O4 I/O PLCC/LCC/JLCC I/O I/O GND CLK/ I/O I/O2 I/O8 I/O I/O7 I/O8 I/O9 I/O I/O GND GND I/O23 I/O22 I/O2 I/O2 Note: For ATF25CQ and ATF25CQL (PLCC/LCC/JLCC packages) pin 4 and pin 26 GND connections are not required. Rev. 777G 2/

2 The ATF25C is organized around a single universal array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop. In the ATF25C, four product terms are input to each sum term. Furthermore, each macrocell s three sum terms can be combined to provide up to 2 product terms per sum term with no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array. Product terms provide individual clocks and asynchronous resets for each flip-flop. The flipflops may also be individually configured to have direct input pin clocking. Each output has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. The Atmel-unique L low-power feature is an edge-sensing option that is now field programmable for the ATF25C family. The L feature utilizes Atmel-patented Input Transition Detection (ITD) circuitry and is activated by selecting the L option from the program menu. Using the ATF25C Family s Many Advanced Features The ATF25Cs advanced flexibility packs more usable gates into 44 leads than other PLDs. Some of the ATF25Cs key features are: Fully Connected Logic Array Each array input is always available to every product term. This makes logic placement a breeze. Selectable D- and T-Type Registers Each ATF25C flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. Buried Combinatorial Feedback Each macrocell s Q2 register may be bypassed to feed its input (D/T2) directly back to the logic array. This provides further logic expansion capability without using precious pin resources. Selectable Synchronous/Asynchronous Clocking Each of the ATF25Cs flip-flops has a dedicated clock product term. This removes the constraint that all registers use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. A Total of 48 Registers The ATF25C provides two flip-flops per macrocell a total of 48. Each register has its own clock and reset terms, as well as its own sum term. Independent I/O Pin and Feedback Paths Each I/O pin on the ATF25C has a dedicated input path. Each of the 48 registers has its own feedback term into the array as well. These features, combined with individual product terms for each I/O s output enable, facilitate true bi-directional I/O design. Combinable Sum Terms Each output macrocell s three sum terms may be combined into a single term. This provides a fan in of up to 2 product terms per sum term with no speed penalty. 2 ATF25C Family 777G 2/

3 ATF25C Family Power-up Reset The registers in the ATF25Cs are designed to reset during power-up. At a point delayed slightly from V CC crossing V RST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state as nature of reset and the uncertainty of how V CC actually rises in the system, the following conditions are required:. The V CC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin or terms high, and 3. The clock pin, and any signals from which clock terms are derived, must remain stable during t PR. Parameter Description Typ Max Units t PR Power-up Reset Time 6 ns V RST Power-up Reset Voltage V Level Forced on Odd I/O Pin during PRELOAD Cycle Q Select Pin State Even/Odd Select Even Q State after Cycle Even Q2 State after Cycle Odd Q State after Cycle Odd Q2 State after Cycle V IH /V IL Low Low High/Low X X X V IH /V IL High Low X High/Low X X V IH /V IL Low High X X High/Low X V IH /V IL High High X X X High/Low 777G 2/ 3

4 Preload and Observability of Registered Outputs Programming Software Support Security Fuse Usage Input and I/O Pull-ups The ATF25Cs registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A V IH level on the odd I/O pins will force the appropriate register high; a V IL will force it low, independent of the polarity or other configuration bit settings. The PRELOAD state is entered by placing an.25v to.75v signal on SMP lead 42. When the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 2 registers chosen by the Q select and even/odd select pins. Register 2 observability mode is entered by placing an.25v to.75v signal on pin/lead 2. In this mode, the contents of the buried register bank will appear on the associated outputs when the OE control signals are active. All family members of the ATF25C can be designed with Atmel-Synario and Atmel-Win- CUPL. ProChip designer support will be available Q2. Additionally, the ATF25C may be programmed to perform the ATV25H/Ls functional subset (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV25H/L JEDEC file. In this case, the ATF25C becomes a direct replacement or speed upgrade for the ATV25H/L. The ATF25CQ/CQL are direct replacements for the ATV25BQ/BQL and the AT25H/L, including the lack of extra grounds on P4 and P26. A single fuse is provided to prevent unauthorized copying of ATF25C fuse patterns. Once programmed, the outputs will read programmed during verify. The security fuse should be programmed last, as its effect is immediate. The security fuse also inhibits Preload and Q2 observability. All ATF25C family members have programmable internal input and I/O pinkeeper circuits. The default condition, including when using the AT25CQ/CQL family to replace the AT25BQ/BQL or AT25H/L, is that the pinkeepers are not activated. When pinkeepers are active, inputs or I/Os not being driven externally will maintain their last driven state. This ensures that all logic array inputs and device outputs are known states. Pinkeepers are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below). 4 ATF25C Family 777G 2/

5 ATF25C Family Input Diagram I/O Diagram PUT Functional Logic Diagram Description The ATF25C functional logic diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the single global bus. The ATF25Cs are straightforward and uniform PLDs. The 24 macrocells are numbered through 23. Each macrocell contains 7 AND gates. All AND gates have 72 inputs. The five lower product terms provide AR, CK, CK2, AR2, and OE. These are: one asynchronous reset and clock per flip-flop, and an output enable. The top 2 product terms are grouped into three sum terms, which are used as shown in the macrocell diagrams. Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share Preset, the next two share Preset, and so on, ending with the last two macrocells sharing Preset 7. The 4 dedicated inputs and their complements use the numbered positions in the global bus as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2 () true and false, flip-flop Q true and false, and the pin true and false. The positions occupied by these signals in the global bus are the six numbers in the bus diagram next to each macrocell. Note:. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATF25Cs. 777G 2/ 5

6 Functional Logic Diagram ATV25C Notes:. Pin 4 and Pin 26 are ground connections and are not required for PLCC, LCC and JLCC versions of ATF25CQ or ATF25CQL, making them compatible with ATV25H and ATV25L as well as ATV25BQ and ATV25BQL pinouts. 2. For DIP package, VCC = P and GND = P3. For, PLCC, LCC and JLCC packages, VCC = P and P2, GND = P33 and P34, and GND2 = P4, P26 (See Note, above). 6 ATF25C Family 777G 2/

7 ATF25C Family Output Logic, Registered () S2 = Terms in S S D/T D/T2 Output Configuration 8 4 Registered (Q); Q2 FB 2 4 () Registered (Q); Q2 FB 8 4 Registered (Q); D/T2 FB S3 Output Configuration S6 Q CLOCK Active Low CK Active High CK P S4 Register Type S7 Q2 CLOCK D CK2 T CK2 P S5 Register 2 Type D T Output Logic, Combinatiorial () S2 = Terms in S5 S S D/T D/T2 X 4 () 4 X 4 4 Output Configuration Combinatorial (8 Terms); Q2 FB Combinatorial (4 Terms); Q2 FB X 4 () 4 () Combinatorial (2 Terms); Q2 FB 4 () 4 Combinatorial (8 Terms); D/T2 FB Note: 4 4. These four terms are shared with D/T. Clock Option Combinatorial (4 Terms); D/T2 FB Note:. These diagrams show equivalent logic functions, not necessarily the actual circuit implementation. 777G 2/ 7

8 Absolute Maximum Ratings* Temperature Under Bias C to +25 C Storage Temperature C to +5 C Junction Temperature...5 C Max Voltage on Any Pin with Respect to Ground...-2.V to +7.V () *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Input Pins with Respect to Ground During Programming...-2.V to +4.V () Programming Voltage with Respect to Ground...-2.V to +4.V () Note:. Minimum voltage is -.6V DC which may undershoot to -2.V for pulses of less than 2 ns. Maximum output pin voltage is V CC +.75V DC which may overshoot to +7.V for pulses of less than 2 ns. DC and AC Operating Conditions Operating Temperature Commercial Industrial Military C - 7 C (Ambient) -4 C - 85 C (Ambient) -55 C - 25 C (Case) V CC Power Supply 5V ± 5% 5V ± % 5V ± % Pin Capacitance f = MHz, T = 25 C () Typ Max Units Conditions C 4 6 pf V = V C OUT 8 2 pf V OUT = V Note:. Typical values for nominal supply voltage. This parameter is only sampled and is not % tested. Test Waveforms and Measurement Levels Output Test Load 8 ATF25C Family 777G 2/

9 ATF25C Family AC Waveforms () Input Pin Clock AC Waveforms () Product Term Clock AC Waveforms () Combinatorial Outputs and Feedback Note:. Timing measurement reference is.5v. Input AC driving levels are.v and 3.V, unless otherwise specified. 777G 2/ 9

10 ATF25C DC Characteristics Symbol Parameter Condition Min Typ Max Units I IL Input Load Current V = -.V to V CC + V µa Output Leakage µa I LO V Current OUT = -.V to V CC +.V I CC I OS Power Supply Current Standby Output Short Circuit Current V CC = MAX, V = GND or V CC f = MHz, Outputs Open V OUT =.5V ATF25C Note:. See I CC versus frequency characterization curves. Com. Ind., Mil. 9 ma 2 ma -2 ma V IL Input Low Voltage M V CC MAX V V IH Input High Voltage 2. V CC +.75 V V OL V OH Output Low Voltage Output High Voltage V = V IH or V IL, V CC = 4.5V V CC = M I OL = 8 ma Com., Ind..5 V I OL = 6 ma Mil..5 V I OH = - µa V CC -.3 V I OH = -4. ma 2.4 ATF25C AC Characteristics - -5 Symbol Parameter Min Max Min Max Units t PD Input to Non-registered Output 5 ns t PD2 Feedback to Non-registered Output 5 ns t PD3 Input to Non-registered Feedback 6 ns t PD4 Feedback to Non-registered Feedback 6 ns t EA Input to Output Enable 5 ns t ER Input to Output Disable 5 ns t EA2 Feedback to Output Enable 5 ns t ER2 Feedback to Output Disable 5 ns t AW Asynchronous Reset Width 4 8 ns t AP Asynchronous Reset to Registered Output 3 8 ns t APF Asynchronous Reset to Registered Feedback 5 ns ATF25C 777G 2/

11 ATF25C ATF25C Register AC Characteristics, Input Pin Clock Symbol Parameter - -5 Min Max Min Max t COS Clock to Output 5.5 ns t CFS Clock to Feedback 2 5 ns t SIS Input Setup Time 2 9 ns t SFS Feedback Setup Time 2 9 ns t HS Hold Time ns t WS Clock Width 3 6 ns t PS Clock Period 8 2 ns F MAXS Internal Feedback /(t SFS + t CFS ) 7 MHz External Feedback /(t + t SIS COS ) MHz No Feedback /(t PS ) 83 MHz t ARS Asynchronous Reset/Preset Recovery Time 5 2 ns Units ATF25C Register AC Characteristics, Product Term Clock Symbol Parameter - -5 Min Max Min Max t COA Clock to Output 5 ns t CFA Clock to Feedback ns t SIA Input Setup Time 2 5 ns t SFA Feedback Setup Time 2 5 ns t HA Hold Time 5 ns t WA Clock Width ns t PA Clock Period 9 5 ns F MAXA Internal Feedback /(t SFA + t CFA ) 58 MHz External Feedback /(t SIA + t COA) MHz No Feedback /(t PS ) 66 MHz t ARA Asynchronous Reset/Preset Recovery Time 2 8 ns Units 777G 2/

12 ICC (µa) STAND-BY I CC VS. SUPPLY VOLTAGE (T A = 25 C) NORMALIZED Icc NORMALIZED I CC VS. TEMP TEMPERATURE (C) ICC (ma) SUPPLY CURRENT VS. PUT FREQUENCY (V CC = 5.V, T A = 25 C) FREQUENCY (MHz) ICC (ma) SUPPLY CURRENT VS. PUT FREQUENCY (V CC = 5.V, T A = 25 C) FREQUENCY (MHz) IOH (ma) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (V OH = 2.4V) IOH (ma) OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (V CC = 5.V, T A = 25 C) VOH (V) Iol (ma) OUTPUT SK CURRENT VS. SUPPLY VOLTAGE (V OL =.5V) IOL (ma) OUTPUT SK CURRENT VS. OUTPUT VOLTAGE (V CC = 5.V, T A = 25 C) ATF25C 777G 2/

13 ATF25C PUT CURRENT (ma) PUT CLAMP CURRENT VS. PUT VOLTAGE (V CC = 5.V, T A = 35 C) PUT VOLTAGE (V) PUT CURRENT (ua) PUT CURRENT VS. PUT VOLTAGE (V CC = 5.V, T A = 25 C) PUT VOLTAGE (V).2 NORMALIZED T PD VS. VCC. NORMALIZED T PD VS. TEMP NORMALIZED T PD...9 NORMALIZED T PD TEMPERATURE (C).3 NORMALIZED T CO VS. VCC. NORMALIZED T CO VS. TEMP NORMALIZED T CO NORMALIZED T CO TEMPERATURE (V) NORMALIZED T PD NORMALIZED T PD VS. VCC NORMALIZED T CO NORMALIZED T SU VS. TEMP TEMPERATURE (C) 3 777G 2/

14 DELTA T PD (ns) DELTA T PD VS. OUTPUT LOADG OUTPUT LOADG (PF) DELTA T CO (ns) DELTA T CO VS. OUTPUT LOADG NUMBER OF OUTPUTS LOADG. DELTA T PD VS. # OF OUTPUT SWITCHG. DELTA T CO VS. # OF OUTPUT SWITCHG DELTA T PD (ns) DELTA TPD (ns) NUMBER OF OUTPUTS SWITCHG NUMBER OF OUTPUTS SWITCHG 4 ATF25C 777G 2/

15 ATF25CL ATF25CL DC Characteristics Symbol Parameter Condition Min Typ Max Units I IL Input Load Current V = -.V to V CC + V µa Output Leakage µa I LO V Current OUT = -.V to V CC +.V I CC I OS Power Supply Current Standby Output Short Circuit Current V CC = MAX, V = GND or V CC f = MHz, Outputs Open V OUT =.5V ATF25CL Note:. See I CC versus frequency characterization curves. Com. Ind., Mil. 2 5 ma 2 ma -2 ma V IL Input Low Voltage M V CC MAX V V IH Input High Voltage 2. V CC +.75 V V OL V OH Output Low Voltage Output High Voltage V = V IH or V IL, V CC = 4.5V V CC = M I OL = 8 ma Com., Ind..5 V I OL = 6 ma Mil..5 V I OH = - µa V CC -.3 V I OH = -4. ma 2.4 ATF25CL AC Characteristics -2 Symbol Parameter Min Max Units t PD Input to Non-registered Output 2 ns t PD2 Feedback to Non-registered Output 2 ns t PD3 Input to Non-registered Feedback 5 ns t PD4 Feedback to Non-registered Feedback 5 ns t EA Input to Output Enable 2 ns t ER Input to Output Disable 2 ns t EA2 Feedback to Output Enable 2 ns t ER2 Feedback to Output Disable 2 ns t AW Asynchronous Reset Width 2 ns t AP Asynchronous Reset to Registered Output 22 ns t APF Asynchronous Reset to Registered Feedback 9 ns 777G 2/ 5

16 ATF25CL Register AC Characteristics, Input Pin Clock Symbol Parameter t COS Clock to Output ns t CFS Clock to Feedback 6 ns t SIS Input Setup Time 4 ns t SFS Feedback Setup Time 4 ns t HS Hold Time ns t WS Clock Width 7 ns t PS Clock Period 4 ns F MAXS Internal Feedback /(t SFS + t CFS ) 5 MHz External Feedback /(t + t SIS COS ) 4 MHz No Feedback /(t PS ) 7 MHz t ARS Asynchronous Reset/Preset Recovery Time 5 ns Min -2 Max Units ATF25CL Register AC Characteristics, Product Term Clock Symbol Parameter t COA Clock to Output 2 ns t CFA Clock to Feedback 6 ns t SIA Input Setup Time ns t SFA Feedback Setup Time 8 ns t HA Hold Time ns t WA Clock Width ns t PA Clock Period 22 ns F MAXA Internal Feedback /(t SFA + t CFA ) 38 MHz External Feedback /(t SIA + t COA) 33 MHz No Feedback /(t PS ) 45 MHz t ARA Asynchronous Reset/Preset Recovery Time 2 ns Min -2 Max Units 6 ATF25CL 777G 2/

17 ATF25CL ICC (µa) STAND-BY I CC VS. SUPPLY VOLTAGE (T A = 25 C) NORMALIZED Icc NORMALIZED I CC VS. TEMP TEMPERATURE (C) ICC (ma) SUPPLY CURRENT VS. PUT FREQUENCY (V CC = 5.V, T A = 25 C) FREQUENCY (MHz) ICC (ma) SUPPLY CURRENT VS. PUT FREQUENCY (V CC = 5.V, T A = 25 C) FREQUENCY (MHz) IOH (ma) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (V OH = 2.4V) IOH (ma) OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (V CC = 5.V, T A = 25 C) VOH (V) OUTPUT SK CURRENT VS. SUPPLY VOLTAGE (V OL =.5V) OUTPUT SK CURRENT VS. OUTPUT VOLTAGE (V CC = 5.V, T A = 25 C) Iol (ma) IOL (ma) G 2/

18 PUT CURRENT (ma) PUT CLAMP CURRENT VS. PUT VOLTAGE (V CC = 5.V, T A = 35 C) PUT VOLTAGE (V) PUT CURRENT (ua) PUT CURRENT VS. PUT VOLTAGE (V CC = 5.V, T A = 25 C) PUT VOLTAGE (V).2 NORMALIZED T PD VS. VCC. NORMALIZED T CO VS. TEMP NORMALIZED T PD...9 NORMALIZED T CO TEMPERATURE (V).3 NORMALIZED T CO VS. VCC.2 NORMALIZED T SU VS. TEMP NORMALIZED T CO NORMALIZED T CO TEMPERATURE (C) NORMALIZED T SU NORMALIZED T SU VS. VCC NORMALIZED T CO NORMALIZED T SU VS. TEMP TEMPERATURE (C) 8 ATF25CL 777G 2/

19 ATF25CL DELTA T PD (ns) DELTA T PD VS. OUTPUT LOADG OUTPUT LOADG (PF) DELTA T CO (ns) DELTA T CO VS. OUTPUT LOADG NUMBER OF OUTPUTS LOADG. DELTA T PD VS. # OF OUTPUT SWITCHG. DELTA T CO VS. # OF OUTPUT SWITCHG DELTA T PD (ns) DELTA TPD (ns) NUMBER OF OUTPUTS SWITCHG NUMBER OF OUTPUTS SWITCHG 9 777G 2/

20 ATF25CQ DC Characteristics Symbol Parameter Condition Min Typ Max Units I IL Input Load Current V = -.V to V CC + V µa I LO Output Leakage Current V OUT = -.V to V CC +.V µa I CC Power Supply Current Standby V CC = MAX, V = GND or V CC f = MHz, Outputs Open ATF25CQ Com. 3 7 ma Ind., Mil ma I OS Output Short Circuit Current V OUT =.5V -2 ma V IL Input Low Voltage M V CC MAX V V IH Input High Voltage 2. V CC +.75 V V OL Output Low Voltage V = V IH or V IL, V CC = 4.5V I OL = 8 ma Com., Ind..5 V I OL = 6 ma Mil..5 V V OH Output High I OH = - µa V CC -.3 V V Voltage CC = M I OH = -4. ma 2.4 Note:. See I CC versus frequency characterization curves. ATF25CQ AC Characteristics -2 Symbol Parameter Min Max Units t PD Input to Non-registered Output 2 ns t PD2 Feedback to Non-registered Output 2 ns t PD3 Input to Non-registered Feedback 5 ns t PD4 Feedback to Non-registered Feedback 5 ns t EA Input to Output Enable 2 ns t ER Input to Output Disable 2 ns t EA2 Feedback to Output Enable 2 ns t ER2 Feedback to Output Disable 2 ns t AW Asynchronous Reset Width 2 ns t AP Asynchronous Reset to Registered Output 22 ns t APF Asynchronous Reset to Registered Feedback 9 ns 2 ATF25CQ 777G 2/

21 ATF25CQ ATF25CQ Register AC Characteristics, Input Pin Clock Symbol Parameter t COS Clock to Output ns t CFS Clock to Feedback 6 ns t SIS Input Setup Time 4 ns t SFS Feedback Setup Time 4 ns t HS Hold Time ns t WS Clock Width 7 ns t PS Clock Period 4 ns F MAXS Internal Feedback /(t SFS + t CFS ) 5 MHz External Feedback /(t SIS + t COS) 4 MHz No Feedback /(t PS ) 7 MHz t ARS Asynchronous Reset/Preset Recovery Time 5 ns Min -2 Max Units ATF25CQ Register AC Characteristics, Product Term Clock Symbol Parameter t COA Clock to Output 2 ns t CFA Clock to Feedback 6 ns t SIA Input Setup Time ns t SFA Feedback Setup Time 8 ns t HA Hold Time ns t WA Clock Width ns t PA Clock Period 22 ns F MAXA Internal Feedback /(t SFA + t CFA ) 38 MHz External Feedback /(t SIA + t COA) 33 MHz No Feedback /(t PS ) 45 MHz t ARA Asynchronous Reset/Preset Recovery Time 2 ns Min -2 Max Units 777G 2/ 2

22 ICC (µa) STAND-BY I CC VS. SUPPLY VOLTAGE (T A = 25 C) NORMALIZED Icc NORMALIZED I CC VS. TEMP TEMPERATURE (C) 4. SUPPLY CURRENT VS. PUT FREQUENCY (V CC = 5.V, T A = 25 C). SUPPLY CURRENT VS. PUT FREQUENCY (V CC = 5.V, T A = 25 C) 2..8 ICC (ma) FREQUENCY (MHz) ICC (ma) FREQUENCY (MHz) IOH (ma) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (V OH = 2.4V) IOH (ma) OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (V CC = 5.V, T A = 25 C) VOH (V) Iol (ma) OUTPUT SK CURRENT VS. SUPPLY VOLTAGE (V OL =.5V) IOL (ma) OUTPUT SK CURRENT VS. OUTPUT VOLTAGE (V CC = 5.V, T A = 25 C) ATF25CQ 777G 2/

23 ATF25CQ PUT CURRENT (ma) PUT CLAMP CURRENT VS. PUT VOLTAGE (V CC = 5.V, T A = 35 C) PUT VOLTAGE (V) PUT CURRENT (ua) PUT CURRENT VS. PUT VOLTAGE (V CC = 5.V, T A = 25 C) PUT VOLTAGE (V).2 NORMALIZED T PD VS. VCC. NORMALIZED T CO VS. TEMP NORMALIZED T PD...9 NORMALIZED T CO TEMPERATURE (V).3 NORMALIZED T CO VS. VCC. NORMALIZED T CO VS. TEMP NORMALIZED T CO NORMALIZED T CO TEMPERATURE (V).2 NORMALIZED T SU VS. VCC.2 NORMALIZED T SU VS. TEMP NORMALIZED T SU...9 NORMALIZED T CO TEMPERATURE (C) G 2/

24 DELTA T PD (ns) DELTA T PD VS. OUTPUT LOADG OUTPUT LOADG (PF) DELTA T CO (ns) DELTA T CO VS. OUTPUT LOADG NUMBER OF OUTPUTS LOADG. DELTA T PD VS. # OF OUTPUT SWITCHG. DELTA T CO VS. # OF OUTPUT SWITCHG DELTA T PD (ns) DELTA TPD (ns) NUMBER OF OUTPUTS SWITCHG NUMBER OF OUTPUTS SWITCHG 24 ATF25CQ 777G 2/

25 ATF25CQL ATF25CQL DC Characteristics Symbol Parameter Condition Min Typ Max Units I IL Input Load Current V = -.V to V CC + V µa I LO Output Leakage Current V OUT = -.V to V CC +.V µa I CC Power Supply Current Standby V CC = MAX, V = GND or V CC f = MHz, Outputs Open ATF25CQL Com. 2 4 ma Ind., Mil. 2 5 ma I OS Output Short Circuit Current V OUT =.5V -2 ma V IL Input Low Voltage M V CC MAX V V IH Input High Voltage 2. V CC +.75 V V OL V OH Output Low Voltage Output High Voltage V = V IH or V IL, V CC = 4.5V V CC = M I OL = 8 ma Com., Ind..5 V I OL = 6 ma Mil..5 V I OH = - µa V CC -.3 V I OH = -4. ma 2.4 ATF25CQL AC Characteristics -25 Symbol Parameter Min Max Units t PD Input to Non-registered Output 25 ns t PD2 Feedback to Non-registered Output 25 ns t PD3 Input to Non-registered Feedback 8 ns t PD4 Feedback to Non-registered Feedback 8 ns t EA Input to Output Enable 25 ns t ER Input to Output Disable 25 ns t EA2 Feedback to Output Enable 25 ns t ER2 Feedback to Output Disable 25 ns t AW Asynchronous Reset Width 5 ns t AP Asynchronous Reset to Registered Output 28 ns t APF Asynchronous Reset to Registered Feedback 25 ns 777G 2/ 25

26 ATF25CQL Register AC Characteristics, Input Pin Clock Symbol Parameter t COS Clock to Output 2 ns t CFS Clock to Feedback 7 ns t SIS Input Setup Time 2 ns t SFS Feedback Setup Time 2 ns t HS Hold Time ns t WS Clock Width 8 ns t PS Clock Period 46 ns F MAXS Internal Feedback /(t SFS + t CFS ) 37 MHz External Feedback /(t SIS + t COS) 3 MHz No Feedback /(t PS ) 62 MHz t ARS Asynchronous Reset/Preset Recovery Time 2 ns Min -25 Max Units ATF25CQL Register AC Characteristics, Product Term Clock Symbol Parameter t COA Clock to Output 22 ns t CFA Clock to Feedback 2 8 ns t SIA Input Setup Time 5 ns t SFA Feedback Setup Time ns t HA Hold Time 2 ns t WA Clock Width 4 ns t PA Clock Period 28 ns F MAXA Internal Feedback /(t SFA + t CFA ) 36 MHz External Feedback /(t SIA + t COA) 27 MHz No Feedback /(t PS ) 36 MHz t ARA Asynchronous Reset/Preset Recovery Time 5 ns Min -25 Max Units 26 ATF25CQL 777G 2/

27 ATF25CQL ICC (µa) STAND-BY I CC VS. SUPPLY VOLTAGE (T A = 25 C) NORMALIZED Icc NORMALIZED I CC VS. TEMP TEMPERATURE (C) 4. SUPPLY CURRENT VS. PUT FREQUENCY (V CC = 5.V, T A = 25 C). SUPPLY CURRENT VS. PUT FREQUENCY (V CC = 5.V, T A = 25 C) 2..8 ICC (ma) FREQUENCY (MHz) ICC (ma) FREQUENCY (MHz) IOH (ma) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (V OH = 2.4V) IOH (ma) OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (V CC = 5.V, T A = 25 C) VOH (V) Iol (ma) OUTPUT SK CURRENT VS. SUPPLY VOLTAGE (V OL =.5V) IOL (ma) OUTPUT SK CURRENT VS. OUTPUT VOLTAGE (V CC = 5.V, T A = 25 C) G 2/

28 PUT CURRENT (ma) PUT CLAMP CURRENT VS. PUT VOLTAGE (V CC = 5.V, T A = 35 C) PUT VOLTAGE (V) PUT CURRENT (ua) PUT CURRENT VS. PUT VOLTAGE (V CC = 5.V, T A = 25 C) PUT VOLTAGE (V).2 NORMALIZED T PD VS. VCC. NORMALIZED T PD VS. TEMP NORMALIZED T PD...9 NORMALIZED T PD TEMPERATURE (C).3 NORMALIZED T CO VS. VCC. NORMALIZED T CO VS. TEMP NORMALIZED T CO NORMALIZED T CO TEMPERATURE (V).2 NORMALIZED T SU VS. VCC.2 NORMALIZED T SU VS. TEMP NORMALIZED T SU NORMALIZED T CO TEMPERATURE (C) 28 ATF25CQL 777G 2/

29 ATF25CQL DELTA T PD (ns) DELTA T PD VS. OUTPUT LOADG OUTPUT LOADG (PF) DELTA T CO (ns) DELTA T CO VS. OUTPUT LOADG NUMBER OF OUTPUTS LOADG DELTA T PD (ns) DELTA T PD VS. # OF OUTPUT SWITCHG NUMBER OF OUTPUTS SWITCHG DELTA T CO (ns) DELTA T CO VS. # OF OUTPUT SWITCHG NUMBER OF OUTPUTS SWITCHG G 2/

30 Ordering Information t PD (ns) t COS (ns) Ext. f MAXS (MHz) Ordering Code Package Operation Range ATF25C-JC 44J Commercial 5 52 ATF25C-5JC 44J Commercial ( C to 7 C) ATF25C-5JI 44J Industrial (-4 C to 85 C) ATF25C-5KM/883 ATF25C-5NM/ M4X M3X 44K 44L 44K 44L Military/883C (-55 C to 25 C) Class B, Fully Compliant Military/883C (-55 C to 25 C) Class B, Fully Compliant 2 4 ATF25CL-2JC 44J Commercial ( C to 7 C) ATF25CL-2JI 44J Industrial (-4 C to 85 C) ATF25CL-2KM/883 ATF25CL-2NM/ M4X M3X 2 4 ATF25CQ-2JC ATF25CQ-2PC ATF25CQ-2JI ATF25CQ-2PI ATF25CQ-2GM/883 ATF25CQ-2KM/883 ATF25CQ-2NM/ M2X M4X M3X 44K 44L 44K 44L 44J 4P6 44J 4P6 4D6 44K 44L 4D6 44K 44L Military/883C (-55 C to 25 C) Class B, Fully Compliant Military/883C (-55 C to 25 C) Class B, Fully Compliant Commercial ( C to 7 C) Industrial (-4 C to 85 C) Military/883C (-55 C to 25 C) Class B, Fully Compliant Military/883C (-55 C to 25 C) Class B, Fully Compliant 3 ATF25CQL 777G 2/

31 ATF25CQL Ordering Information (Continued) t PD (ns) t COS (ns) Ext. f MAXS (MHz) Ordering Code Package Operation Range ATF25CQL-25JC ATF25CQL-25PC ATF25CQL-25JI ATF25CQL-25PI ATF25CQL-25GM/883 ATF25CQL-25KM/883 ATF25CQL-25NM/ M2X M4X M3X 44J 4P6 44J 4P6 4D6 44K 44L 4D6 44K 44L Commercial ( C to 7 C) Industrial (-4 C to 85 C) Military/883C (-55 C to 25 C) Class B. Fully Compliant Military/883C (-55 C to 25 C) Class B, Fully Compliant Note: *SMD numbers are. Using C Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the I to the C device (7 ns C = ns I ) and derate power by 3%. Package Type 4D6 44J 44K 4P6 44L 4-pin,.6" Wide, Ceramic, Dual Inline Package (Cerdip) 44-lead, Plastic J-leaded Chip Carrier OTP (PLCC) 44-lead, Ceramic J-leaded Chip Carrier (JLCC) 4-pin,.6" Wide, Plastic, Dual Inline Package OTP (PDIP) 44-pad, Ceramic Leadless Chip Carrier (LCC) 777G 2/ 3

32 Packaging Information 4D6 Cerdip Dimension in Millimeters and (Inches) Controlling dimension: Inches MIL-STD-835 D-5 CONFIG A (Glass Sealed) 53.9(2.9) 5.82(2.4) P 5.49(.6) 2.95(.5) 5.72(.225) MAX 48.26(.9) REF.27(.5)M SEATG PLANE 5.8(.2) 3.8(.25) 2.54(.)BSC.65(.65).4(.45) 5.7(.62) 5.(.59).78(.7).38(.5).66(.26).36(.4).46(.8).2(.8) º~ 5º REF 7.8(.7) MAX 4// R 2325 Orchard Parkway San Jose, CA 953 TITLE 4D6, 4-lead (.6" Wide), Non-windowed, Ceramic Dual Inline Package (Cerdip) DRAWG NO. 4D6 REV. A 32 ATF25CQL 777G 2/

33 ATF25CQL 44J PLCC.4(.45) X 45 P NO. IDENTIFIER.4(.45) X 45.38(.25).9(.75) B E E B D2/E2 e D D A A2 A.5(.2)MAX 45 MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes:. This package conforms to JEDEC reference MS-8, Variation AC. 2. Dimensions D and E do not include mold protrusion. Allowable protrusion is."(.254 mm) per side. Dimension D and E include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is.4" (.2 mm) maximum. SYMBOL M NOM MAX NOTE A A A2.58 D D Note 2 E E Note 2 D2/E B B e.27 TYP /4/ R 2325 Orchard Parkway San Jose, CA 953 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWG NO. 44J REV. B 777G 2/ 33

34 44K JLCC.4 X 45 D D.89 X 45 C b E E b E2 e A2 A.2 C A D2 c SEATG PLANE COMMON DIMENSIONS (Unit of Measure = mm).25(.635) RADIUS MAX (3X) SYMBOL M NOM MAX NOTE A A A D D D E E E b b c e.27 TYP Note : Refer to MIL-STD-835C-J R 2325 Orchard Parkway San Jose, CA 953 TITLE DRAWG NO. 9/8/ 44K, 44-lead, Non-windowed, Ceramic J-leaded Chip Carrier (JLCC) 44K A REV. 34 ATF25CQL 777G 2/

35 ATF25CQL 4P6 PDIP D P E A SEATG PLANE L e B B A Notes: C E eb º ~ 5º REF. This package conforms to JEDEC reference MS-, Variation AC. 2. Dimensions D and E do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed.25 mm (."). COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL M NOM MAX NOTE A A.38 D Note 2 E E Note 2 B B.4.65 L C eb e 2.54 TYP 9/28/ R 2325 Orchard Parkway San Jose, CA 953 TITLE 4P6, 4-lead (.6"/5.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWG NO. 4P6 REV. B G 2/

36 44L LCC Dimensions in Millimeters and (Inches) Controlling dimension: Inches MIL-STD-835 C-5 6.8(.662) 6.26(.64) 2.74(.8) 2.6(.85) 6.8(.662) 6.26(.64) 2.4(.95).9(.75) P.4(.55).4(.45) 2.3(.8).4(.55) DEX CORNER.635(.25).38(.5) X (.5) BSC.35(.2).78(.7) RADIUS.737(.29).533(.2).27(.5) TYP.2(.4) X (.5) BSC 2.6(.85).65(.65) 4// R 2325 Orchard Parkway San Jose, CA 953 TITLE 44L, 44-pad (.6" Wide), Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) DRAWG NO. 44L REV. A 36 ATF25CQL 777G 2/

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