FOR many years, there have been prospects to realize

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1 3392 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 24, NO. 9, SEPTEMBER 2006 All-Optical Multiple Logic Gates With XOR, NOR, OR,andNAND Functions Using Parallel SOA-MZI Structures: Theory and Experiment Joo-Youp Kim, Jeung-Mo Kang, Tae-Young Kim, and Sang-Kook Han, Member, IEEE Abstract The authors have proposed, simulated, and experimentally demonstrated all-optical multiple logic gates using two parallel semiconductor optical amplifier (SOA)-Mach Zehnder interferometer (MZI) structures that enable simultaneous operations of various logic functions of XOR, NOR, OR, and NAND. The proposed scheme, which is optimized by adjusting the optical gain and phase differences in SOA-MZI structures with creative and systematic method, has great merits to achieve the reshaped output pulses with high extinction ratio and enable the high-speed operation at over 10 Gb/s through performance enhancement of SOAs. Its validity is confirmed through simulation and experiments at 2.5 and 10 Gb/s, respectively. Index Terms All-optical logic gate, Mach Zehnder interferometer (MZI), NAND, NOR, OR, semiconductor optical amplifier (SOA), XOR. I. INTRODUCTION FOR many years, there have been prospects to realize all-optical computers using digital optical elements. As compared with electronic gates, optical elements lack packing density because the interaction length of electrons is much shorter than that of photons. Nevertheless, it is very practical to aim at simple optical-signal processing in telecommunication networks. The all-optical processing is especially attractive in high-capacity core networks where we want to avoid inefficient optoelectronic conversion. All-optical logic devices required in optical add-drop multiplexers (OADMs) and optical cross connects (OXCs) perform networking functions, such as addressing and header recognition, data encoding and encryption, pattern matching, etc. [1]. In order to realize the devices, various configurations of optical logic gates have been reported that utilize the ultrafast nonlinear properties of the semiconductor optical amplifier (SOA) [2], including from the single SOA structure using cross gain modulation (XGM), to interferometric structures such as the terahertz optical asymmetric demultiplexer (TOAD) [3] and the ultrafast nonlinear interferometer (UNI) [4], etc. These schemes have been shown to have some advantages, but they are difficult to control or construct, and polarization states or random phase changes are critical for their output performance. Among interferometric structures, the SOA-Mach Zehnder interferometer (MZI) structure using XPM is the most promising candidate due to its attractive Manuscript received February 3, 2006; revised May 26, The authors are with Department of Electrical and Electronic Engineering, Yonsei University, Seoul , Korea ( Digital Object Identifier /JLT features of low-energy requirement, simplicity, compactness by integration capability, and stability. In addition, it has the merits of high extinction ratio (ER), regenerative capability, high-speed operation, and low chirp [1]. So far, all-optical AND and XOR gates using an SOA-MZI structure have been investigated [5] [7], and an all-optical NAND gate using an SOA-MZI structure has not yet been reported. The all-optical AND gate is one of the fundamental logic gates because it is able to perform the bit-level functions such as address recognition, packet-header modification, and data-integrity verification [5]. The all-optical XOR gate is a key technology to implement primary systems for binary address and header recognition, binary addition and counting, decision and comparison, encoding and encryption, and pattern matching. This gate has been demonstrated at 10 [8], 20 [9], and 40 Gb/s [10] using SOA-MZI differential schemes that have been deployed to overcome the strong speed limitations imposed by the SOA s slow recovery time. Recently, all-optical logic data processing circuits using multiple gates have been demonstrated to perform specific logic operations that include a half adder using the TOAD, a semiconductor laser amplifier in a loop mirror (SLALOM), and SOA-based devices, a full adder based on the TOAD, counter, or parity checker [5]. Since all logical operations can be performed using logical combinations of NOR and/or NAND gates, future high-capacity optical communication networks will require integrated alloptical logic gates with NOR and NAND functions. In this paper, we propose, simulate, and experimentally demonstrate all-optical multiple logic gates with XOR, NOR, OR, and NAND functions using two parallel SOA-MZI structures at 2.5 and 10 Gb/s, respectively. The proposed design is optimized by adjusting the optical gain and phase differences in SOA-MZI structures with a creative and systematic method in order to obtain the reshaped output pulses with maximum ER. The XOR gate of the proposed scheme is derived from the previously known structure [7]. II. THEORETICAL APPROACH The schematic diagram of the proposed all-optical multiple logic gates is shown in Fig. 1. P in is the optical power level of the continuous wave (CW) probe input signal entering into each arm of two parallel SOA-MZIs. P AL, P AH, P BL, and P BH represent the optical power levels corresponding to the low- and high-logic states of pump input signals (P A and P B ), respectively. In the upper SOA-MZI for the XOR function, the levels of (P in + P AL ) and (P in + P AH ) experience the /$ IEEE

2 KIM et al.: ALL-OPTICAL MULTIPLE LOGIC GATES USING PARALLEL SOA-MZI STRUCTURES 3393 Fig. 1. Schematic diagram of all-optical multiple logic gates with XOR, NOR, OR,andNAND functions using two parallel SOA-MZI structures. optical gains defined as G 1L and G 1H at the first SOA (SOA1), respectively. Similarly, the levels of (P in + P BL ) and (P in + P BH ) undergo the optical gains of G 2L and G 2H at the second SOA (SOA2), respectively. Each of the low- (P in G 1L ) and high- (P in G 1H ) logic state levels via SOA1 is interfered with in combination with each of the low- (P in G 2L ) and high- (P in G 2H ) logic state levels via SOA2. XPM occurs mainly at the high-logic state level of the pump input signal passing through the SOAs. Therefore, if either SOA experiences the high-logic state, then the optical phase shift difference by XPM is largest between both arms of MZI; this means that the XOR function can be performed. When φ 1 is defined as the optical phase difference between two arms of the upper MZI, the optical power levels [P O1 AB (φ 1 )] of the probe output signal interfered at the upper MZI can be expressed as P O1 AB (φ 1 )=P in ( G1A + G 2B +2 G 1A G 2B cos(φ 1 + φ XPM1 AB ) ). (1) The subscripts of A and B mean logic states (X) ofp AX and P BX, respectively. φ XPM1 AB represents the relative optical phase shift difference by XPM between both arms of MZI. We have reported the novel automatic control technique that the optical gain and phase differences inside SOA-MZI wavelength converters are controlled with the probe output power levels [11], [12]. According to the method, if we know six representative probe output power levels of P O1 AB (φ 1 ) varying by φ 1, the unknown values of P in G 1L, P in G 2L, P in G 1H, and P in G 2H will be easily obtained using (1). The six levels are P O1 LL (φ 1 =0), P O1 LL (φ 1 = π), P O1 HL (φ 1 =0), P O1 HL (φ 1 = π), P O1 LH (φ 1 =0), and P O1 LH (φ 1 = π) existing in two probe output pulses of P O1 AB (φ 1 =0) and P O1 AB (φ 1 = π). After operating (1), including the above six levels, four relations are expressed as P in G 1L = P in G 2L = ( PO1 LL (φ 1 =0)± ) 2 P O1 LL (φ 1 = π) /4 ( PO1 LL (φ 1 =0) ) 2 P O1 LL (φ 1 = π) /4 uppersign : G 1L G 2L lowersign : G 1L G 2L (2) P in G 1H = P in G 2L +(P O1 HL (φ 1 =0) +P O1 HL (φ 1 = π)) /2 P in G 2H = P in G 1L +(P O1 LH (φ 1 =0) +P O1 LH (φ 1 = π)) /2. (3) In addition, we specially define φ XPM1 HL as the relative optical phase shift by XPM between SOA1 and SOA2 when A (passing through SOA1) and B (passing through SOA2) are the high- and low-logic states, respectively. φ XPM1 LH is defined as that when A and B are the low- and high-logic states, respectively. Therefore, each of φ XPM1 HL and φ XPM1 LH can be expressed by operating (1) (3) with two probe output power levels (P O1 HL (φ 1 = π), P O1 LH (φ 1 = π)) at φ 1 = π [13]: φ XPM1 HL [ ] =cos 1 PO1 HL (φ 1 = π) P in G 1H P in G 2L 2P in G1H G 2L φ XPM1 LH =cos 1 [ PO1 LH (φ 1 = π) P in G 1L P in G 2H 2P in G1L G 2H (4) ]. (5) AsshowninFig.1,inthelowerSOA-MZIforNOR/OR function, the levels of (P in + P AL + P BL ), (P in + P AL + P BH ),

3 3394 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 24, NO. 9, SEPTEMBER 2006 (P in + P AH + P BL ), and (P in + P AH + P BH ) experience the optical gains defined as G 3LL, G 3LH, G 3HL, and G 3HH at the third SOA (SOA3), respectively. The CW level of P in undergoes the optical gain of G 4 at the fourth SOA (SOA4). Each of the low- (P in G 3LL ) and high- (P in G 3LH, P in G 3HL, and P in G 3HH ) logic state levels via SOA3 is interfered with the CW level (P in G 4 ) via SOA4. Generally, since P AL and P AH are almost equal to P BL and P BH, respectively, P in G 3LH is identical to P in G 3HL if we consider the same gain transfer characteristics of SOA1 and SOA2. Thus, two high-logic state levels of P in G 3LH (= P in G 3HL ) and P in G 3HH can have different quantity of XPM. When φ 2 is defined as the optical phase difference between two arms of the lower MZI, the optical power levels [P O2 AB (φ 2 )] of the probe output signal interfered at the lower MZI can be expressed as P O2 AB (φ 2 )=P in (G 3AB + G 4 +2 G 3AB G 4 ) cos(φ 2 + φ XPM2 AB ). (6) Like at the upper SOA-MZI, if we know six representative probe output power levels of P O2 AB (φ 2 ) varying by φ 2, the unknown values of P in G 3LL, P in G 3LH (= P in G 3HL ), P in G 3HH, and P in G 4 will be easily obtained using (6). The six levels are P O2 LL (φ 2 =0), P O2 LL (φ 2 = π), P O2 LH (φ 2 = 0)(= P O2 HL (φ 2 = 0)), P O2 LH (φ 2 = π)(= P O2 HL (φ 2 = π)), P O2 HH (φ 2 =0), and P O2 HH (φ 2 = π) existing in two probe output pulses of P O2 AB (φ 2 =0) and P O2 AB (φ 2 = π). Since P in G 3LH is identical to P in G 3HL, P O2 LH (φ 2 ) is equal to P O2 HL (φ 2 ). After operating (6), including the above six levels, four relations are expressed as ( P in G 3LL = PO2 LL (φ 2 =0)± 2/4 P O2 LL (φ 2 =π)) P in G 4 = ( PO2 LL (φ 2 =0) P O2 LL (φ 2 =π)) 2/4 uppersign : G 3LL G 4 lowersign : G 3LL G 4 (7) P in G 3LH = P in G 4 +(P O2 LH (φ 2 =0) +P O2 LH (φ 2 =π))/2 P in G 3HH = P in G 4 +(P O2 HH (φ 2 =0) +P O2 HH (φ 2 =π))/2. (8) Like at the upper SOA-MZI, we define φ XPM2 HL as the relative optical phase shift by XPM between SOA3 and SOA4 when each logic state of A and B, which are to pass through SOA3, is the high and low or the low and high; both cases are the same because of P O2 HL (φ 2 )=P O2 LH (φ 2 ). φ XPM3 HH is defined as when both A and B are the high-logic states. Therefore, each of φ XPM2 HL and φ XPM2 HH can be expressed by operating (6) with two probe output levels of P O2 HL (φ 2 =0) (= P O2 LH (φ 2 = 0)) and P O2 HH (φ 2 =0)at φ 2 =0[13]: φ XPM2 HL [ ] =cos 1 PO2 HL (φ 2 =0) P in G 3HL P in G 4 2P in G3HL G 4 φ XPM2 HH =cos 1 [ PO2 HH (φ 2 =0) P in G 3HH P in G 4 2P in G3HH G 4 (9) ]. (10) On the basis of (1) and (6), we impose the optical gain conditions, such as P in G 1L = P in G 2L = a, P in G 1H = P in G 2H = b, P in G 3LL = c, P in G 3LH = P in G 3HL = d, P in G 3HH = e, and P in G 4 = f in order to simplify the expressions. Thus, as shown in Table I, ideal all-optical multiple logic gates with XOR, NOR, OR, and NAND functions can be obtained by optimizing the conditions for the optical gain and phase difference, including φ XPM1 AB and φ XPM2 AB. The conditions can be easily sought through adjusting the bias currents of SOAs and the control voltage (or current) of optical phase shift means including π phase shifter and summarized in Table I [13]. The maximum ERs at XOR and OR gates can be achieved when (φ 1 + φ XPM1 LL ), (φ 1 + φ XPM1 HH ), and (φ 2 + φ XPM2 LL ) are close to π, evenif φ XPM1 LL, φ XPM1 HH and φ XPM2 LL are not close to 0. Also, the high ER at NOR gate can be realized when (φ 2 + φ XPM2 LH ), (φ 2 + φ XPM2 HL ), and (φ 2 + φ XPM2 HH ) approach π even if φ XPM2 LH, φ XPM2 HL, and φ XPM2 HH do not approach π. The NAND function is performed by summing the XOR and NOR gates. Thus, XOR, NOR, and NAND gates can be simultaneously operated. Considering the principle of operation, the proposed design cannot be applied to the Michelson interferometer structure. Additionally, its operating speed depends on the recovery time of the SOAs. III. OPTIMIZATION METHOD To obtain maximum ERs at the proposed all-optical multiple logic gates, we should optimize the optical gain differences and the φ XPM1 AB and φ XPM2 AB between SOAs in both MZIs. They can be easily optimized by adjusting the bias currents of SOAs. The optimization procedure is proposed as below. First, various values of the bias currents are arranged for SOA1, SOA2, SOA3, and SOA4 within the range of their maximum values. Second, six levels of P O1 LL (φ 1 =0), P O1 LL (φ 1 = π), P O1 LH (φ 1 =0), P O1 LH (φ 1 = π), P O1 HL (φ 1 =0), and P O1 HL (φ 1 = π) are measured according to all the combination of the bias currents for two SOAs in the upper MZI. At the lower MZI, six levels of P O2 LL (φ 2 =0), P O2 LL (φ 2 = π), P O2 LH (φ 2 =0) (= P O2 HL (φ 2 =0)), P O2 LH (φ 2 = π)(= P O2 HL (φ 2 = π)), P O2 HH (φ 2 =0), and P O2 HH (φ 2 = π) are also measured with the same method. Third, for upper MZI, the values of P in G 1L, P in G 2L, P in G 1H, P in G 2H, φ XPM1 HL, and φ XPM1 LH are calculated, and then, the combination of the bias currents satisfying the optical gain conditions of P in G 1L = P in G 2L = P in G 3L and P in G 1H = P in G 2H = P in G 3H are found in order to obtain the optimized XOR gate. For the lower MZI, the values of P in G 3LL, P in G 3LH (= P in G 3HL ), P in G 3HH, P in G 4, φ XPM2 HL, and φ XPM2 HH are calculated, and the combination of the bias currents satisfying the optical gain conditions of P in G 3LH = P in G 4 P in G 3HH and those of P in G 3LL = P in G 4 and P in G 3LH P in G 3HH are found in order to obtain the optimized NOR and OR gates, respectively. As remarked in previous section, the optimized XOR gate or the optimized NOR and OR gates do not definitely depend on the absolute values of φ XPM1 AB or φ XPM2 AB because the values of (φ 1 + φ XPM1 AB ) and (φ 2 + φ XPM2 AB ) are more meaningful. Nevertheless, it is better that the values of φ XPM1 AB and φ XPM2 AB

4 KIM et al.: ALL-OPTICAL MULTIPLE LOGIC GATES USING PARALLEL SOA-MZI STRUCTURES 3395 TABLE I OPTIMIZED TRUTH TABLE FOR THE XOR, NOR, OR, AND NAND GATES OF THE PROPOSED SCHEME Fig. 2. Experimental setup at 2.5 Gb/s. PC: polarization controller. arecloserto0orπ, as shown in Table I, to obtain the most optimized XOR, NOR, and OR gates. The optimized NAND gate is achieved by summing the optimized XOR and NOR gates. As a result of the optimization procedure above, the optimized all-optical multiple logic gates can produce the reshaped probe output pulses with maximum ER. IV. EXPERIMENT AND SIMULATION AT 2.5 Gb/s Fig. 2 shows the experimental setup, which is not monolithically integrated but has the hybrid form combined with various discrete optical elements and equipment, in order to verify the proposed scheme at 2.5 Gb/s, even if the proposed design can be applied to both types. The wavelength of probe input signal (P in ) is nm, and those of the two pump input signals (P A and P B ) entering into the two parallel MZIs are and nm, respectively. The pump input signals into both MZI are directly modulated to 2.5 Gb/s being programmed to repeated pattern of 0011 by the pulse pattern generator (PPG). Since the modulated electric signal to make P B passes through a time delay line for half-period delay of pulse, as shown in Fig. 2, P A and P B can make the logical combinations [ 00 (LL), 01 (LH), 10 (HL), and 11 (HH)]. Each P A and P B is divided into two signals through 3-dB splitters. At the upper MZI, one of the divided P A s enters directly into the upper arm of the upper MZI, and one of the divided P B s enters into lower arm. In front of the lower MZI, the rest of the divided P A s and P B s are combined, again by the 3-dB combiner. Thus, P A plus P B make the logical signal corresponding to OR, and then, they can be either inverted (NOR) or noninverted (OR) via the lower MZI by the optical phase difference of φ 2 =0or π, respectively. The probe (P in ) and pump [P AH (= P BH ) and P AL (= P BL )] input power levels into both MZIs are fixed to 0.1, 0.15, and 0.01 mw for the experiment, respectively, and 0.4, 0.5, and 0.01 mw for the simulation, respectively.

5 3396 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 24, NO. 9, SEPTEMBER 2006 Fig. 3. XOR: Probe output power levels and the calculated values of φ XPM1 HL and φ XPM1 LH, all of which are varying according to the bias currents injected into (a) SOA1 and (b) SOA2 in the case of the fixed bias currents of (a) SOA2 =90mA and (b) SOA1 =90mA at φ 1 = π. The examples of the optimization procedure described in the previous section are concretely shown below through the experiment. First, in the process of seeking the optimized XOR gate through the experiment, Fig. 3(a) shows the measured levels of P O1 LL (φ 1 = π), P O1 LH (φ 1 = π), P O1 HL (φ 1 = π), and P O1 HH (φ 1 = π) and the calculated values of φ XPM1 HL and φ XPM LH, all of which are varying according to the bias current injected into SOA1 in the case that the fixed bias current of 90 ma is injected into SOA2. Also, Fig. 3(b) shows those which are varying according to the bias current injected into SOA2 in the case that the fixed current of 90 ma is injected into SOA1. As shown in Fig. 3(a) and (b), the increased bias currents of SOA1 and SOA2 mainly increase the φ XPM1 HL and φ XPM1 LH, respectively. Even if the φ XPM1 HL and φ XPM1 LH are smaller than π, the probe output pulse [P O1 AB (φ 1 = π)] can achieve a very high ER performance by very low low-logic state levels Fig. 4. NOR: Probe output power levels and the calculated values of φ XPM2 HL and φ XPM2 HH, all of which are varying according to the bias currents injected into (a) SOA3 and (b) SOA4 in the case of the fixed bias currents of (a) SOA4 =60mA and (b) SOA3 = 100 ma at φ 2 =0. [P O1 LL (φ 1 = π) and P O1 HH (φ 1 = π)] because the values of (φ 1 + φ XPM1 LL ) and (φ 1 + φ XPM1 HH ) are close to π, as remarked in the previous section. Second, in the process of seeking the optimized NOR gate through the experiment, Fig. 4(a) shows the measured levels of P O2 LL (φ 2 =0), P O2 LH (φ 2 =0), P O2 HL (φ 2 =0), and P O2 HH (φ 2 =0) and the calculated values of φ XPM2 HL and φ XPM2 HH, all of which are varying according to the bias current injected into SOA3 in the case that the fixed bias current of 60 ma is injected into SOA4. Also, Fig. 4(b) shows those that are varying according to the bias current injected into SOA4 in the case that the fixed current of 100 ma is injected into SOA3. As shown in Fig. 4(a) and (b), the increased bias current of SOA3 only increases the φ XPM2 HL and φ XPM2 HH. Even though the φ XPM2 HL and φ XPM2 HH are smaller than π, the probe output signal [P O1 AB (φ 1 = π)] can achieve a very high ER performance because the values

6 KIM et al.: ALL-OPTICAL MULTIPLE LOGIC GATES USING PARALLEL SOA-MZI STRUCTURES 3397 Fig. 5. Experiment (2.5 Gb/s): Pump input pulses of (a) P A,(b)P B,and probe output pulses of (c) XOR, (d)nor, (e)or, and (f) NAND gates in the case of (c) (f) SOA1 =90mA, SOA2 =90mA, (d), (f) SOA3 = 100 ma, SOA4 =60 ma, (e) SOA3 = 100 ma, SOA4 = 100 ma at (c) φ 1 = π, (d) φ 2 =0,(e)φ 2 = π, and (f) φ 1 = π and φ 2 =0. of (φ 2 + φ XPM1 HL )(= (φ 2 + φ XPM2 LH )) and (φ 2 + φ XPM2 HH ) approach π, as remarked in the previous section. According to the repeated optimization procedures as the above, the optimum combination of bias currents is determined as 90 and 90 ma for SOA1 and SOA2, respectively, and as 100 ma and either 60 (NOR) or 100 ma (OR) for SOA3 and SOA4, respectively, when considering that the highest ERs are obtained. As these bias current combinations are applied, Fig. 5 shows the measured pulses of (a) P A and (b) P B as pump input signals and those of (c) P O1 AB (φ 1 = π), (d)p O2 AB (φ 2 =0), (e) P O2 AB (φ 2 = π), and (f) P O3 AB as probe output signals from the XOR, NOR, OR, and NAND gates, respectively [13]. The output pulse of P O3 AB is produced by sum mixing P O1 AB (φ 1 = π) and P O2 AB (φ 2 =0).Fig.5 shows that all output pulses from the XOR, NOR, OR, and NAND gates can have a high ER performance of better than 10 db. Through simulation, the optimization procedure yields the optimum bias current combination of 200 and 200 ma for SOA1 and SOA2, respectively, and either 250 (NOR) or 180 ma (OR) and either 80 (NOR) or 180 ma (OR) for SOA3 and SOA4, respectively. As a result of the simulation under these bias current combinations, Fig. 6 shows the pulses of (a) P A and (b) P B as pump input signals and those of (c) P O1 AB (φ 1 = π), (d) P O2 AB (φ 2 =0),(e)P O2 AB (φ 2 = π), and (f) P O3 AB as probe output signals from the XOR, NOR, OR, and NAND gates, respectively. Fig. 6 demonstrates that all output pulses from the XOR, NOR, OR, and NAND gates have a very high ER performance of better than 15 db. It is shown that the probe output pulses are also reshaped because they are derived from optical phase modulations at MZIs. Fig. 6. Simulation (2.5 Gb/s): Pump input pulses of (a) P A,(b)P B, and probe output pulses of (c) XOR, (d)nor, (e)or, and (f) NAND gates in the case of (c), (f) SOA1 = 200 ma, SOA2 = 200 ma, (d), (f) SOA3 = 250 ma, SOA4 =80 ma, (e) SOA3 = 180 ma, SOA4 = 180 ma at (c) φ 1 = π, (d) φ 2 =0,(e)φ 2 = π, and (f) φ 1 = π and φ 2 =0. V. E XPERIMENT AND SIMULATION AT 10 Gb/s Fig. 7 shows the experimental setup that is not monolithically integrated but has the hybrid form combined with various discrete optical elements and equipment, in order to demonstrate the proposed scheme at 10 Gb/s. The wavelength of probe input signal (P in ) is nm, and those of two pump input signals (P A and P B ) entering into two parallel MZIs are and nm, respectively. Each P A and P B is externally modulated by two Mach Zehnder modulators (MZM1 and MZM2) at Gb/s (OC192/STM64) with nonreturn-to-zero (NRZ) patterns of pseudorandom binary sequences (PRBSs) from PPG. The reason why external modulation is performed with MZMs is that the operation speeds of the used distributed feedback laser diodes (DFBLDs) are not fast enough to use at about 10 Gb/s. A time delay line in front of MZM2 is needed for logical combinations [ 00 (LL), 01 (LH), 10 (HL), and 11 (HH)] of P A and P B. The probe (P in ) and pump [P AH (= P BH ) and P AL (= P BL )] input power levels into both MZI are fixed to 0.4, 0.95, and 0.05 mw for the experiment, respectively, and 0.4, 0.7, and 0.01 mw for the simulation, respectively. The erbium-doped fiber amplifiers (EDFAs) are used to amplify the pump input signals weakened by insertion loss of the MZM, and the optical bandpass filters (OBPFs) are done to remove the ASE noise. As shown in the previous section, we seek the optimum optical gain and phase differences including φ XPM1 AB and φ XPM2 AB between SOAs in both MZIs in order to

7 3398 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 24, NO. 9, SEPTEMBER 2006 Fig. 7. Experimental setup at 10 Gb/s. PC: polarization controller. Fig. 8. Experiment (10 Gb/s): Pump input pulses of (a) P A,(b)P B, and probe output pulses of (c) XOR, (d)nor, (e)or, and (f) NAND gates in the case of (c), (f) SOA1 = 180 ma, SOA2 = 190 ma, (d), (f) SOA3 = 190 ma, SOA4 = 130 ma, (e) SOA3 = 190 ma, SOA4 = 200 ma at (c) φ 1 = π, (d) φ 2 =0,(e)φ 2 = π, and (f) φ 1 = π and φ 2 =0. maximize ER. By experiment through the optimization procedure, as described in Section III, we obtain the optimum bias current combination of 180 and 190 ma for SOA1 and SOA2, respectively, and 190 and either 130 (NOR) or 200 ma (OR)for SOA3 and SOA4, respectively. As a result of the experiment under these bias current combinations, Fig. 8 shows the measured pulses of (a) P A and (b) P B as pump input signals and those of (c) P O1 AB (φ 1 = π),(d)p O2 AB (φ 2 =0),(e)P O2 AB (φ 2 = π), and (f) P O3 AB as probe output signals from the XOR, Fig. 9. Simulation (10 Gb/s): Pump input pulses of (a) P A,(b)P B, and probe output pulses of (c) XOR, (d)nor, (e)or, and (f) NAND gates in the case of (c), (f) SOA1 = 143 ma, SOA2 = 200 ma, (d) (f) SOA3 = 150 ma, SOA4 =80 ma, (e) SOA3 = 150 ma, SOA4 = 200 ma at (c) φ 1 = π, (d) φ 2 =0,(e)φ 2 = π, and (f) φ 1 = π and φ 2 =0. NOR, OR, and NAND gates, respectively. Through simulation, the optimization procedure yields the optimum bias current combination of 143 and 200 ma for SOA1 and SOA2, respectively, and 150 and either 80 (NOR) or 200 ma (OR) for SOA3 and SOA4, respectively. As a result of simulation under these bias current combinations, Fig. 9 shows the pulses of (a) P A and (b) P B as pump input signals and those of (c) P O1 AB (φ 1 = π), (d) P O2 AB (φ 2 =0),(e)P O2 AB (φ 2 = π), and (f) P O3 AB

8 KIM et al.: ALL-OPTICAL MULTIPLE LOGIC GATES USING PARALLEL SOA-MZI STRUCTURES 3399 as probe output signals from the XOR, NOR, OR, and NAND gates, respectively. Figs. 8 and 9 demonstrate that all output pulses from the XOR, NOR, OR, and NAND gates have a very high ER performance of better than 15 db. The reason why Fig. 9 has the higher ER than Fig. 5 that is gained from the experiment at 2.5 Gb/s is that both ERs of P A and P B on the experiment at 10 Gb/s are higher than those at 2.5 Gb/s: enough to achieve more XPM differences. Also, the probe output pulses have also been reshaped because they are derived from optical phase modulations of XPM at the MZIs. Thus, in terms of performance and integration capability, the proposed scheme can be superior to other all-optical logic gates that have been demonstrated by different methods. VI. CONCLUSION In this paper, we have proposed, simulated, and experimentally demonstrated all-optical multiple logic gates with XOR, NOR, OR, and NAND functions using two parallel SOA-MZI structures that enable simultaneous operations of various logical functions. Since each one of all-optical XOR, NOR, OR, and NAND logic gates can be applied to various networking functions, and all logical operations can be performed using logical combinations of NOR and/or NAND gates, the proposed all-optical multiple logic gates will play an important role in future high-capacity optical communication networks. The proposed design is optimized by adjusting the optical gain and phase differences in SOA-MZI structures with creative and systematic method in order to obtain maximum ER. The proposed scheme has great merits to generate output pulses that have been reshaped with a high ER performance of better than 15 db and enables all-optical logic operations at a high speed of over 10 Gb/s through performance enhancement of SOAs. In the future, using the proposed method, we will progress our research for concrete applications, such as parity checker and shift registers. Mach Zehnder interferometer, Electron Lett., vol. 38, no. 21, pp , Oct [9] T. Fjelde, D. Wolfson, A. Kloch, B. Dagens, A. Coquelin, I. Guillemot, F. Gaborit, F. Poingt, and M. Renaud, Demonstration of 20 Gb/s alloptical logic XOR in integrated SOA-based interferometric wavelength converter, Electron Lett., vol. 36, no. 22, pp , Oct [10] R. P. Webb, R. J. Manning, G. D. Maxwell, and A. J. Poustie, 40 Gb/s all-optical XOR gate based on hybrid-integrated Mach Zehnder interferometer, Electron Lett., vol. 39, no. 1, pp , Jan [11] J. Y. Kim and S. K. Han, Novel automatic control for the optimum optical gain and phase difference in SOA-MZI wavelength converter, in Conf. Lasers and Electro-Optics/Quantum Electronics and Laser Science (CLEO/QELS), Baltimore, MD, May 2005, pp [12], Novel automatic control for the optimum optical gain and phase differences in SOA-MZI wavelength converter: Theory and experiment, Opt. Commun., vol. 261, no. 1, pp , May [13] J.-Y. Kim, S.-K. Han, and S. Lee, All-optical multiple logic gates using parallel SOA-MZI structures, in Proc. 18th Annu. Meeting IEEE Lasers and Electro-Optics Society (IEEE LEOS), Sydney, Australia, Oct. 2005, pp Joo-Youp Kim was born in Seoul, Korea, on January 9, He received the B.S. and M.S. degrees in electronic engineering from Sungkyunkwan University, Seoul, in 1993 and 1995, respectively, and the Ph.D. degree in electrical and electronic engineering from Yonsei University, Seoul, in He joined Samsung Electronics in 1995 and has been engaged in research and development of optical disk drives. His current research interests include wavelength converters, all-optical logic gates, optical control methods, and optical disk drives. Jeung-Mo Kang received the B.S. and M.S. degrees in electrical and electronic engineering from Yonsei University, Seoul, Korea, in 1999 and 2001, respectively, where he is currently working toward the Ph.D. degree in electrical and electronic engineering. His current research interests include wavelength converter and optical switching devices based on SOAs and optical systems. REFERENCES [1] H. Soto, J. D. Topomondzo, D. Erasme, and M. Castro, All-optical NOR gates with two and three input logic signals based on cross-polarization modulation in a semiconductor optical amplifier, Opt. Comm., vol. 218, no. 4, pp , Apr [2] K. E. Stubkjaer, Semiconductor optical amplifier-based all-optical gates for high-speed optical processing, IEEE J. Select. Top. Quantum Electron., vol. 6, no. 6, pp , Nov./Dec [3] H. J. S. Dorren, G. D. Khoe, and D. Lenstra, All-optical switching of an ultrashort pulse using a semiconductor optical amplifier in a Sagnac-interferometric arrangement, Opt. Commun., vol. 205, no. 4 6, pp , May [4] C. Schubert, J. Berger, U. Feiste, R. Ludwig, C. Schmidt, and H. G. Wever, 160-Gb/s all-optical demultiplexing using a gaintransparent ultrafast-nonlinear interferometer (GT-UNI), IEEE Photon. Technol. Lett., vol. 13, no. 5, pp , May [5] J. H. Kim, Y. T. Byun, Y. M. Jhon, S. Lee, D. H. Woo, and S. H. Kim, All-optical half adder using semiconductor optical amplifier based devices, Opt. Commun., vol. 218, no. 4 6, pp , Apr [6] T. Houbavlis, K. E. Zoiros, G. Kanellos, and C. Tsekrekos, Performance analysis of ultrafast all-optical Boolean XOR gate using semiconductor optical amplifier-based Mach Zehnder Interferometer, Opt. Comm., vol. 232, no. 1 6, pp , Mar [7] Q. Wang, G. Zhu, H. Chen, J. Jaques, J. Leuthold, A. B. Piccirilli, and N. K. Dutta, Study of all-optical XOR using Mach Zehnder interferometer and differential scheme, IEEE J. Quantum Electron., vol. 40, no. 6, pp , Jun [8] H. Chen, G. Zhu, Q. Wang, J. Jaques, J. Leuthold, A. B. Piccirilli, and N. K. Dutta, All-optical logic XOR using differential scheme and Tae-Young Kim received the B.S. and M.S. degrees in electrical and electronic engineering from Yonsei University, Seoul, Korea, in 1998 and 2000, respectively, where he is currently working toward the Ph.D. degree in electrical and electronic engineering. His current research interests include the architecture design and analysis of the passive optical network (PON) systems and its applications. Sang-Kook Han (M 95) received the B.S. degree in electronic engineering from Yonsei University, Seoul, Korea, in 1986 and the M.S. and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, in 1988 and 1994, respectively. From 1994 to 1996, he worked at System IC Lab, Hyundai Electronics, where he was involved in the development of optical devices for telecommunications. He is currently a Professor at the Department of Electrical and Electronic Engineering, Yonsei University. His current research interests include optical device/systems for communications, optical switching, and microwave photonics technologies.