New Reed Solomon Encoder Design Using Galois Subfield Multiplier

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1 New Reed Solomon Encoder Design Using Galois Subfield Multiplier Hyeong-Keon An*, Jin-Young Kim** *Dept. of Information & Communications Engineering, Tongmyong University of Information Technology, Busan 68-7, KOREA, Tel: , Fax: , **Dept. of Mechatronics Engineering, Tongmyong University of Information Technology; Busan 68-7, KOREA, Tel: , Fax: , Abstract-A new RS(Reed Solomon) Encoder design method, using Galois Subfield GF(2') Multiplier, is describe& The Encoder is designed using Erasure Correction method. Here New Multiplier in GF(2&) is designed, which is simpler and faster than the classical GF(2') Multiplier, using the Galois Subfield GF(2') Multiplier. Keywords: RS(Reed Solomon), Syndrome, Encoder, Decoder, Erasure, Galois Field(GF). Introduction.. Reed Solomon coding theory is very famous well known nonbinary error correction method for Digital. Electronic Devices (Consumer and Communication products.)[3]. In this paper, new RS(Reed Solomon) Encoder design method is proposed using Erasure correction algorithm of RS decoder[2]. Especially new Multiplier in GF(2') is implemented using its Galois Subfield GF(2') Multiplier. The new Subfield Multiplier is much. simpler and faster than before, So More efficient RS Encoder design is Possible[. In chapter 2, we briefly described RS(Reed Solomon) ECC method For example we describe how to calculate syndromes, design RS encoder & decoder. Also Galois Field product, addition (subtraction) methods are briefly described with table and Diagram. In chapter 3, we show the New RS Encoder design method is described. Here Erasure Correction method of RS decoder is used. Example is showing the resultant syndromes are zeros as expected. In CDP(Compact Disc Player), 4 erasure values are the desired 4 Parities of its RS Encoder. In chapter 4, the new Multiplier, in CF(27, design method is described. Inversing and Dividing can be done using Multiplier only. Definitely the new Multiplier, using Galois subfield GF(2') Multiplier, is much more efficient than the direct GF(2*) Multiplier In chapter 5 conclusions are made. Gate counts Comparison between the new Multiplier' and the old one is shown. Also Brief algorithms how the Inversing and Dividing is done using Galois Multiplier are described. 2. Reed Solomon coding theory An RS(Recd Solomon) codes are based on finite fields, often called Galois fields. 4 n symbols?. unchanged data. I parity In CDP, RSC(32,28), on GF(Z8) field, codes is used and up to 2 symbol errors can be corrected. An RS code with 8bit symbols will use a Galois field GF(2*), consisting of 256 symbols. Thus every possible 8bit value is in the field. The order in which the symbols appear depends on the generator polynomial. This polynomial is used in a simple iterative algorithm to generate each element of the field. Different polynomials 'will generate different fields. For instance, the generator polynomial for DVB is p(x)=+x2+x3+w4+x8. This can be given the shorthand 285, from the binary value of the coefficients t[3]. As an example, take the Gatois field GF(24) using 4bit symbok, polynomial is the p(x)=l+x3+x?. The Galois field consists of 6 symbols shown in Table

2 Table I. 5s! Power a a4 a5 a6 a7 as ' I ai2 ai3 a4 ibols in GF(24)field Polynomial a +az +a3 +a3 +a +a3 I +U +a2 +a3 +a +a2' +a +a2 +cl3 +a2 +U ' +a3 +a2 +a3 +a +a +az +a2 +U' 4 tuple or binary ' ' I olio Note that each element is the previous multiplied by a. By setting p(a)=o, then'a4= + (substituting a into the polynomial p(x)). Thus in the above table is substituted with +, then US=(+Q3U, = a + a4=+a+pr3 a6=a = a+ 2 + a4=+at+d+cr3 a7=aa6 =CL + d + d + a4 =li-a+a2 Feedback - Input Galois Galois addition Q Fig.2 RS(n, k) encoder circuit. m bi; resister I select input or parity symbols The encoder shown in Fig. 2 is a 2t tap shift register, where each register is m bits wide[6]. The multiplier coefficients go to g(2t-) are coefficients of the RS generator polynomial. The coefficients are fixed, which can be used to simplify the multipliers if required. The first step in decoding the received symbols is to determine the data syndrome. In this paper, for finding Erasure values, syndrome ' ' calculator shown in Fig.3 is used[4]. General Rs decoder design method is not covered in this Papem]. and so on. The RS encoder is easy the bit. The encoder acts to divide the polynomial represented by the k message symbols d(x) by the RS generator polynomial g(x). This generator polynomial is not the same as the Galois Field generator polynomial, but is derived from it. Received Syndrome Si c x(n-k)*d(x)/g(4 = q(x) + r(x)/p(x) Fig.3 U Syndrome calculator of RS codec. The term x(n-k) is a constant power. of x, which is simply a shift upwards n-k places of all the polynomial coefficients in d(x). It happens as part of the shifting process in the architecture below. The remainder after the division r(x) becomes the parity. By concatenating the parity symbols on to the end of the k message symbols, an n coefficient polynomial is created which is exactly divisible 3. New Reed Solomon Encoder Design When we design a Reed Solomon Encoder, normally we use the Encoder shown 'in Fig.2.But VLSI WW of this method is very complex, because there are separate RS Encoder and Decoder 'md Encoder itself is not so simple in HW wise also

3 Here to save the Encoding HW(Hardware) we briefly describe the encoding hardware,which is the Erasure corrector of the RS Decoder. So Encoder is part of the RS decoder and we neednot design the separate Encoder saving the Encoder HW [2]. < Encoding Steps>. Assume arbitrary parity values ( Normally,. assumeo) :P,P, Z,...,~ al ~ 2. Using K syndromes calculated by the cct in Fig. 3, Erasure Decoder get the K Erasure Values. 3. K Erasure values are added to the assumed Parities and the result values Are True Parities. The New Encoder Block Diagram is shown in Fig. 4. (i =,,2,3) are parities and D, Cj=4,5,...,3) are data bytes. If D, i3=3,4,..., 3) =, D3, = a =I, Find the Correct Parities P,( i=o to. 3). <Sol> Parity positions are known so this is the Erasure Correction case. Because all assumed Parities are and using given data bytes, we calculate syndromes. s, = C(aO)= S = c(a )= a $ = qa2 j= cl62 S3=C(a3)=a9... (). - Now we setup following equations to find 4 erasure values Eo, E,, Ez, El. Eo+Ei+Ez+E3 = So Eo+Ela+E~u2+E3a3=S EotEla2+E2u4+E3a6=~ Eo+Ela3+Ep6+E3a9=~...(2), I, e. equations () and (2), I a U a - so s -7 Syndrome Generator U= a4 c6 s, = s, mlf Calculator /- 7 a as U~~ aly a5 u3 a49 a45 a am a U3l d2 P I * A : Do, D,, *.., DM (Data) B : P ~,P,,..., ~ ~ (Error - Parities) c : Sh SI,..., Sk- D : E*EI,..., Ek.l (Erasure Values) E : PwP,..-,Pk-l (Correct Parities) Fig.4 Block Diagram of New RS Encoder <Example> In RS(32,28) code system of GF(2 ),.let s assume all parities. The codeword polynomial C(x)= Po+ PIX +Pzxz tp3x3 +D4x4 t...+ D3,x3, where Pi ala4 u45.a44 alol u93 So From Fig.4 and Equation (3), we find correct Pasrities as follows. TF I Pi,i=O to 3 =[ Ei + Initial {i=o to 3) Pi ]= a6,a O L

4 Using this Correct Parities, we find all syndro'mes Si, j=o to 3 are zeros and this is correct. 4. New GF(2') Multiplier design in this section, we describe how to simplify the multiplier using GaIois subfield[. The Multiplier is most important HW in RS Codec and Division can be done using Multiplication only. Using the Multiplier in this section RS Encoder can be simplified and faster. In Fig. 5 we draw the New Multiplier block diagram [ 3. ai converter equation is, for example Bq= ZI + Z7... (6) All the other bk 's can be got in the same way. Now A, B, C in GF(2') can be expressed as follows. A = a++alp B= bo+blp c =CO+ e$ AndC=A*B...(7) Here %, a,, bo, b,, col c- E GF(24), pand y EGF(~~) also p"p+u, then co. c are represented as in (8) [ ] : Co=aobo+a lbry C=aobl+albo+albl.,.(S) At A2;4b 6 62 ;4b Multiplier Core In GF(24) field E L c2 ~ ~ ( 2 ~ To GF(Z~) This is the desired multiplication core formula for GF(2') elements using GF(Z4) elements. The y multiplier is calculated as follows. Suppose that element A=ao+alyfa2~+a3$. Then ya=aoy+ai~+az~~a~y'=a~+a~~~a~~+(a~+a~ ( Since y4$ +), So The circuit is shown in Fig6. Also The circuit for CO, CI can be drawn using the y multiplier, mutiplier, and adder in GFQ4) field. Fig.5 Block Diagram of New Multiplier using Sub Field GF(23 T- GF(2') to GF(2') is processed as follows. Let ak is in GF(2') field as (bo, bl,..., b,), it can be expressed as at= a + bp where a and b is in GF(z4) field and p is in GF(2*). Here a and b are (zo,z~,z~,z~) and (r4,q,a,z7) respectively. All b,, 3 (j=o to 7) are in GF(2) = (,l). This means CY^ 34 ( z+ BZ~+~ ) $, y~gf(23 and y4 = $+I (GF(Z4) Primitive Polynomial). Then, Zo= ba+bl+bs Zl= bl+bj+bs Zz= b+b,+b6 Z,= b!+b,+b4+btj Zq= bi+bz+h3+b5+b6+b7 Zg= bz+bs+bs Zs= bl+b+b3+b4+b5+b6 Z7= b,+b3+b,+b5...( 5) In the same way, From (5), we find GF(Z4) to GF(2*) Fig.6 y Multiplier circuit <Example) Let ~=~~=(), ~=a*=() in GF(28). Find A.3 using Sub Field GF(24) element operation. A=%+alp, B=b+b$. Then al=d and bo=2,bl=a3 in GF(Z4) using Equation (5). Now from equation (S), Co=ar24+9y = a9+a4y = CL' using the circuit in Fig.6. Also CI=a2(a6+3)+a4 = a5 using

5 equation (8). Upto now, we only used GF(Z4) operation. Now to change into GF(2*) vector expression use equation (6). Then C=(b,,i= to 7)=() =ai3 in GF(2 ). This is the correct result of a5ma8=(r. 5. Conclusions With the implementation of the multiplier, the dividerand the inversion circuit over GF(2 ) by using the subfield GF(Z4), the idea presented in the paper simplies the circuit and performs high speed operation by decreasing the number of logic gates [. Also RS encoder can be implemented using the circuit of Erasure correction.rs decoder. This means we don t need separate RS encoder and decoder or RS codec in digital AV I Communication devices. So implementing the RS codec is just implementing RS decoder including RS erasure decoding circuit, resutting in greately reducing RS codec HW circuitry[ References [l]. US patent number , Operational Method and Apparatus over GF(27 using a Subfield GF(2mn), Man-young Lee, Hyeong-Keon An et al., 993 Jul. 3 [23. Hyeong-Keon An, TS Joo et al, The New RS Ecc Codec For Digital Audio and Video, IEEE CES Conference paper, PP2-5,992 [3]. Lee Man Young, BCH coding and Reed-Solomon Coding theory, 99, Minumsa(Daewoo Academic Press). [4]. Sunghoon Kwon and Hyunchul Shin, Anareaefficient VLSI architecture of Reed-Solomon decoderiencoder for digital VCRs, IEEE Transactions on Consumer Electronics, Vol. 43, No.4, Nov. 997 [5]. Kwang Y.Liu, Architecture for VLSI design of Reed-Solomon Decoders, IEEE Transactions on Computers. VoI.33, No.2, Feb. 984 [6].Hsu, I.K., I.S.Reed, The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp s Bit-Serial Multiplier Algorithm, IEEE Trans. On Computer, Vl.C-33, N., pp.96-9(984)

B. Cyclic Codes. Primitive polynomials are the generator polynomials of cyclic codes.

B. Cyclic Codes. Primitive polynomials are the generator polynomials of cyclic codes. B. Cyclic Codes A cyclic code is a linear block code with the further property that a shift of a codeword results in another codeword. These are based on polynomials whose elements are coefficients from