ELEC3227/4247 Mid term Quiz2 Solution with explanation

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1 ELEC7/447 Mid term Quiz Solution with explanation Ang Man Shun Department of Electrical and Electronic Engineering, University of Hong Kong Document creation date : This document explain the solution of linear block code, cyclic code, BCH code and RS code. It is suggest to read this document after revision. Q1. Linear Code C={000000,010101,101010,111111} n = length of code = 6 k = length of message = Explanation : the number of possible message is related to the length of message. Since the message here is binary, so the number of possible message = k Now number of possible message = 4, so k = Now we have a (6,) linear block code, so the generator matrix G has the following form P I ] G = [ 6 P = [ ; ] And since GH T = 0, thus H T has the following form. H T = [ I P T ]

2 And in this case GH T = [ P 4 I ] [I 4 4 P 4 T ] = P P = 0 Because it is binary, so subtraction is same as addition, thus H T T = [ I P ] After obtaining the matrix G and H, construct the syndrome as s = rh T T = ( c + e)h = ch T + eh T = mgh T + eh T = eh T Now since e is a vector with only only one 1s. So s = rh T s = eh T = [ ]H T = i t h row of H And by comparing the s and rows of H we can find where is the error bits. Q.Cyclic Code Step. 1. Compute the error detector logic gate pattern, which is equal to the remainder of x n g (x). The answer here is 1011, which correspond to x 4 x x x 1. The error detector logic pattern thus is [TFTT], make sure the order of the AND gate match the expression! 1

Step. Draw the decoder. In general, the decoder consists of three parts : 1) The shift register (the uppermost part) ) The division circuit (the middle part).

3 Step. Draw the decoder. In general, the decoder consists of three parts : 1) The shift register (the uppermost part) ) The division circuit (the middle part). The connection to the register of the division circuit is determined by the coefficient of g ( x ) ) The error detector AND gate, the AND gate input logic pattern should match the step 1 solution.

Step. Compute syndrome The received codeword r is fired into the whole circuit bit by bit and the following figure show the computation of the process.

4 Step. Compute syndrome The received codeword r is fired into the whole circuit bit by bit and the following figure show the computation of the process. In general there are three phase in the process, the first phase is the process of filling the unfilled register. The second phase is the phase when there is external input (from r ) and internal input (from the feedback of the last register). The last phase is when there is no external input but only internal.

5 The error is detected when logic of the register match the error detector. At that moment the AND gate will fire a 1 to correct the content in the shift register. 4

6 Q. BCH Code Step 1. Obtain the receiver polynomial r ( x ), where the coefficients are determined by the received codeword. In here, r (x) = x + x 5 + x 14 Step. Compute the syndrome as S i = r(α i ). i). Comput S 1, S,... S t according to the number of detectable error t. If t = 1, it means the code can detect at most 1 error. And in this case we only need to compute S 1. If t =, it means the code can detect at most errors. And in this case we need to compute S 1 S S S 4. If t =, it means the code can detect at most errors. And in this case we need to compute S 1 S S S 4 S 5 S 6. In this question t = so we need to determine S 1 up to S 6 ii) Compute S i = r(α i ) iii) When the power (index) of with the helps of the table for simplification. α exceed the range [ 0, n ], add or subtract n until the index fall within the range [ 0, n ]. iv) There is a short cut for BCH code, that is S k = ( S k ) 5

7 Step. Compute the error location polynomial as σ (x) Error location polynomial has the following form It is a t order polynomial, and thus σ (x) = 1 + σ 1 x + σ x σ t xt σ (x) = 0 should have t roots. Recall that t is the number of detectable error (detectability), so the order of the error location polynomial is related to such detectability of the code. 6

8 The coefficients of the error location polynomial is obtained by solving Newton s identities by Peterson s method and it has different form for different t : When t = 1, it can detect at most 1 error σ 1 = S 1 σ (x) = 1 + σ 1 x When t =, it can detect at most errors σ 1 = S 1 σ = S S 1 + S1 σ (x) = 1 + σ 1 x + σ x When t =, it can detect at most errors σ 1 = S 1 S +S σ = S +S σ = S 1 + S + S 1 σ σ (x) = 1 + σ 1 x + σ x + σ x In this problem, t =, so polynomial for this problem is σ (x) = 1 + σ 1 x + σ x + σ x, and the error location 7

9 Step 4. Find the error position and correct the error We have a n bit codeword, but we count the monomial order from 0, 1,, up to n 1, so k th bit is error σ (α n (k 1) ) = 0 After checking all the σ (α i ) : σ (α 1 ) = 0 σ (α 10 ) = 0 σ (α 1 ) = 0 th 15 bit is error th 6 bit is error th bit is error 8

10 Step 5. Chien s Searching Circuit The Chien s Searching circuit is the hardware implementation of step 4. Since we need to compute multiplication in step 4, so Chien s searching circuit is basically a multiplication circuit, with the coefficient equal to the coefficients in the error location polynomial σ (x). Since t = in this problem, so σ (x) = 1 + σ 1 x + σ x + σ x register content of equal to the coefficients σ 1, σ, σ, and we have the i) Write down the register content Refer to the table obtained from the Galois Field σ 1 = α 7 = 1101, so the content of the 4 register are σ = α 9 = 0101 σ = α 6 = , so the content of the 4 register are , so the content of the 4 register are ii) Find the connection pattern between the register The connection pattern between the register is determined by the expression α i β = α i (b 0+ b α b α + b α ) = (b0α i + b α 1+i 1 + b α +i + b α +i ) Where coefficient of b i is the connection pattern to the register. Now in order to simplify α i, α 1+i, α +i, α +i, we need to apply the minimal polynomial Φ ( x ) by solving Φ ( α i ) = 0, Φ ( α i+1 ) = 0, Φ ( α i+ ) = 0, Φ ( α i+ ) = 0 9

In this problem, after applying the Φ : Φ ( α 4 ) = 0 Thus for the 1st part of the circuit : α 4 = 1 + α α 1 β = α 1 (b 0+ b α 1 1 + b α + b α ) = b α 1 0 + b α 1 + b α + b α4 = b 0 α + b α 1 + b α +

11 In this problem, after applying the Φ : Φ ( α 4 ) = 0 Thus for the 1st part of the circuit : α 4 = 1 + α α 1 β = α 1 (b 0+ b α b α + b α ) = b α b α 1 + b α + b α4 = b 0 α + b α 1 + b α + b (1 + α ) = b + (b 0 + b )α + b α 1 + b α Therefore the 1st part of the circuit, which the connection is the coefficient of α i is Now the second part of the circuit : α β = α (b 0+ b α b α + b α ) = b α 0 + b α 1 + b α 4 + b α5 Since Φ ( α 4 ) = 0 α 4 = 1 + α, so α 5 = α + α = b α 0 + b α 1 + b (1 + α ) + b (α + α ) = b + ( b + b )α + ( b 0 + b )α + b 1 α 10

12 So the diagram is : Now the third part of the circuit : α β = α (b 0+ b α b α + b α ) = b α 0 + b α b α 5 + b α6 α 4 = 1 + α α 5 = α + α α 6 = α + α = b α 0 + b 1 (1 + α ) + b (α + α ) + b (α + α ) = b 1 + ( b 1 + b )α + ( b + b )α + ( b 0 + b )α 11

The overall circuit The overall circuit is as shown as follows Q4. Reed Solomon Code Step 1. Obtain the receiver polynomial r ( x ), where the coefficients are determined by the received codeword.

13 The overall circuit The overall circuit is as shown as follows Q4. Reed Solomon Code Step 1. Obtain the receiver polynomial r ( x ), where the coefficients are determined by the received codeword. Step. Compute the syndrome S i = r(α i ), i = 1,,,4 (t= for this problem) Step. Compute the error location polynomial as σ (x) = 1 + σ 1 x + σ x where S S +S S σ 1 = S +S S and σ = S +S S 1 S S +S 1 1

14 Step 4. Find the error position. After checking all the σ (α i ) : Step 5. Find the error magnitude σ (α 1 ) = 0 β 1 = α 5 σ (α ) = 0 β = α6 e 1, by solving S 1 = e 1 β 1 + e β S = e 1 β 1 + e β Step 6. Correct the received codeword END of document 1

Error Correction Review

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