EE382V: System-on-a-Chip (SoC) Design

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1 EE82V: SystemonChip (SoC) Design Lecture EE82V: SystemonaChip (SoC) Design Lecture Operation Scheduling Source: G. De Micheli, Integrated Systems Center, EPFL Synthesis and Optimization of Digital Circuits, McGraw Hill, 2. Additional sources: Notes by Kia Bazargan, Notes by Rajesh Gupta, UCSD, Andreas Gerstlauer Electrical and Computer Engineering University of Teas at Austin Lecture : Outline The scheduling problem Case analysis Unconstrained scheduling ASAP and ALAP schedules Resource constrained (RC) scheduling List scheduling Time constrained (TC) scheduling Forcedirected scheduling Advanced scheduling problems Chaining Pipelining EE82V: SoC Design, Lecture G. De Micheli 2 2 A. Gerstlauer

2 EE82V: SystemonChip (SoC) Design Lecture Scheduling Circuit model: Sequencing graph Cycletime is given Operation delays epressed in cycles Scheduling: Determine the start times for the operations Satisfying all the sequencing (timing and resource) constraint Goal: Determine area/latency tradeoff EE82V: SoC Design, Lecture G. De Micheli Eample < n TIME 2 8 TIME < TIME TIME n EE82V: SoC Design, Lecture G. De Micheli 2 A. Gerstlauer 2

3 EE82V: SystemonChip (SoC) Design Lecture Operation Scheduling Input: Sequencing graph G(V, E), with n vertices Cycle time Operation delays D = {d i : i=..n} Output: Schedule determines start time t i of operation v i. Latency = t n t. Goal: determine area / latency tradeoff Classes: Nonhierarchical and unconstrained Latency constrained Resource constrained Hierarchical EE82V: SoC Design, Lecture R. Gupta G. De Micheli Simplest Method All operations have bounded delays All delays are in cycles: Cycletime is given No constraints no bounds on area Goal: Minimize latency EE82V: SoC Design, Lecture G. De Micheli 2 A. Gerstlauer

4 EE82V: SystemonChip (SoC) Design Lecture Min Latency Unconstrained Scheduling Simplest case: no constraints, find min latency Given set of vertices V, delays D and a partial order > on operations E, find an integer labeling of operations : V Z such that: t i = (v i ) t i t j d j (v j, v i ) E and = t n t is minimum Solvable in polynomial time Bounds on latency for resource constrained problems ASAP algorithm used: topological order EE82V: SoC Design, Lecture R. Gupta G. De Micheli 7 ASAP Schedules Schedule v at t = While (v n not scheduled) Select v i with all scheduled predecessors Schedule v i at t i = ma {t j d j }, v j being a predecessor of v i Return t n 2 < EE82V: SoC Design, Lecture R. Gupta G. De Micheli 8 2 A. Gerstlauer

5 EE82V: SystemonChip (SoC) Design Lecture ALAP Schedules Schedule v n at t n =l While (v not scheduled) Select v i with all scheduled successors Schedule v i at t i = min {t j d j }, v j being a succecessor of v i 2 < EE82V: SoC Design, Lecture R. Gupta G. De Micheli 9 Remarks ALAP solves a latencyconstrained problem Latency bound can be set to latency computed by ASAP algorithm Mobility Defined for each operation Difference between ALAP and ASAP schedule Slack on the start time EE82V: SoC Design, Lecture G. De Micheli 2 A. Gerstlauer

6 EE82V: SystemonChip (SoC) Design Lecture Eample Operations with zero mobility: { v, v 2, v, v, v } Critical path Operations with mobility one: { v, v 7 } Operations with mobility two: { v 8, v 9, v, v } < TIME TIME 2 TIME TIME < n n EE82V: SoC Design, Lecture G. De Micheli Lecture : Outline The scheduling problem Unconstrained scheduling Resource constrained (RC) scheduling Eact formulations ILP Hu s algorithm Heuristic methods List scheduling Time constrained (TC) scheduling Advanced scheduling problems EE82V: SoC Design, Lecture G. De Micheli 2 2 A. Gerstlauer

7 EE82V: SystemonChip (SoC) Design Lecture Scheduling under Resource Constraints Classical scheduling problem Fi area bound minimize latency (MLRCS) Minimum latency resource constrained scheduling The amount of available resources affects the achievable latency Dual problem: Fi latency bound minimize resources (MRLCS) Minimum resources latency constrained scheduling Assumption: All delays bounded and known EE82V: SoC Design, Lecture G. De Micheli MLRCS Given a set of ops V with integer delays D a partial order on the operations E upper bounds { a k ; k =, 2,, n res } on resource usage Find an integer labeling : V Z such that: t i = ( v i ), t i t j d j for all i,j s.t. (v j, v i ) E, {v i T(v i ) = k and t i l < t j d j } a k for all types k =,2,,n res and steps l and t n is minimum Intractable problem EE82V: SoC Design, Lecture G. De Micheli 2 A. Gerstlauer 7

8 EE82V: SystemonChip (SoC) Design Lecture ILP Formulation Binary decision variables X = { il, i =,2,. n; l =,2,, λ } il is TRUE only when operation v i starts in step l of the schedule ( i.e. l = t i ) λ is an upper bound on latency Start time of operation v i : Σ l l. il EE82V: SoC Design, Lecture G. De Micheli ILP Constraints Operations start only once Σ il = i =, 2,, n Sequencing relations must be satisfied t i t j d j t i t j d j for all (v j, v i ) є E Σ l il Σ l jl d j for all (v j, v i ) є E Resource bounds must be satisfied Simple case (unit delay) Σ l il a k k =,2, n res ; for all l i:t(v i )=k EE82V: SoC Design, Lecture G. De Micheli 2 A. Gerstlauer 8

9 EE82V: SystemonChip (SoC) Design Lecture Start Time vs. Eecution Time For each operation v i, only one start time If d i =, then the following questions are the same: Does operation v i start at step l? Is operation v i running at step l? But if d i >, the two questions should be formulated as: Does operation v i start at step l? Does il = hold? l Is operation v i running at step l? Does the following hold?? im ml d i EE82V: SoC Design, Lecture K. Bazargan G. De Micheli 7 Operation v i Still Running at Step l? Is v 9 running at step? Is 9, 9, 9, =? v 9 v 9 v 9 9, = 9, = 9, = Note: Only one (if any) of the above three cases can happen To meet resource constraints, we have to ask the same question for ALL steps, and ALL operations of that type EE82V: SoC Design, Lecture K. Bazargan G. De Micheli 8 2 A. Gerstlauer 9

10 EE82V: SystemonChip (SoC) Design Lecture Operation v i Still Running at Step l? Is v i running at step l? Is i,l i,l... i,ldi =? ld i ld i ld i... l... l l v i l v i l v i l i,l = i,l = i,ldi = EE82V: SoC Design, Lecture K. Bazargan G. De Micheli 9 ILP Formulation of MLRCS Constraints: Unique start times: Sequencing (dependency) relations must be satisfied t i j Resource constraints l j Objective: min c T t t = start times vector, c = cost weight (e.g., [... ]) When c = [... ], c T t = j i l, i,,, n il t d ( v, v ) E l. l. im it : ( v ) k ml d i i a k, k,, n l. l EE82V: SoC Design, Lecture K. Bazargan G. De Micheli 2 nl l res il, l jl d l,, j 2 A. Gerstlauer

11 EE82V: SystemonChip (SoC) Design Lecture ILP Eample < Resource constraints 2 ALUs; 2 Multipliers a = 2; a 2 = 2 Singlecycle operation d i = for all i n EE82V: SoC Design, Lecture G. De Micheli 2 ILP Eample Assume = First, perform ASAP and ALAP (we can write the ILP without ASAP and ALAP, but using ASAP and ALAP will simplify the inequalities) 2 v v v7 v9 < v v2 v v8 v v 2 v v v v2 v v7 v8 v v vn v vn v9 < v EE82V: SoC Design, Lecture K. Bazargan G. De Micheli 22 2 A. Gerstlauer

12 EE82V: SystemonChip (SoC) Design Lecture ILP Eample: Unique Start Times Without using ASAP and ALAP values: , 2,,,2 2,2,2, 2,,, 2,, Using ASAP and ALAP:... EE82V: SoC Design, Lecture K. Bazargan G. De Micheli 2, 2,,2,,, 7,2 8, 9,2,2 7, 8,2 9, 8, 9, ILP Eample: Dependency Constraints Using ASAP and ALAP, the nontrivial inequalities are: (assuming unit delay for and ) 2. 2.,2 9,2.., 9, n,, n, 7,2 9, ,, 9,2,2 8, 7, , 8,2,2 7,2 9,, ,2 8,, 7, 9,, EE82V: SoC Design, Lecture K. Bazargan G. De Micheli 2 2 A. Gerstlauer 2

13 EE82V: SystemonChip (SoC) Design Lecture ILP Eample: Resource Constraints Resource constraints (assuming 2 adders and 2 multipliers),2,, 9,2,2 9,, 2,,2,, Objective: Since = and sink has no mobility, any feasible solution is optimum, but we can use the following anyway: Min n, 2. n,2. n,. n, 9,,,2, EE82V: SoC Design, Lecture K. Bazargan G. De Micheli 2, 7,2 7, 8, 8,2 8, ILP Eample: Solution TIME 2 TIME 2 < TIME 7 8 TIME 9 n EE82V: SoC Design, Lecture G. De Micheli 2 2 A. Gerstlauer

14 EE82V: SystemonChip (SoC) Design Lecture MRLCS Dual ILP formulation Minimize resource usage under latency constraint Additional constraint Latency bound must be satisfied Σ l l nl λ Resource usage is unknown in the constraints Resource usage is the objective to minimize EE82V: SoC Design, Lecture G. De Micheli 27 MRLCS ILP Eample TIME 2 TIME 2 < TIME 7 8 TIME 9 Cost function Multiplier area = ALU area = Objective function: a a 2 n EE82V: SoC Design, Lecture G. De Micheli 28 2 A. Gerstlauer

15 EE82V: SystemonChip (SoC) Design Lecture ILP Solving Use standard ILP packages Transform into LP problem Advantages Eact method Others constraints can be incorporated Disadvantages Works well up to few thousand variables EE82V: SoC Design, Lecture G. De Micheli 29 Hu s Algorithm Simple case of the scheduling problem Operations of unit delay Operations (and resources) of the same type Hu s algorithm Greedy, polynomial and optimal (eact) Computes lower bound on number of resources for given latency OR Computes lower bound on latency subject to resource constraints Basic idea Label operations based on their distances from the sink Try to schedule nodes with higher labels first (i.e., most critical operations have priority) EE82V: SoC Design, Lecture R. Gupta G. De Micheli 2 A. Gerstlauer

16 EE82V: SystemonChip (SoC) Design Lecture Hu s Algorithm with ā Resources Label operations with distance to sink Set step l = Repeat until all ops are scheduled U = unscheduled vertices in V Predecessors have been scheduled (or no predecessors) Select S U resources with S ā Maimal labels Schedule the S operations at step l Increment step l = l EE82V: SoC Design, Lecture G. De Micheli Hu s Algorithm Eample Assumptions One resource type only All operations have unit delay Labels Distance to sink EE82V: SoC Design, Lecture G. De Micheli 2 n 2 A. Gerstlauer

17 EE82V: SystemonChip (SoC) Design Lecture Hu s Algorithm Eample _ a = Step : Op,2, Step 2: Op,7,8 Step : Op,9, Step : Op, n EE82V: SoC Design, Lecture G. De Micheli List Scheduling Heuristic method for: Min latency subject to resource bound (MLRCS) Min resource subject to latency bound (MRLCS) Greedy strategy (like Hu s) Does not guarantee optimality (unlike Hu s) General graphs (unlike Hu s) Resource constraints on different resource types Operations of arbitrary delay Priority list heuristics Priority decided by criticality (similar to Hu s) Longest path to sink, longest path to timing constraint O(n) time compleity EE82V: SoC Design, Lecture K. Bazargan G. De Micheli 2 A. Gerstlauer 7

18 EE82V: SystemonChip (SoC) Design Lecture List Scheduling for Minimum Latency LIST_L( G(V, E), a) { l = ; repeat { for each resource type k =, 2,, n res { Determine ready operations U l,k ; Determine unfinished operations T l,k ; Select S k U l,k vertices, s.t. S k T l,k a k ; Schedule the S k operations at step l; } l = l ; } until (v n is scheduled) ; return (t); } EE82V: SoC Design, Lecture G. De Micheli List Scheduling Eample < TIME 2 n TIME 2 TIME 7 8 < TIME Resource bounds TIME multipliers with delay 2 TIME ALU with delay TIME 7 9 EE82V: SoC Design, Lecture G. De Micheli n 2 A. Gerstlauer 8

19 EE82V: SystemonChip (SoC) Design Lecture Lecture : Outline The scheduling problem Unconstrained scheduling Resource constrained (RC) scheduling Time constrained (TC) scheduling Eact methods ILP formulations Hu s algorithm Heuristics List scheduling Forcedirected scheduling Advanced scheduling problems EE82V: SoC Design, Lecture G. De Micheli 7 List Scheduling for Minimum Resources LIST_R( G(V, E), λ) { a = ; Compute the latest possible start times t L by ALAP ( G(V, E), λ); if (t < ) L return (Ø); l = ; repeat { } for each resource type k =, 2,, n res { L Determine ready operations U l,k ; Compute the slacks { s i = t i l for all v i є U lk }; Schedule candidate operations with zero slack and update a; Schedule candidate operations not needing addt l resources; } l = l ; } until (v n is scheduled) ; return (t, a); EE82V: SoC Design, Lecture G. De Micheli 8 2 A. Gerstlauer 9

20 EE82V: SystemonChip (SoC) Design Lecture List Scheduling Eample < Step Two multiplications on CP Set a = 2 Schedule Mult,2 Schedule ALU Step 2 Schedule Mult, Schedule ALU Step Schedule Mult 7,8 Schedule ALU Step Set a 2 =2 Schedule ALU, 9 n TIME 2 Assumptions Unitdelay resources Maimum latency = Start with a = multiplier a 2 = ALUs TIME 2 TIME TIME n EE82V: SoC Design, Lecture G. De Micheli < ForceDirected Scheduling (FDS) Heuristic, similar to list scheduling Can handle MLRCS and MRLCS For MLRCS, schedules stepbystep BUT, selection of the operations tries to find the globally best set of operations Idea [Paulin] Find the mobility μ i = t i L ti S of operations (ALAPASAP) Look at the operation type probability distributions Try to flatten the operation type distributions Definition: operation probability density p i ( l )=Pr{v i eecutes in step l } ( ) S L Assume uniform distribution: p l for l[ t, t ] EE82V: SoC Design, Lecture R. Gupta G. De Micheli i i i i 2 A. Gerstlauer 2

21 EE82V: SystemonChip (SoC) Design Lecture ForceDirected Scheduling: Definitions Operationtype distribution (sum of operation probabilities for each type) qk ( l) pi ( l) it : ( vi ) k Operation probabilities over control steps pi { pi (), pi (),, pi ( n)} Distribution graph of type k over all steps { qk (), qk (),, qk ( n)} q k ( l ) can be thought of as epected operator cost for implementing operations of type k at step l EE82V: SoC Design, Lecture K. Bazargan G. De Micheli ForceDirected Scheduling Eample q q q q add add add add (). (2) () 2 () < () (2) ().8 2 () EE82V: SoC Design, Lecture K. Bazargan G. De Micheli 2 q q q q mult mult mult mult A. Gerstlauer 2

22 EE82V: SystemonChip (SoC) Design Lecture ForceDirected Scheduling Algorithm Very similar to LIST_L(G(V,E), a) Compute mobility of operations using ASAP and ALAP Computer operation probabilities and type distributions Select and schedule operation Update operation probabilities and type distributions Go to net step/operation Difference with list scheduling in selecting operations Select operations with least force O(n 2 ) time compleity due to pairwise force computations EE82V: SoC Design, Lecture R. Gupta G. De Micheli Force Used as priority function Force is related to concurrency Sort operations for least force Mechanical analogy (spring) Force = constant displacement Constant = operationtype distribution Displacement = change in probability EE82V: SoC Design, Lecture G. De Micheli 2 A. Gerstlauer 22

23 EE82V: SystemonChip (SoC) Design Lecture Two Types of Forces Selfforce Sum of forces to feasible schedule steps Selfforce for operation v i in step l Sum over type distribution delta probability Σ m in interval q k (m) (δ lm p i (m)) Higher selfforce indicates higher mobility Predecessor/successorforce Related to the predecessors/successors Fiing an operation timeframe restricts timeframe of predecessors/successors E: Delaying an operation implies delaying its successors Computed by changes in selfforces of neighbors EE82V: SoC Design, Lecture G. De Micheli Eample: Schedule Operation v < n Distribution graphs for multiplier and ALU Operation v can be scheduled in step or step 2 EE82V: SoC Design, Lecture G. De Micheli 2 A. Gerstlauer 2

24 EE82V: SystemonChip (SoC) Design Lecture Eample: Operation v Op v can be scheduled in the first two steps p ( ) =.; p (2) =.; p ( ) = ; p ( ) = Distribution q ( ) = 2.8; q ( 2 ) = 2. Assign v to step Variation in probability. =. for step Variation in probability. =. for step 2 Selfforce =.2 No successor force Total force =.2 EE82V: SoC Design, Lecture G. De Micheli 7 Eample: Operation v Assign v to step 2 variation in probability. =. for step variation in probability. =. for step 2 Selfforce =.2 Successorforce Operation v 7 assigned to step Succ. force is 2. (. ).8 (. ) =.7 Total force = EE82V: SoC Design, Lecture G. De Micheli 8 2 A. Gerstlauer 2

25 EE82V: SystemonChip (SoC) Design Lecture Eample: Operation v Total force in step =.2 Total force in step 2 = Conclusion: Least force is for step 2 Assigning v to step 2 reduces concurrency EE82V: SoC Design, Lecture G. De Micheli 9 FDS for Minimum Resources FDS ( G ( V, E ), λ ) { repeat { Compute/update the timeframes; Compute the operation and type probabilities; Compute the selfforces, p/sforces and total forces; Schedule the op. with least force; } until (all operations are scheduled) return (t); } EE82V: SoC Design, Lecture G. De Micheli 2 A. Gerstlauer 2

26 EE82V: SystemonChip (SoC) Design Lecture Scheduling Generalizations Detailed timing constraints Protocol and interface synthesis Bounds on start time differences Forward & backward edges for min/ma constraints Operation generalizations Unbounded delay operations (e.g. synchronization) Relative scheduling w.r. to anchors and combine Conditional operations Resource generalizations Multicycling and chaining Pipelined resources Model generalizations Hierarchy Pipelining Loops EE82V: SoC Design, Lecture R. Gupta G. De Micheli MultiCycling and Chaining Consider delays of resources not in terms of cycles Use scheduling to chain multiple operations in the same control step Use scheduling to multicycle an operation across more than one control step Useful techniques to eplore effect of cycletime on area/latency tradeoff Algorithms ILP ALAP/ASAP List scheduling EE82V: SoC Design, Lecture G. De Micheli 2 2 A. Gerstlauer 2

27 EE82V: SystemonChip (SoC) Design Lecture Chaining Eample N N (a) (b) Cycletime: EE82V: SoC Design, Lecture G. De Micheli Pipelining Two levels of data pipelining Structural pipelining Pipelined resources Nonpipelined model Functional pipelining Nonpipelined resources Pipelined model Control pipelining Pipelined control logic EE82V: SoC Design, Lecture R. Gupta G. De Micheli 2 A. Gerstlauer 27

28 EE82V: SystemonChip (SoC) Design Lecture Structural Pipelining Nonpipelined model using pipelined resources Resources characterized by Eecution delay Data introduction interval: DII Implications Operations sharing a pipelined resource are serialized (always) Operations do not have data dependency Solution using list scheduling Rela criteria for selection of vertices EE82V: SoC Design, Lecture R. Gupta G. De Micheli Structural Pipelining Eample < < < < multipliers w/ 2 cycle delay and DII = EE82V: SoC Design, Lecture R. Gupta G. De Micheli 2 A. Gerstlauer 28

29 EE82V: SystemonChip (SoC) Design Lecture Functional (Loop) Pipelining Pipelined model, nonpipelined resources Assume nonhierarchical graphs Model characterized by Latency Initiation interval, II Restart source before completing sink Implicit loop Limited by loopcarried dependencies Solutions using ILP or heuristics ILP resource constraints modified to include increased concurrency List or forcedirected methods EE82V: SoC Design, Lecture R. Gupta G. De Micheli 7 Pipelining and Concurrency II determines resource usage Smaller II leads to larger overlaps, higher resource requirements min{a k } = n k, for II= (all n k operations are concurrent) In general, a k nk II Concurrent operations Operations v i and v j are eecuting concurrently at control step l, if rem{ t i II } = rem{ t j II } = l Affects the design of the controller circuitry EE82V: SoC Design, Lecture R. Gupta G. De Micheli 8 2 A. Gerstlauer 29

30 EE82V: SystemonChip (SoC) Design Lecture Loop Scheduling Potential parallelism across loop invocations Single loop eecutions Sequential eecution Loop unrolling (known iteration count) Merge multiple iterations into one to provide scheduling opportunities Loop pipelining (iteration count might be unknown) Start net iteration while current one is still running Depends on dependencies across iterations Functional pipelining Merging of multiple loops Run different loops in parallel (no dependencies) EE82V: SoC Design, Lecture R. Gupta G. De Micheli 9 Loop Scheduling Eample Sequential Unrolled,2,,, 7,8,9 Pipelined Iteration count = N Loop latency = N λ Pipeline loop iterations with II < λ Latency of the pipelined loop N II overhead II Overhead = EE82V: SoC Design, Lecture R. Gupta G. De Micheli 2 A. Gerstlauer

31 EE82V: SystemonChip (SoC) Design Lecture Lecture : Summary Scheduling determines area/latency tradeoff Intractable problem in general Heuristic algorithms ILP formulation (smallcase problems) Several heuristic formulations List scheduling is the fastest and most used Forcedirected scheduling tends to yield good results Several etensions Chaining and multicycling Pipelining EE82V: SoC Design, Lecture G. De Micheli 2 A. Gerstlauer

EE382V-ICS: System-on-a-Chip (SoC) Design

EE382V-ICS: System-on-a-Chip (SoC) Design EE8VICS: SystemonChip (SoC) EE8VICS: SystemonaChip (SoC) Scheduling Source: G. De Micheli, Integrated Systems Center, EPFL Synthesis and Optimization of Digital Circuits, McGraw Hill, 00. Additional sources: