ITG Japan. September 15 th, Makoto Yamamoto, Muratec ITG Japan. Interoperability Test Group Japan 1

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1 ITG Japan September 15 th, 2010 Makoto Yamamoto, Muratec ITG Japan Interoperability Test Group Japan 1

2 Interoperability Test Group for 450mm Industry Standard development Japan Name: Interoperability Test Group for 450mm Industry Standard development Japan (Interoperability Test Group Japan) Mission: To provide test reports to the related industry standard committees and/or task forces for the standardization. Organization and Members ITG Japan is not belonged to any industry organization Members are voluntary companies and/or individuals who have interest and support in the mission. Established June, 2008 Interoperability Test Group Japan 2

3 Members (12 companies) ITG-J Co-chairs ITG-J active members Interoperability Test Group Japan 3

4 450mm PIC Standards Carriers: E158(450FOUP), E1xx(450 MAC), Mxx(450 FOSB) M74, M76, Mxx(Wafer) E144(RF Air Interface) Load Port E154(FOUP Load Port), E1xx(FOSB Load Port) E84(Carrier Hand off Parallel I/O) E83(PGV Docking Flange) E156(Stocker Interface) Interoperability Test Group Japan 4

5 ITG-J major test items & Standards Carriers Load Port Standards Test Items Completion FOUP MAC FOSB budget* May 2009 KC Grove life cycle* Dec Placement sensor* Dec Center gravity Mar AMHS Vibration Apr Manual handling Jan New placement Jul budget* On going Drop tests Mar Door closure force Apr FOUP & MAC Wafer vibration at EFEM Mar Alternative latch System Aug FOSB Wafer mapping test Mar Interoperability Test Group Japan 5

6 Differences among carriers FOUP (Front Opening Unified Pod) FOSB (Front Opening Shipping Box) MAC (Multi Application Carrier) Where to use IC makers Fab (Carry process wafers) Wafer Shipment from Silicon suppliers to IC makes Silicon suppliers fab Processed wafer shipment from IC makers. Different points Wafers supported by back side contact. Process induced warp is considered. Wafers supported by edge grip. Drop height assumption is 510mm during transportation. Wafers supported by edge grip. Drop height assumption is 210mm during transportation. Process induced warp is considered. Interoperability Test Group Japan 6

7 Report samples FOUP Pictures of Test System Test Method ITG-J inputs for budget 1 Close up of EE down position FOUP Wafer Table Shipping Box Shipping Box test Shipping Box Wafer Table Interoperability Test Group Japan 7

8 Test Bed Outline 1000mm 1200mm Test carrier Controller Measuring instrument etc. 2000mm Robot controller LP1 LP2 LP3 ST1 Support pin positioning wafer by drop Interoperability Test Group Japan 8

9 Wafer handling robot link dual arm cylindrical coordinate robot with slider Pictures from Test test Robot End Effector(Short type) Robot Linearity test stage (Dynamic wafer handling) Interoperability Test Group Japan 9

10 Picture of test Interoperability Test Group Japan 10

11 Pictures from Test Interoperability Test Group Japan 11

12 FOUP Wafer Table Line Description "A" "A" "B" "B" "C" "C" "D" "D" "E" "E" "F" "F" 2 Thickness of Wafer Deflection under Gravity for Wafer 4 Process Induced Robot Warp 5 Initial Warp Tolerance of wafer planes 7 Carrier Placement Error 8 EE Structure 9 EE Wafer Contact Pads 10 EE Curve w/o wafer 11 EE Curve w/ wafer 12 Inclination of Robot Motion 13 Vibration of EE (P- P) 14 Teaching and alignment 15 EE Roll Error 16 Desired Safety Margin 17 Thickness of Wafer Support Incl. in #13 Incl. in # Incl. in #13 Incl. in # TOTAL TBD Wafer related 4.75mm Carrier related 1.2mm Varies (W Robot suppliers estimates) Min. 3.5mm Max. 4mm ITG-J report (test data of vibration) 2.5 mm OK 1.94mm NG Grand Total Min mm Max mm 12 Interoperability Test Group Japan 12

13 Shipping Box test Tested with single crystal wafers loaning from ISMI program. Three members tested with three different EE. 1.5 mm 1 mm 3 mm 3 mm 2 mm 1 mm 1.5mm 3.5mm Interoperability Test Group Japan 13

14 FOSB Wafer Table Item Description Supplier A Supplier B Supplier C Supplier D 2 Thickness of Wafer Deflection under Gravity Process Induced Warp Initial Warp Tolerance of wafer planes Carrier Placement Error EE Structure EE Wafer Contact Pads EE Curve w/o wafer EE Curve w/ wafer Inclination of Robot Motion Vibration of EE (P-P) Incl. Incl. Incl. Incl. Incl. Incl. Incl. Incl. in #12 in #12 in #12 in #12 in #12 in #12 in #12 in #12 14 Teaching and alignment Incl. Incl. Incl. Incl. Incl. Incl. Incl. Incl. in #12 in #12 in #12 in #12 in #12 in #12 in #12 in #12 15 EE Roll Error Incl. Incl. Incl. Incl. Incl. Incl. Incl. Incl. in #12 in #12 in #12 in #12 in #12 in #12 in #12 in #12 16 Desired Safety Margin Thickness of Wafer Support TOTAL Three inputs from members Description 22 Wafer (2, 3, 4, & 5) Carrier (6 & 7) 8.0mm EE (8, 9, 10 & 11) 8.25mm Robot (12, 13, 14,& 15) Desired Margin (16) 8.7mm Thickness of Wafer Support (17) Wafer related 2.55mm? Carrier related 1.2mm? for Wafer Robot Interoperability Test Group Japan 14

15 ITG-J Next Step ITG-J believes most of planned tests have been finished with supports of ISMI and member companies. ITG-J expects SEMI Task Forces utilize the test results and develop industry wide accepted standard. ITG-J will slow down the activities and will come back whenever the industry needs the activities. Interoperability Test Group Japan 15

16 Thank You Interoperability Test Group Japan 16

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