Switched apacitor Filters SF) Passive Filters omponents are R, L, Big, Heavy, discrete Inductors are limited in quality Designed in sdomain Active R filters omponents are Opamps, OTAs, R s and s an be integrated on the same chip Inaccurate R in Is Designed in sdomain Switched apacitor Filters Idea well known for over 80 years Accurate R, where R is realized using switches and capacitors lock noise and noise alias Small chip area Designed in zdomain Two most useful filter realizations ascade Ladder Realization 8 SF Design Three basic methods. Resistor substitution Replace the resistors in a continuous time active R filter, with switched capacitor circuits. Uses switched capacitor integrators to simulate passive RL prototype circuits, RL ladder networks, for a desired filter realization 3. Uses a direct building block approach in the Z domain of which there are two approaches: a. onvert the transfer function into a signal flow diagram consisting of amplifiers, delays and summers b. Break the transfer function into products of first and second order terms. 8
S Resistor Simulation V V f V V T c = f c = T c = f c i R R V V f φ,φ is a two phase nonoverlapping clock 8 3 S Resistor Simulation ont d) At position the charge on at steady state is q = V At position the charge on at steady state is q = V Assuming V > V, the charge Δq transferred is ) Δq = q q = V V The current flowing will be on average it) = δqt) δt = lim ΔT c 0 ) Δq V V ΔT c onsider now a resistance of value R connected to the same two sources V &V. Then ) i R t) = V V R Equating ) and ) yields R = T c = f c T c ) ) Ex. Using =pf, f c =00kHz R =0MΩ 8 4
onditions for SR Approximation At least one of the sources must be a voltage source R V V V V " R = T c $ ' & If >>, R = T c Note if neither V nor V are voltage sources then R To other nodes Show that " R = ) $ ' T c & 8 5 onditions for SR Approximation ont d) S Resistors cannot close an opamp feedback path R Not allowed Allowed 8 6
onditions for SR Approximation ont d) No floating nodes allowed Floating Node V V Switches G φ G f S D S D NMOS PMOS omplementary Switch 8 7 Summary of Approximated Resistance of Four Switched apacitor Resistor ircuits Parallel f V V R = T Series f V V R = T SeriesParallel f V V T R = φ φ Bilinear V φ φ V R = T 4 8 8
MOS Switch Realization SiO S G Polysilicon D n n NMOS Switch ptype silicon Substrate SiO S G Polysilicon D p p PMOS Switch nwell ptype silicon Substrate 8 9 Switches ontinued Switch turns on when V G > V TH and turns off when V G < V TH Typically R on kω 0kΩ, and R off 00MΩ GΩ for single switches. For complementary MOS switches R on is lower and in the order of R on 0Ω kω f V V f V V T c = f c f 8 0
apacitor Realization Basically two types of capacitors. Metal Oxide rystalline Silicon apacitor Grounded capacitor) Best suited for metal to gate MOS and MOS processes which do not use self alignment procedures.. PolysiliconOxidePolysilicon apacitor Floating apacitor) Found in many processes today Requires little self alignment Selling feature of Ss is the capacitor ratio accuracy which can reach 0. in some cases. Note transistors can also be used as capacitors! SiO Aluminum SiO Poly Poly n,p n,p n,p Substrate n,p Substrate MOS ap. PolyPoly ap. 8 0 µm Δ apacitance Mismatch Area Inaccuracy & Oxide Thickness Variation Keep apacitance Ratio onstant 40 µm = 40 0.5) 40 0.5 0 0.5 ) ) 0 0.5) = 4.03.6 error 0 µm = ) 0 0.5 ) ) 0 0.5) = 4 4 0 0.5 0 0.5 0 µm 8
apacitance Layout Non optimal approach 4 4 Optimal layout is the entroid Approach Ground shielding should also be added 8 3 Parasitic apacitances Parasitic capacitances exist in switches and in capacitors Switch S gs G gd D Overlap component f gs gd n sb gb n db Voltage dependent sb gb db Substrate gs = gd 0.005 pf sb = db 0.0 pf 8 4
Parasitic apacitances ontinued Polypoly apacitor SiO Poly n,p Poly T T B B n,p Substrate T 0. of the desired MOS capacitance B 5 0 of the desired MOS capacitance 8 5 A Switched apacitor Integrator R s domain "Miller" Integrator = R s f c R S Integrator obtained by replacing "R" with a switched capacitor = & c $ ' s f Implementation f 8 6
f Effects of Parasitics T B ol ol ol ol p p p p p 's are sb and db ol 's are gs and gd T B p is always charging from and has no effect B is shorted p and T have zero voltage across them. This has no effect B is always charging to ol and ol only affect the output by feeding the clock signal through the integrator. This is known as clockfeedthrough. It can be minimized but never eliminated. Thus we are left with p = p p T 8 7 Effects of Parasitics ont d) f p p & = f c $ ' s The above integrator is said to be parasitic sensitive Not desireable if precision is required Parasitic insensitive integrators exist. 8 8
A Noninverting Parasitic Insensitive) Integrator Negative Resistor f f Examining parasitics p p p always has a zero potential p charges to during one cycle " s) = c $ ' & s and discharges to zero in the next. It has no effect. 8 9 A Differential Parasitic Sensitive) Integrator p p By superposition s) = f c s If p << s) = f c s " $ " $ ) " ' p, $ '. &* & ' & [ ] 8 0
Sample ircuits First order S section R 4 S direct replacement 4 R 3 3 = & $ ' $ s R 3 s R 4 & ' = & $ ' $ s f c 3 s f c 4 & ' 8 Sample ircuits ont d) Second order S section LP Filter R R R 3 4 R opamp realization R s) = R 3 4 s s R 3 4 R R 3 4 3 4 s) = 3 4 f c s f c 3 4 s 3 4 f c = ω o s ω o Q s ω o 8
Ex. Design a LP filter with f o =.59kHz and Q = 5. The D gain is to be unity. Solution Sample ircuits ont d) ω s) = o 0 8 s ω = o Q s ω o s 000s 0 8 Using the previous circuit the design equations are 3 4 f c =0 8 and 3 4 f c = 000. hoosing f c =6kHz 0 times f o ) = 3.5 and 3 4 = 0.5. Let =pf and 4 =0 pf yields = 3.5 pf and 3 =.5 pf Note the maximum capacitance ratio is 0 8 3 Sample ircuits ont d) Ex. BP Filter R R opamp realization R a R R s) = R s s α R s R R a S opamp realization = f c R s) = f c s s α f c s f c = f c R Behaves as a negative resistor 8 4
Ex. Soln. Realize a S BPF with f o =.59kHz and Q = 5. The center frequency gain is to be.5. Using the previous S BPF we obtain the following design equations: ω o = f c Q = α FG = α Letting f c =6kHz 0 f o ) and solving the above equations, yields α = 0.4 =.5 = 0.35 We may scale by 0 to yield =.5 pf, = 0.35 pf, =pf and α = 0.4 pf. Note the maximum capacitance ratio is 4.0, which is practical. 8 5 A Useful ircuit The Sample & Hold The sample and hold provides a means for delaying the input or the output of a circuit by half a clock delay in a two phase clock system. The simplest sample and hold is an opamp configured as a buffer with a switch clocked on either of the two clock phases and a holding capacitor. Other more elaborate schemes exist. or f V S / H V V or f V In the z domain V z) = z V z) regardless of the clock phasing. 8 6
Numerical Integration and the stoz transformation Ú Vo v o t) = t t o t v in t) = v in t) v in t) t o = v o t o ) Area under the v in t) curve from t o t In the frequency domain this can be expressed as, s) = s s) or s) s) = s Numerically we can calculate v o t) by v o nt ) = v o nt T ) Area There are four well known methods of area calculation Note others exist! 8 7 Four methods of discrete integration v in t) v in t) ) Ê v in n ˆ Á T Ë 3) v in nt ) Ê n )T n ˆ Á T Ë nt t Ê n )T n ˆ Á T Ë v in nt ) nt t ) v in n )T Ê n )T n ˆ Á T Ë nt t 4) v in n )T Ê n )T n ˆ Á T Ë nt t. Middle Point Integrator or Lossless Discrete Integration LDI). Forward Euler Discrete Integration FEDI 3. Backward Euler Discrete Integration BEDI) 4. Bilinear Discrete Integration BDI) or Trapeziodal Integration Rule 8 8
Middle Point Integrator v in t) Ê v in n ˆ Á T Ë Ê n )T n ˆ Á T Ë Area = Tv in nt T & $ '. Thus v nt ) = v nt T )Tv nt T & o o in $ ' Taking z transforms z) = z z)tz z) nt t z) = T z z s) = s The corresponding s to z transform is then obtained as s = z ) = T T z z & $ ' z 8 9 Forward Euler Integrator v in t) v in n )T Ê n )T n ˆ Á T Ë nt t Area = Tv in nt T ). Thus v o nt ) = v o nt T )Tv in nt T ) Taking z transforms z) = z z)tz z) z) = T z z s) = s The corresponding s to z transform is then obtained as s = z ) T z = z ) T 8 30
Backward Euler Integrator v in nt ) v in t) Ê n )T n ˆ Á T Ë nt t Area = Tv in nt ). Thus v o nt ) = v o nt T )Tv in nt ) Taking z transforms z) = T z z) = z z)t z) s) = s The corresponding s to z transform is then obtained as s = T z ) 8 3 Bilinear Discrete Integrator v in t) v in nt ) v in n )T Ê n )T n ˆ Á T Ë nt t Area of the trapezoid = T [ v in nt T ) v in nt )]. [ )] Thus v o nt ) = v o nt T ) T v in nt T ) v in nt Taking z transforms z) = z z) T z [ ) z z) ] z) = T z z s) = s The corresponding s to z transform is then obtained as s = & z ) T ' z * 8 3
Bilinear Discrete Integrator ont d) s = z & st z = T $ z ' st For s = jω and z = re jωt re jωt = jωt jωt r =, and ω = T tan $ If s = σ ± jω r < ΩT & ' p T w digital frequency If s = σ ± jω r > 0 W analog frequency p T We have distortion in the digital frequency domain Prewarping the digital frequency can compensate for this 8 33 Another Transform and Summary There exists the impulse invariance transform which is popular due to its simplicity. z = e st or s = T lnz) Summary z =, Backward Euler st z = st, Forward Euler z 3 = st st z 4 = e st,, Bilinear Impulse Invariance For high sampling rates st < z = st st ) st ) 3... st z = st, z 3 = st z 4 = st st ) st ) st )3 4 st )3 6... st... st 8 34
Errors associated with the Discrete Integrators Errors exist with each integrator Ideal integrator should have zero magnitude and phase error H I ω) = H s) s= jω = jω Let us assume each integrator has a magnitude error ε and phase error θ asscociated with it. That is, For the LDI H NI ω) = jθ ε)e jω z H z) = T z = T z z H e jωt T ) = jωt e e jωt Equating 3) and 4) jω ε)e jθ = ε = ωt osec & ωt ' θ = 0 ) * T jωt e e jωt & ωt = jω osec & ωt )) ' ' ** 3) 4) 8 35 Errors associated with the Discrete Integrators ont d) Magnitude Error ε) Phase Error ωt osec " ωt LDI $ ' 0 & FEDI BEDI ωt osec " $ ωt ωt osec " $ ωt θ) ' ωt & ' ωt & ωt ot " ωt BDI $ ' 0 & Because θ = 0 for LDI) Dr. Bruton called this integrator the Lossless Discrete Integrator. Note the LDI has no real part. For high sampling rates all errors are low. 8 36
Summary Type of Integrator R φ φ Inverting Straysensitive Forward) Magnitude He jwt ) ω o ω For at φ ω o ωt / & ω $ sin ωt /)' For at φ ω o ωt / & ω $ sin ωt /)' Phase ArgHe jwt )) π π π ωt Mapping Equivalent) In the s plane LDI Forward Hs) = Transfer Function sr = o s Hz) = z / z Hz) = z z φ φ φ φ NonInverting V φ φ in φ φ Inverting Backward) For at φ ω o ωt / & ω $ sin ωt /)' For at φ ω o ωt / & ω $ sin ωt /)' For at φ ω o ωt / & ω $ sin ωt /)' For at φ ω o ωt / & ω $ sin ωt /)' π π ωt π ωt π LDI Forward Backward LDI Hz) = z / z Hz) = z z Hz) = z Hz) = z / z 8 37 splane Impulse Invariance Mapping jw 3p T zplane B p T Im D E p T A 0 p T p T S DE 0 AB Re 3p T A strip of length π T is wrapped once around the unit circle Method is only applicable to filters with a bandlimited analog frequency response that satisfies H jω) 0 for Ω > Ω B 8 38
splane Backward Euler Mapping j zplane j B Im D A D B E A Re j E Poles in the LHP map to a circle of center / and radius / Integrator has good performance for low frequency signals. That is signals with discrete frequency close to. For high frequencies it performs poorly. 8 39 splane j Forward Euler Mapping zplane j B Im B D A D A Re j E E Like the BEDI this integrator works well with low frequency signals. It is possible for points to be mapped outside the unit circle yielding and unstable system. 8 40
Bilinear Mapping splane j j F B B zplane Im A F E A Re j D D E Points all along the jω axis are mapped to the unit circle. 8 4 Midpoint Integration v in t) LDI Transformation s a = z Tz = z T z & $ Tz ' v in n T n )T nt n )T t z, = s a T ± z z = s a T Forward Euler s a T ) s a T ) ) at s a T ) Backward Euler ) = z = z If z > then z < and vice versa A stable pole s a will transform into one stable and one unstable pole in the z plane This implies H a s a ) will not transform into a stable H z) However, the LDI is still useful in understanding the operation of SFs based on the LDI transformation 8 4
Midpoint Integration ont d Image of the jω a axis for jω a > T Image of the jω a axis for jω a T z x z x z x z x 8 43 S Analysis using harge Equations The priniciple of charge conservation can be used to analyze S circuits. Useful guidelines. harge at the present time= harge at the instant before harge Injected.. If the output is to be evaluated at time ntt/ draw the circuit at time ntt/) and at ntt). Similarly if the output is to be evaluated at time nt) draw the circuit at time nt) and at ntt/). 3. If the polarity of the capacitor injecting charge into another has the same polarity as the one receiving the charge use a ve sign in the charge equation otherwise use a ve sign. 8 44
The Middle Point Integrator Parasitic sensitive) We wish to evaluate z) at an instant we designate as nt nt v v nt T Assuming a current flow nt T v o nt T & = $ ' v o nt T ) 0 Zero charge Injected) 5) 8 45 The Middle Point Integrator ont d) nt v o nt ) = v o nt T & $ ' ) v nt ) v nt T &, $ * '. but v nt ) = 0 and v nt T & $ ' = v nt T & in $ ' v o nt ) = v o nt T & $ ' v in nt T & $ ' Substuting 5) in 6) yields v o nt ) = v o nt T ) v in nt T $ and taking z transforms & ' 6) z) = z)z z)z z z) = z 8 46
A Forward Euler Discrete Integrator PS) We wish to evaluate z) at an instant we designate as nt nt v v nt T Assuming a current flow nt v o nt ) = v o nt T $ & 0 Zero charge Injected) 7) ' 8 47 A Forward Euler Discrete Integrator PS)ont d v o nt T & ) = $ ' v o nt T but v nt T & = 0 and v $ ' nt T v o nt T & = $ ' v o nt T Substituting 7) in 8) yields v o nt ) v nt T * $ ) = v in nt T ) ) v in nt T ) ) = v o nt T ) v in nt T ) and taking z transforms z) = z)z z)z z z) = z &, v ' nt T ). 8) Depending on which clock phase the output is sampled the outcome is a parasitic sensitive LDI or FEDI integrator. The two outcomes are separated only by half a clock delay. 8 48
A Stray Insensitive) Forward Euler Discrete Integrator v n Notes n n v o n v ) = v o n $ & 0 ' v o n & ) = $ ' v o n but v n & = 0 and v $ ' n v o n ) v n * $ ) = v in n ) ) = v o n ) v in n ) z z) = z &, v ' n ). n Output is to be evaluated at time n. T can be omitted since it conveys no useful information in the charge equations If the output was to be evaluated at time n/ instead, the numerator of the answer would be z / instead of z. That is the circuit would be non inverting LDI Stray insensitive). 8 49 A Stray Insensitive) Backward Euler Discrete Integrator n Notes n n v o n v v ) = v o n $ with v n) = v in n v o n & = $ ' v o n v o n & ) ' v n * ) and v n $ ) 0 ) = v o n ) v in n) z) = z ) v n $ & = 0 ' n &, '. Output is to be evaluated at time n. If the output was to be evaluated at time n/ instead, the numerator of the answer would be z / instead of. That is the circuit would be an inverting LDI Stray insensitive). 8 50
A Stray Insensitive) Bilinear Discrete Integrator V S / H By superposition the output can be computed by recognizing the presence of a BEDI and a LDI. Loosely speaking therefore, z) = { BEDI LDI} V z) $ z) = z z ' & ) & & z ) V z) ) $ = V z) z V ' & z)z ) & & z ) ) but V z) = z z) V z)z = z z) z) z) = $ z ' & z ) 8 5 A First Order Building Block 4 5 Notes V S / H 3 All switches discharge into simultaneously. This eases how fast the the opamp has to work. $ z) = γ z z γ γ ' $ 3 & z ) z) γ 4 z z γ ' 5 & z ) z) [ ] = z)[ γ z γ γ z γ 3 ] z) z γ 5 γ 4 z z) = γ γ 3) γ γ )z γ 5 ) γ 4 )z = α o α z β o β z 8 5
Another First Order Building Block g 4 Notes V S / H g g 5 Opamp has to work twice as hard. Output is available only on one phase g g 3 z) = ) γ $ γ ' & γ 3 ) z γ 4 $ γ ' 5 & ) z γ 4 8 53 Yet another First Order Building Block g 4 V S / H g g g 5 Notes Opamp has to work twice as hard. Output is available only on one phase g 3 z) = ) γ γ 5 γ $ $ ' ' & & ) γ 3 ) z γ 4 $ γ ' 5 & ) z γ 4 8 54
Signal Flow Graph Analysis V z) = γ V z) = γ z z V 3 z) = γ 3 z V V V 3 g g g 3 n By superposition therefore [ ] z) = z γ z )V z)γ z V z) γ 3 V 3 z) 8 55 Signal Flow Graph Analysis ont d) Equivalent signal flow graph V z) g z ) V z) g z S z) z V 3 z) g 3 8 56
Signal Flow Graph st Order Example Active R Version S Version R 3 3 s) R s) Signal Flow Graph z) z z) z) = γ γ γ z γ 3 z z 3 8 57 General StrayInsensitive S Biquad Dr. ElMasry) g 0 g g 8 g 9 g 5 g 7 g 6 S / H V x g g g V g 3 V g 3 g 4 g 4 g 6 g 5 8 58
General StrayInsensitive S Biquad ont d) A general S Biquad can be used to realize the biquadratic transfer function T z) = α o α z α z β o β z β z using two of the Sst order building blocks in a feedforward / feedback manner. For the circuit shown in the figure the equations are: & V z) = γ 3z z γ z γ ) & z) γ 7z ' * z γ ) & 8 ' z V z) γ z * z γ 0 z γ ) 9 V z) ' * and & V z) = γ 4z z γ z γ ) & 3 V z) γ 6z ' * z γ ) & 5 ' z V z) γ 6z * z γ 4 z γ ) 5 z) ' * 8 59 General StrayInsensitive S Biquad ont d) T z) = V z) = a 0 a z a z c 0 c z c z and T z) = V z) = b 0 b z b z c 0 c z c z where a 0 = γ 4 γ 5 ) γ 9 γ 0 ) γ γ ) γ 5 ) a = γ γ ) γ 6 ) γ γ 3 ) γ 5 ) γ 4 γ 5 ) γ 9 γ ) γ 5 γ 6 ) γ 9 γ 0 ) a = γ 5 γ 6 ) γ 9 γ ) γ γ 3 ) γ 6 ) b 0 = γ γ ) γ γ 3 ) γ 4 γ 5 ) γ 8 ) b = γ 4 γ 5 ) γ 7 ) γ 5 γ 6 ) γ 8 ) γ γ ) γ 3 γ 4 ) γ γ 3 ) γ γ 3 ) b = γ γ 3 ) γ 3 γ 4 ) γ 5 γ 6 ) γ 7 ) c 0 = γ 8 ) γ 5 ) γ 9 γ 0 ) γ γ 3 ) c = γ 9 γ ) γ γ 3 ) γ 9 γ 0 ) γ 3 γ 4 ) γ 7 ) γ 5 ) γ 8 ) γ 6 ) c = γ 7 ) γ 6 ) γ 9 γ ) γ 3 γ 4 ) The equivalent analog pole frequency ω o and pole Q are given by ω o = f c c 0 c c c 0 c c and Q = where f c is the clock frequency. c 0 c c ) c 0 c c ) c 0 c ) Note ω o and Q are obtained by using the bilinear z transform 8 60
Simplified version of the General Biquad g 0 g 9 g 5 g S / H V x V g 4 g 3 V g 4 g 6 Let us set γ = γ 5 = γ 7 = γ 8 = γ = γ = γ 3 = γ 6 = 0. Then [ ] γ γ 3 γ 5 ) γ 6 γ 0 γ 9 γ 4 γ 6 ) T z) = V z) = γ 4 γ 9 γ 0 ) γ γ 5 ) T z) = V z) = γ 4 [ γ γ 4 γ 4 γ 6 ]z [ γ 3 γ 4 γ 6 ]z Dz) where Dz) = γ 5 ) [ γ 4 γ 9 γ 0 ) γ 5 ]z [ γ 9 γ 4 ]z [ ]z [ γ 6 γ 9 γ 3 ]z Dz) 8 6 A S Low Q Biquad Q<) w o w o Q V w S o K o w o S s s V K K s V s) = $ k k s) s) ω o s Q V ' & s) ω o V ) and V s) = $ k 0 ' & s)ω o V ) s ω o 8 6
A S Low Q Biquad Q<)ont d w o Q w o w o K o A = V w o B = V K K Note the presence of the negative resistor ω o making it not practical as an active R filter. 8 63 A S Low Q Biquad Q<)ont d S Equivalent with switch sharing g g 4 γ TK o = H a 0)ω o T ω o γ γ 3 ω o T g g 5 g 3 A V γ 4 ω o T Q γ 5 K T Signal Flow Graph g 6 γ γ 6 K γ 4 γ γ 3 z z ) V z z z ) γ 5 γ 6 z ) 8 64
A S Low Q Biquad Q<)ont d Note for low Q the capacitance spread max min = ω o T = γ and for frequencies of interest ω << ω c ω o T << so that the capacitance spread will be large. The direct z transfer function of the circuit is given by H z) = γ 5 γ 6 )z γ γ 3 γ 5 γ 6 )z γ 6 γ 4 )z γ γ 3 γ 4 )z γ 6 = a 0 γ 5 = a γ 6 = a a 0 & γ = ) a γ 5 γ 6 ' * γ 3 γ 4 = b = a z a z a 0 b z b z b 0 ) = a 0 a a γ γ 3 = b γ 4 = b b γ 3 6 unknown values and 5 relations. One minimization constraint is to choose γ = γ 3 = b b 8 65 A S Low Q Biquad Q<)ont d Lowpass γ 5 = γ 6 = 0 Highpass γ = γ 5 = 0 Bandpass γ 5 = 0 Notch γ = γ 6 = 0 Possible Realizations of the lowq Biquad Allpass realizations are possible if an inverting S branch is added between the input terminal and node A with γ 5 removed. 8 66
A S High Q Biquad Active R Version o o K o K o V Q o V Hs) = V s) = K s K s K o s ω o Q s ω o 4 K 6 S Version 5 V 3 8 67 A S High Q Biquad ont d) Signal Flow Graph 4 6 z z) z 5 z z V z) z 3 z Hz) = V z) = γ 3 z γ γ 5 γ γ 5 γ 3 )z γ 3 γ γ 5 z γ 4 γ 5 γ 5 γ 6 )z γ 5 γ 6 ) γ 3 = a γ γ 5 = a a o γ γ 5 = a o a a γ 5 γ 6 = b o γ 4 γ 5 = b b o ) = a z a z a o z b z b o 8 68
S Filter Design Strategy using the Bilinear ztransform Given the specifications of the S filter in terms of the discrete frequency ω) the following is a step by step design strategy: $ Prewarp the specs using the equation Ω = f s tan ω ' & ) to obtain the f s continous time specs. Using available tables or formula for the continous time filter e.g. Butterworth hebychev, auer, etc) obtain H s) that meets the analog specs z Apply the Bilinear z transform s = f s to the analog transfer function z H s) to obtain the discrete time function H z), H z) = H s) s= fs z z H z) can be realized using the cascade approach. 8 69 ascade Realization of S Filters H z) is realized as a cascade of first and second order S building blocks. For n odd, H z) = a 0 a z b 0 b z For n even, H z) = n n k= α 0k α k z α k z β 0k β k z β k z α 0k α k z α k z k= β 0k β k z β k z nodd st Order Block Biquad Biquad... Biquad n)/ Biquad Biquad... Biquad n/) neven 8 70
Bilinear z transform of the general biquadratic transfer function Given H s) = a 0 a s a s b 0 b s b s then H z) = H s) s= fs z z where = α 0 α z α z β 0 β z β z α 0 = a 0 f s a f s ) a α = a 0 a f s ) and α = a 0 f s a f s ) a β 0 = b 0 f s b f s ) b β = b 0 b f s ) β = b 0 f s b f s ) b 8 7 S Design Example using the ascade approach Ex. 3 Design a S LP filter with equiripple response in both the passband and the stopband, that meets the attentuation specifications shown below. In your design use a sampling frequency f s = 8kHz. Soln. Prewarping the discrete time specs αω) db) 65dB αω) db) 65dB 0.5dB 0.5dB 0 0 ω p = 998.7 ω s =989.7 ωrad / s) 0 0 000 000 Ωrad / s) 8 7
S Design Example using the ascade approach ont d) From auer filter tables the desired order is 5th and the normalized transfer function is given by, H s) norm = 0.004605 s 0.396 s 4.36495 s 0.955s.0340 s 0.56773 s 0.58054s 0.55 H s) = H s) norm s= s 000 4.605 H s) = s 396. s 4.36495 0 6 s 9.55s.0340 0 6 s 0.56773 0 6 s 580.54s 5.5 0 6 The discrete time transfer function is therefore ) H z) = 0 4 z.9348z z 0.6059z.9604z 0.9763z 0.8388.5446z 0.8388z.807z 0.945z = H z) H z) H 3 z) 8 73 S Design Example using the ascade approach ont d) The first order building block g 4 g 5 g S / H V x g 3 V V z) = H z) = g $ γ γ 3 ' $ & ) γ γ ' & ) z γ 5 γ 5 γ = $ ' 4 & ) z γ 5 0 4 z ) 0.6059z 8 74
Let us choose γ = γ 3 = γ 4 = 0 S Design Exampleont d) γ γ 5 = 0 4 and γ 5 =/ 0.6059 = 0.6504. γ = 3.3 0 4 ' * This design yields a high capacitance ratio ) = 3030, which is not practical. 4 3.3 0 A simple solution is to distribute the gain evenly over each section. Hence each ) ' 3 = 0.058 ) = stage would have a gain of 0 4 *,, which is more practical. For 7 the new design then γ = 0.058 / 0.6059 = 0.0965. 0.6504 Note: The output is valid for both phases S / H 0.0965 V 8 75 S Design Example ont d) Biquad.9348z z H z) = 0.058.9604z. Using the simplified version of the general biquad 0.9763z with the output taken from the second opamp yields. γ H z) = 4 [ γ γ 4 γ 4 γ 6 ]z [ γ 6 γ 3 γ 4 ]z γ 5 [ γ 4 γ 9 γ 0 ) γ 5 ]z [ γ 9 γ 4 ]z = 0.058.9348z z.9604z 0.9763z The design equations are: γ 4 = 0.058 γ γ 4 γ 4 γ 6 = 0.058.9348 = 0. γ 6 γ 3 γ 4 = 0.058 γ 5 = γ 4 γ 9 γ 0 ) γ 5 =.9604 γ 9 γ 4 = 0.9763 There are 6 equations and 8 unknowns. We may therefore set γ 3 = 0 and γ 4 =. Solving yields γ 4 = γ 6 = 0.058,γ 9 = 0.037,γ = 0.05,γ 0 = 0.059 and γ 5 = 0 8 76
Biquad S Design Example ont d) H 3 z) = 0.058 0.8388.5446z 0.8388z. Using the simplified version of the.807z 0.945z general biquad with the output taken from the first opamp yields. [ H 3 z) = γ 4 γ 9 γ 0 ) γ γ 5 )] [ γ γ 3 γ 5 ) γ 6 γ 0 γ 9 γ 4 γ 6 )]z [ γ 6 γ 9 γ 3 ]z γ 5 [ γ 4 γ 9 γ 0 ) γ 5 ]z [ γ 9 γ 4 ]z The design equations are : ) γ γ 5 ) = 0.058 0.8388 = 0.0487 ) γ 6 γ 0 γ 9 γ 4 γ 6 ) = 0.058.5446 = 0.08959 γ 4 γ 9 γ 0 γ γ 3 γ 5 γ 6 γ 9 γ 3 = 0.058 0.8388 = 0.04865 γ 5 = ) γ 5 =.807 γ 4 γ 9 γ 0 γ 9 γ 4 = 0.945 There are 6 equations and 8 unknowns. We may therefore set γ 3 = 0 and γ 4 =. Solving yields γ 4 = 0.78,γ 6 = 0.836,γ = 0.5474,γ 9 = 0.058,γ 0 = 0.6608 and γ 5 = 0 8 77 Final Realization S / H 0.0965 0.6504 st Order Stage V 0.059 V 0.05 0.058 0.037 V Biquad 0.058 0.6608 0.5474 0.058 V Biquad 0.78 0.836 8 78
Switch Sharing 0.6504 S / H 0.0965 V 0.059 0.037 V 0.05 Switches can be shared to reduce hardware 0.058 0.058 0.6608 V 0.058 0.5474 V 0.78 0.836 8 79 Design of S Ladder Filters Procedure very similar to that of analog filters We have to employ a transformation because the analog prototype filter operates in s and the corresponding S filter operates in terms of z. Most used sz transformations are the LDI and the bilinear transformation. Note the bilinear transformation has zero phase error. LDI Approximate) s = T z z & $ ' jω = jωt T e e jωt & $ ' Ω = T sin ωt & $ ' ωt = ΩT & sin $ ' w digital frequency BDI Exact) s = z & T $ z ' ω = ΩT & T tan $ ' w digital frequency analog 0 W frequency 0 W analog frequency 8 80
General procedure for the Approximate Design of S Ladder filters A doubly terminated L two port is designed from the specifications. The specifications are prewarped using the relationship Ω = T sin $ ωt ' & ) Find the state equations of the resulting RL circuit. The signs of the voltage and current variables must be choosen such that inverting and noninverting integrators alternate in the implementation. onstruct the block diagram or SFG from the state equations. Transform it directly or via the active R circuit into the S filter. If necessary, additional circuit transformations can be performed to improve the response of the SF. These include modifications of the termination sections which improves the passband response or eliminating unnecessary capacitive coupling between opamps in circuits with high clock rates. 8 8 Design Example 3rd Order LPF I I 3 R s L V 3 V 4 I o R L I R Â I 3 R Â I o R R R s Rs L R s 3 Rs R R L Â V Â V 4 8 8
Design Example 3rd Order LPF ont d) W I 3 W EqualR R= Ohm) R s k R s r r 3 R L L V W W V 4 W I 3 W R s k R s 3 R L L Elimination of o p a m p b y using negative resistors V W W V 4 8 83 Inverting Integrator R s s H s) = R s s Noninverting Integrator L H inv z) = s z ) L R H s) = RL s z H noninv z) = L z ) z Note H z) = H inv z) H noninv z) = s L z K = $ z z ' & ) ) and H e jωt ) = K which is 4sin ωt & $ ' purely real Zero phase error) 8 84
R s Termination s s T R s R L L 3 3 Note that this termination results in a phase error. L T R L V s) I 3 = 0 = R s R s R s s ) V jω) = s T T s T ' jω * & s ) = s T T s Qj ) Q = ω T, represents an approximation error s 8 85 s Final Realization With Switch sharing f s s No Switch sharing f f L L f f 3 3 f f L L 8 86
Ladders with Finite Transmission Zeroes Procedure is the same as before except that we have to manipulate the SV equations slightly. I c I c = s V V ) R s I I V V L R s I I V V L 3 R L 3 R L R s I I V V L R s I I V V L I o I c I c 3 R L s V V ) s s V V ) s 3 3 R L 8 87 SV Equations are I = V s V R s V = s V = s 3 ) I I ) ) I I 0 ) = I 0 R L = V s ) V s s ) V s 3 R s  I  R s s ) sl s 3 ) R L s s V  V 8 88
Final Realization switch sharing) f s s A = A B = L = 3 f f B f f f f L 8 89 NonIdeal Opamp Effects Nonideal opamp effects such as D offset voltage, finite D gain, finite opamp bandwidth, slew rate, and charge injection are important considerations in S filters. D Offset voltage effect consider the simple lossy integrator with opamp offset voltage ff. ff ff n n 8 90
n n NonIdeal Opamp Effects ont d)d Offset v o n) v off n) = v o n & $ ' v off n & $ 0 ' v o n & $ ' v off n & $ = v ' o n ) v off n ) ) v c n &, $ v ' c n ) *. ) v c n &, v $ ' c n ) *. but v c n & $ ' = v off n & $ ',v c n & $ ' = v off n & $,v ' c n ) = v in n ) v c n ) = v o n ) and v off n) = v off n & $ = v ' off n ) Substitution and taking z transforms yields, z) = z ) z z z) z z ff z) If = 0 z) = ) z z ff z) Since ff is constant s = 0 z = = & ff $ ' is independent of the feedback capacitor. It depends on the ratio. 8 9 Simple Offset ancelation scheme PIS) a By charge conservation we can write 0 * $ α v off v off v in & n ' 3 ),. / 4 5 v off v o n) {[ ] v off } = 0 $ v o n) = αv in n ' & ) and taking z transforms yields ff H z) = αz If the clock phases at the input terminal are interchanged, then H z) = α Another circuit f f ff Show that for this circuit H z) = z Note the TF only valid for φ 8 9
Effects of the finite D gain Here we consider the opamp as having a finite D gain A o but an infinite bandwidth. v v n v o A o n n ) v o n) v o n) & $ A o ' = v ) o n v, o n,&. * *. ) v n) v n,&. A o $ * ' $ ' ) ) v o n v, o n,&. *. = * v o n A o $ $ ' ) v o n ) A o & ' 8 93 Effects of the finite D gain ont d) but v n) = v on) v in n) and v n & = 0 A o $ ' Substitution and taking z transforms yields, H z) = z) = ) A o & z $ A o ' ) ) ),. z * A = o z & ) ),. $ A o ' * A o ompare with the ideal transfer function H i z) = )z z Two observations: ) to a smaller value The gain is reduced from Pole previously at z = now has a smaller value = ) z 8 94
Effects of the finite D gain ont d) The ideal frequency response obtained from z = e jωt is H i e jωt ) = )e jωt j sin ωt and therefore $ ' & ) H e jωt ) = mω) jθω) H i e jωt ) where mω) = $ ' & ) and θω) = ) A o $ A o tan ωt ' ) for ωt << A & ) o ωt For A o >000 and typical values of and ωt, m << and θ << Except near ω = 0) For high sampling rates st <<), z = e st st [ ] st H s) = H z) z st = ) ) A o ) st A o ) [ ) A o ] H s) )T s A o T ) The s domain pole of the integrator is σ i = ) instead of s = 0 A o T H s) A oσ i s σ i 8 95 Effects of finite D gain on the Low Q Biquad w o Low Q Biquad w o Q V w S in o K o w o V S s s V If each ideal integrator is replaced by its lossy counterpart = Q new Q A o ωt ω onew) K K s &, F is the feedback capacitor $ F ' F = ω o ω oσ i Q σ i σ i As an example if A o =000, Q =5, and i ωt i =,) Q new 4.56. F Note the effect is worse for high Q biquads. The change in ω o is less dramatic. 8 96
Effects of finite D gain on Ladder Filters Recall in a ladder filter each integrator simulates a reactive L or ) element of the passive prototype filter. m s i If the element is m Ideal Integrator The branch simulated has the impedance Zs) = The quality factor of the capacitor is therefore, s m)σ i m). Q c = ωr c = ω = A oωt σ i ) = θω) The change in element value m) is usually neglible since the doubly terminated ladder is insensitive to such variations. The finite Q c can result in significant changes in the gain response, especially for narrow band filters with high Q poles. Lossy Integrator 8 97 Effects of finite D gain on Ladder Filters ont d) If the element is L L L m s i L m Ideal Integrator Lossy Integrator and Q L = ωl = ω = A oωt R L σ i Y s) = ) = θω) s L m)σ i L m) 8 98
Effects of Finite Opamp Bandwidth onsider the BEDI V For the opamp s) = ω o V s σ = s A o ω o unity gain bandwidth product of the opamp. where ω o = A o σ is the The above equation can be written in the time domain as v o t) dv o t) = v i t) A o ω o dt Using the opamp time domain behaviour the BEDI can be analyzed for samples v o nt ),v o nt T ), etc and the actual transfer function H z) = z) z) calculated and evaluated for z = e jωt. For the BEDI mω) = e k [ k cos ωt )] 8 99 and where Effects of Finite Opamp Bandwidth ont d) θω) = e k k sin ωt ) k = and k = k ω o T If we define a unity gain frequency ω i of the integrator as H i e jω it mω) θω) ω i Te ω o T where ω i T << is assumed. ) = then Thus if ω ot = πω o >> ω c clock frequency), then both mω) and θω) ω c become negligible. In general ω o 5ω c is usually adequate. The unity gain bandwidth of the opamp should be at least five times as large as the clock frequency ω c. 8 00
Effects of Finite Opamp Bandwidth ont d) For the FEDI and For ω i << ω c, mω) = k)e k θω) 0 mω i ) ω i Te ω o T Hence ω o 5ω c applies for the FEDI as well. 8 0 Effects of Opamp Slew Rate All opamps exhibit finite slew rates that are dependent on currents and capacitances in the output stage of the opamp. A typical output in response to an input step function might therefore look like; t slew t settle t Slew rate is defined as the maximum rate of change dv o dt. Thus S r = dv o = I L dt L where I L is assumed to be a load current and L the load capacitor. Note slew rate is not directly related to the frequency response. 8 0
Effects of Opamp Slew Rate ont d) For S circuits based on the assumption of a sine wave input whose highest passband frequency is ω B and amplitude is V max S r ω BV max t slew T ) with T = T T = and t slew t settle < T f c Note positive and negative slew rates exist. 8 03 harge Injection φ Due to overlap capacitance ol Signal Independent Δl = ol V DD V SS ) ol Due to channel charge ΔQ ch Signal Dependent ΔV ch = ΔQ ch / = µ oxw /L V GS V TH ) = µoxw /L V V V ) DD S TH 8 04
Solution Δl HalfSize Dummy Switch driven by omplementary clocks. Transmission Gate Fully Differential Approach φ φ φ φ φ φ φ φ Δl ) & Δl ) ancel each other 8 05 Solution Δl Delay locking Scheme. φ φ φ 4 φ 3 ut Due to φ : hannel harge Dependent on Due to φ 3 & φ 4 : hannel harge Dependent on GND an be removed Turning off φ 3 & φ 4 Earlier hannel harge of φ isolated from Use a ompensation apacitor Insert ) ΔQ ch which is stored on the compensation capacitor 8 06