Digitally Assisted A/D Conversion- Trading off Analog Precision for Computing Power UCB IC-Seminar November 25, 2002 Boris Murmann Prof. Bernhard E. Boser
Outline Motivation Research Overview Analog Errors and Digital Correction Correction Parameter Estimation Prototype IC Summary
Demand for High Performance ADCs Source: Analog Devices Increasing number of applications use sophisticated DSP
Modern Application 4 Million Transistors 50% P tot (ADC only) 802.11 Baseband Processor [Thomson et. al., ISSCC 2002]
Research Plan Goals: o Reduce power consumption of high performance ADCs o Improve compatibility with fine line technology Approach: o Relax analog domain precision o Recover ADC accuracy in digital domain
Outline Motivation Research Overview Error Analysis and Digital Correction Calibration Technique Experimental Results Conclusion
Research Vehicle: Pipelined ADC V in S/H STAGE 1 STAGE N-1 STAGE N R bits (e.g. R=1) V in A/D D/A - 2 R V res res V D D=0 D=1 Predominant topology for wide performance range: 10-14 bits, 10-200MHz V in
Relax Analog Precision? V in A/D D/A - 2 R V res D Digital correction helps tolerate large sub A/D errors [Lewis, 1987] Digital calibration removes D/A and linear gain error by adjusting digital weights [Karanicolas, 199]
Relax Analog Precision? V in - 2 R V res A/D D/A D Digital correction helps tolerate large sub A/D errors [Lewis, 1987] Digital calibration removes D/A and linear gain error by adjusting digital weights [Karanicolas, 199] Remaining burden: Fast, highly linear gain element 50-70% of total pipeline ADC power is consumed by interstage amplifiers
Conventional Gain Element E.g. [Kelly, ISSCC 2001] Electronic feedback linearizes, stabilizes High gain requirement costs headroom and/or additional stages power penalty Semiconductor technology trend: Decreasing VDD and low intrinsic device gain!
Precision Amplifier Alternatives Low loop gain Open loop Power Precision Sensitivity Power Precision Sensitivity
Research Overview V D Digital Post- D raw corrected in ADC Processor Aspects: Analog domain errors (1 st and 2 nd order) Digital correction mechanism Error measurement and tracking
Outline Motivation Research Overview Analog Errors and Digital Correction Correction Parameter Estimation Prototype IC Summary
Precision Requirements V in STAGE 1 STAGE i V resi STAGE i+1 STAGE N V ini A/D D/A - 2 Ri ε i V resi A/D Backend B bits Residue errors must be < ½ LSB of backend converter E.g. -bit Stage1 in 12-bit converter 9-bit backend ε 1 <0.1%
Basic Amplifier Considerations 1.5 R R 1 Diff. Pair TF Tangent V o 0.5 V i I SS Vo/(ISS*R) 0-0.5-1 V 2 V i dsat max =? -1.5-1.5-1 -0.5 0 0.5 1 1.5 Vi/Vdsat Example: Simplest possible topology What fraction of transfer function should be used?
Transfer Function Nonlinearity V V = I SS R V 1 + 4 β V β V 2 1 V 8 V 1 V 128 V 0 i i i i dsat dsat 2nd order (Device Mismatch) dsat dsat rd order 5th order (Gain Compression) 5... Linearity Error [%] 10 1 10 0 10-1 10-2 10-2nd order (0.5% mism.) rd order 5th order 0.1% 10-4 0.1 0.2 0. 0.4 0.5 0.6 0.7 0.8 Vi/Vdsat rd order error unavoidable 5 th and higher order error small for V imax 0.5V dsat Desirable to neglect high order terms Design implications?
Design Example V ˆ in = V ref A/D D/A - Vˆ x V! ref = 0. 5 V R 2 2 R dsat V ˆ = V res ref V ref R Vˆ V x dsat 1 500 mv 1V 2 250 mv 500 mv 1V 125 mv 250 mv 4 62.5 mv 125 mv (headroom, g m /I D ) Simple diff. pair practical for stage resolution R>2 Third order error model sufficient in this case
Pipeline Stage Model a V x a 2 V x 2 V in a 1 A/D D/A - V os V res D 2 R How can we correct errors digitally?
Offset Pushthrough a V x a 2 V x 2 V in a 1 V os A/D D/A - V res -V os D Input referred converter offset, does not harm linearity Equivalent sub-a/d offset can be addressed with digital RSD arithmetic [Lewis, 1987]
Gain Error Pushthrough a V x a 2 V x 2 V in 2 R /a 1 a 1 A/D D/A - V res D
Gain Error Pushthrough a V x a 2 V x 2 V in 2 R /a 1 a 1 A/D D/A - V res a 1 /2 R D Correct digital weight of sub-conversion [Karanicolas, 199] Results in (often) tolerable input referred gain error
Second Order Cancellation V x V res a 1 a 2 V x 2 a V x V res b1 b V x V x s b 0? If a 0: 1 0 2 2 1 ) ( ) ( s x b s x b b x a x a x a + + = + + = = = = 2 2 1 2 2 0 2 2 1 1 27 2 : a a s a a a a a b a a a b a b With
Use of Digitized Residue V in STAGE 1 STAGE i V resi STAGE i+1 STAGE N b V x V ini - b1 V resi A/D D resi A/D D/A b 0 -b 0 D Compensate error using digital backend representation of residue Add 1-2 bits to backend to reduce quantization error
Third Order Correction b V x b 1 V res A/D - b V x D res
Third Order Correction V res b 1 A/D b V x - e(v res ) D res 0 : 27 1 2 cos 1 cos 1 2 ) ( 1 1 < = + = b b p with p V p V V e res res res π
Third Order Correction b V x V res b 1 A/D D res - D' res e(d res ) Single-parameter correction function can be precomputed and stored in look-up table (ROM) Small ROM size achievable through continuous data compression methods
Complete Digital Correction V in A/D D/A - V res a 1 V x +a 2 V x2 +a V x A/D D res p 2 D' res e(d' res ) - D'' res p 1 p D a 1 1 2 p1 p2 p R a a 2 a a a 1 How can we measure parameters in digital domain?
Outline Motivation Research Overview Analog Errors and Digital Correction Correction Parameter Estimation Prototype IC Summary
Calibration Concept Classical Approach: Problem: V in A/D D out Chip Temp. Power-Up Idle Test Signal Param. Calibration Circuit Bad time to calibrate! Calibrate now? Time Correction parameters depend on temperature, etc. Classical foreground calibration unfeasible Need continuous background calibration during normal A/D operation
Key: Two-Residue Pipeline Stage V in A/D D/A - V res SHIFT D 1 1 0.5 0.5 Vres/Vref 0 Vres/Vref 0-0.5-0.5-1 -1-0.5 0 0.5 1 Vi/Vref -1-1 -0.5 0 0.5 1 Vi/Vref Add: Digital SHIFT signal, redundant A/D and D/A states Can carry out conversion on red or black segments
Digitized Segment (a 2 =0) no calibration: h 1 <h 2 perfect calibration: h 1 =h 2 Dres (0...2 B -1) h 1 h 2 Dres (0...2 B -1) h 1 h 2 0 0.1 0.2 0. 0.4 0.5 Vi/Vref 0 0.1 0.2 0. 0.4 0.5 Vi/Vref Idea: Measure h 1, h 2 and force difference to 0 How to measure without interrupting A/D operation? Solution: Statistics based measurement
Distance Estimation (1) Dres (0...2 B -1) "Red" with Prob. 1/2 "Black" with Prob. 1/2 Input Samples V in (k) For each input sample fair coin toss [independent of V in (k)] decides red/black
Distance Estimation (2) Dres (0...2 B -1) q CH ref (q) f(v in (k)) v q v in Simple input model: stationary random process Count # of codes q in black channel cumulative histogram CH ref (q)
Distance Estimation () Dres (0...2 B -1) h CH(j+m) CH(j) CH(j-m) H* CH ref (q) f(v in (k)) Place counter array in red channel v q After n samples, find red count that is closest to CH ref (q) Distance Estimator H* v in
Distance Estimation (4) Dres (0...2 B -1) f(v in (k)) h CH(j+m) CH(j) CH(j-m) H* CH ref (q) Can show: lim E( H*) h n var( H*) F ( v n q ) 2 f ( v q 2B ) 2 F(v q ) v q v in Estimation fails if signal not busy around v q Detectable!
LMS Loop V ini V resi STAGE i A/D D resi b - D' res Update rate: f s /n e(d' res ) p Distance Estimation H 1 H 2 - Accum. µ Accumulator forces average H 2 -H 1 to zero Tradeoff: Residual variance of p vs. tracking time constant Straightforward extension to track p 1, p 2
Tracking Time Constant Avg. Time Const. [msec] 1000 800 600 400 200 0 10 11 12 1 14 N Converter Resolution [bits] τ Example : k = B = N f AVG s = 100MHz 2 0.6 k 2 2 f ε s 2B Confidence Backend res. Sampling rate ε = 0.5 LSB precision [bits] Example: N bit converter with -bit Stage1, uniform input distribution Must address/attenuate potentially faster variations in analog domain
On-Chip Temperature Variations µp Temperature Map [Najm, EEdesign 01/09/01] Local g m R replica bias Solutions: Local replica biasing Rule of thumb, d=200µm: T remote / T local >10, τ=100µs Keep distance to hot spots, common centroid layout
Outline Motivation Research Overview Analog Errors and Digital Correction Correction Parameter Estimation Prototype IC Summary
Note: Slides 40-46 were removed due to prepublication restrictions. Please Refer to my publication at ISSCC 200 for a deatialed description of the prototype.
Potential Deep sub-µm: P analog P digital P saved Multi-stage calibration Topological optimization Vision: 12b, 200MHz ADC in 0.1µm Net savings 70% possible!
Summary Open loop amplification o o Reduces ADC power consumption Improves deep sub-µm compatibility Resulting analog errors o o Slow -> statistics based digital calibration Fast -> analog domain techniques Demonstrated feasibility through 12b, 75MSa/sec prototype IC Future Work: Optimized deep sub-µm implementation
Acknowledgements High Speed Converter Group, Wilmington, MA o Katsu Nakamura, Sudhir Korrapati, Dan Kelly, Larry Singer, Will Yang, Doug Mercer, Richard Schreier, Steve Reine,... ADSiV San Jose ADBrk Berkeley