Technology Trend of ADCs

Technology Trend of ADs Akira Department of Physical Electronics Tokyo Institute of Technology 008.04.5 LSIDAT A.

ontents Issues of pipeline ADs Revolution of SA ADs Fight back of pipelined ADs What determines FoM Summary 008.04.5 LSIDAT A.

Megatechnology trend of ADs 3 Major conversion scheme is now changing from pipeline to SA st stage nd stage Pipeline AD f f Op amp Op amp s Sample s Amplify MP DA MP DA st stage nd stage SA AD 4 8 6 6 008.04.5 LSIDAT A.

4 Issues of pipeline ADs (current major AD architecture) 008.04.5 LSIDAT A.

Pipeline AD 5 Folding I/O characteristics makes higher resolution along with pipeline stages. Hold Sample Amplify Transfer characteristics st stage Sample Amp. Sample Amp. st Stage nd Stage ref ref nd Stage Sample Amp. Sample Amp. ref 0 ref ref 0 0 ref X ref X ref 008.04.5 LSIDAT A.

.5bit/stage Pipeline AD 6 Amplification at each stage reduces the input referred thermal noise..5b/stage architecture reduces the requirement for Lewis et al., JSS '9 the comparator offset drastically. Ginetti et al., JSS '9 Amplifiers determine AD performance Transfer characteristics omparators don t affect the performance. R S f i R R R 4 R 4 LATH MUX R R SUBAD DA X GAIN 008.04.5 LSIDAT A. s S 3 Unit conversion stage for.5bit/stage pipeline AD o o = s i f s f s i f i i f i f ref ref R if if i < 4 4 ref if i > 4 ref ref i 4 ref

Issues of pipeline ADs 7 Major issues of pipeline ADs are caused by OpAmp. G D ( db) > 6N 0 0b :70dB b :8dB dd eff Sub00nm MOS n G A D 6dB n eff 0.5 n < 5 G n D < 80 db 7 in v outv out in sig_max dd 4 A[] 6 5 4 3 A I g g G = g ds m ds ds = eff A 350nm 80nm 50nm 30nm 90nm L eff 0 0 0. 0. 0.3 0.4 0.5 0.6 0.7 ds[] 90m 0.3μ 0.8μ 0.5μ 0.35μ 008.04.5 LSIDAT A.

Performance model for pipeline AD 8 We have developed the performance model for pipeline AD that can treat technology scaling. g N f GBW f c 3 s ω OpAmp p s pi gm po RL OL β= L m _ close = β> π L f = ol po = f s s ol f pi f f ( ) s o s pi s pi = = = f ol g, R m s pi ol L ωp : Transconduc tance of input stage f, : Signal capaci tance for po : input & putput paracitic capaci tance : Load capaci tance : Output resis tance : Second pole of OpAmp feedback loop A., Analog I Technologies for Future Wireless Systems, IEIE, Tan on Electronics, ol. E89, No.4, pp. 446454, April, 006. GBW _ close = gm π I ds = π o o eff pi po pi o o o α pii ds α poi ds o o α pi I o ds 008.04.5 LSIDAT A.

p and o for several design rules 9 ap. [ff/ma],f T [GHz] W[μm/mA] p will be reduced by technology scaling, however o will be increased by operating voltage reduction. N L 9 W = I.66 0 ds o μ ox eff =0.75 eff sig 000 00 0 p /I & W/I vs. design rule gd 0. 0. 0.3 0.4 0.5 L[μm] 008.04.5 LSIDAT A. gs W f T / S S: Scaling factor sig o [pf] ( m ) = dd 000 00 0 0. 0.0 0.00 0.05 o vs. design rule 4bit bit 0bit 8bit eff Single stage: m= Double Stage: m= m= 0. 0.5

Performance summary 0 0000 Scaled MOS is effective for just low resolution AD. Scaled MOS is not effective for high resolution AD. 0000 000 000 fc[mhz] 00 fc[mhz] 00 0 8bit 0 0bit 0.0 0. 0 Ids[mA] 0.0 0. 0 Ids[mA] 90nm 0.3μm 0.8μm 0.5μm 0.35μm 90nm 0.3μm 0.8μm 0.5μm 0.35μm 000 00 00 0 fc[mhz] 0 fc[mhz] bit 0. 0.0 0. 0 Ids[mA] 90nm 0.3μm 0.8μm 0.5μm 0.35μm 008.04.5 LSIDAT A. 0. 4bit 0.0 0.0 0. 0 Ids[mA] 90nm 0.3μm 0.8μm 0.5μm 0.35μm

Speed and power FoM onversion speed has saturated at 00 MHz Lower mw/mhz is needed for low power operation. = Power[mW] f c 0000 000 00 P d ENOB High Speed AD [Sampling Freq. S Power] b 0b 600 fj 00fJ/onvsteps 0b JSS,ISS,LSI,I,ESS & Products ( 0Bit, 0MSps) 995006 bit :mw / MHz 0bit : 0.3mW / MHz (006) 0.mW / MHz (007) 0 00MHz ISS 007 0 00 000 0000 Sampling Freq.[MSps] 008.04.5 LSIDAT A. Bit(Paper) 0Bit(Paper) Bit Products 0Bit Products.

Revolution of SA ADs (Low FoM AD architecture) 008.04.5 LSIDAT A.

SA AD 3 Successive Approximation AD is free from OpAmp design issues and looks suitable for sub00nm MOS era. Require only capacitors, switches, comparator, and logics. No quiescent current extremely low power Binary search algorithm DA in FS 4 FS FS FS 8 6 FS 4 8 6 6 FS FS 8 FS MP in b = b = b =0 b = b 3 = b = b 3 = b 4 = b =0 b =0 008.04.5 LSIDAT A.

Performance overview of SA ADs 4 0000 Power[mW] 000 00 0 0. 0.0 0.00 SA ADs become dominant in every performance range. In particular FoM has rapidly lowered. SAR AD Power vs Sampling Freq. 0. 0 00 000 0000 00000 Sampling Freq.[MSps] /00 during past three years. ourtesy Y. Kuramochi ISS008 4bit bit FoM[fJ/conv.step] 09bit 75bit 000 00 0 0. FoM fj/conv. steps 005 006 007 008 009 00 Year 008.04.5 LSIDAT A.

Recent SA AD 5 SAR AD must be one of the good solution for scaled analog technology. No OpAmp is needed. No static power consumption. Higher signal swing and small capacitance INp TP TP QP SP M= N 4 Q REF = i i U DD U TN SN INn LK cn cp TN QN Track Sample Reset cp[0..n] Precharge omp cn[0..n] Result SAR ontroller B[0..N] J. raninckx and G. an der Plas, A 65fJ/onversionStep 0to0.7mW 9b harge Sharing SAR AD in 90nm Digital MOS, IEEE ISS 0007, Dig. of Tech. Papers, pp.46 47, Feb. 007. 008.04.5 LSIDAT A.

Analog operation with capacitances 6 apacitances can realize analog operation for SAR AD. No static current is required and higher signal swing can be used. QP SP c0n c0p 8 U SN QN c0p c0n Precharge Precharge Track Sample Precharge ompare c0n c0p Qn Qp S Q = IN 8 U 008.04.5 LSIDAT A. DD Q = ± S 8 64 U IN U DD... DD

Results 7 9 Amazing small FoM=65fJ/conv.steps has been attained. ENOB 8 7 6 Fs = 50MS/s P = 75µW k 0k 00k M 0M Input frequency [Hz] 8bit, 0.3mW at 0MHz J. raninckx and G. an der Plas, A 65fJ/onversionStep 0to0.7mW 9b harge Sharing SAR AD in 90nm Digital MOS, IEEE ISS 0007, Dig. of Tech. Papers, pp.46 47, Feb. 007. ISS06 Fs P FoM Arch. ENOB Paper # [MS/s] [mw] [fj] 3. TΔΣ 40 50 300 3.4 ΔΣ 4.4.6 3.8 500. PL 00 9.4 39 570.3 Subr. 50 0.4 30 440.4 PLBS 7.9 8.7.5 760.5 SAR 0. 0.5 0.05 70.7 PL 50 9. 5 50 3. Flash 50 3.7.5 60 3.5 SAR 300 5.3.65 0 This work SSAR 0 7.8 0.9 65 008.04.5 LSIDAT A. FoM includes Ref. lock Dec. Yes Yes No No No No No Yes Yes Yes

High resolution and high speed SA AD 8 To increase the resolution, a preamplifier is located in front of a comparator Segmented capacitor array M. Hesener, A. Hanneberg, D. Herbison, F. Kuttner, and H. Wenske, A 4b 40MS/s Redundant DAR AD with 480MHz lock in 0.3um, IEEE ISS 007, Dig. of Tech. Papers, pp.4849, Feb. 007. 008.04.5 LSIDAT A.

Results 9 High conversion rate of 40MS/s H and low power of 66mW have been attained i High ENOB of 3.5bit has been gattained FoM=40fJ/convsteps h 0.3um MOS Supply voltage Input range Sample frequency Internal clock frequency Analog power Digital power Total power.5 ±0.9 diff. 40MHz 480MHz 49mW 7mW 66mW 008.04.5 LSIDAT A.

World lowest FoM AD 0 Extremely low FoM of 4.4fJ/convsteps. SA AD has been realized M. van Elzakker, Ed van Tujil, P. Geraedts, D. Schinkel, E. Klumperink, B.Nauta, A.9uW 4.4fJ/onversionstep 0b MS/s harge Redistribution AD, IEEE ISS 008, Dig. of Tech. Papers, pp.4445, Feb. 008. Simple SA architecture Multistep charging can reduce energy more E diss = n eq n b = n eq b Multistep charging (Adiabatic charging) 008.04.5 LSIDAT A.

Summary of performance Extremely low FoM has been attained!! SNR (db) THD (db) DNL (LSB) INL (LSB) SNDR (db) ENOB (bit) E conversion (pj/conversion) Figure Of Merit (fj / conversionstep) Average 55.6 6. 0.49.4 54.4 8.75.9 4.4 Standard deviation 0.58.95 0.06 0.8 0.47 0.08 0.4 008.04.5 LSIDAT A.

omparison with stateoftheart ADs FOM (fj / conversionstep) 000 00 0 Low FoM <00fJ/conv.steps ADs become major. 4.4fJ/conv.steps is the world lowest!! This work 3.5...3.4.5.6.7.8 ISS 007 ISS 008 008.04.5 LSIDAT A.

Massively parallel high speed SA AD 3 Input. pp diff. power splitter.5 subad (6) T/H array (96) T/H array (8) 60 6b SA ADs realize 4GS/s conversion P. Schvan, et. al., A 4GS/s 6b AD in 90nm MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.544545, Feb. 008. # of ADs = 6 0 = 60 8 8 subad (9) multiphase clock generator subad (8) subad () 6 6 6 6 :8 demux lock 48 70MHz sync. 48 :8 demux :8 demux :8 demux 48 48 One AD: 50MS/s Memory array SFI4 offset cntrl gain cntrl timing cntrl DA array DA array DA array 008.04.5 LSIDAT A.

Summary of performance and comparison 4 Packaged AD performance Ramp generator Resolution 6 bits onversion 0. 4GS/s rate omparators Input range. pp diff. T/H array ENOB average cal / Lim. 4./4.8, amplifiers F in = 8GHz lock gen. cal each freq 3.5/4., F in = GHz SFDR 40dB @ 8GHz 35dB @ GHz Power.W @ and.5 AD core 4 x 4 mm Process 90nm MOS subad FoM, pj/conv. demuxes demuxes However FoM is about 3pJ/conv. (Large) 50 Encoder 40 30 0 0 [Lee 03] [Poulton 03] FoM = P F in ENOB [Schvan 06] [Nosaka 04] [Harwood 07] This work 0 0 5 0 5 0 5 30 Sampling rate, GS/s 008.04.5 LSIDAT A.

5 Fight back of pipeline ADs 008.04.5 LSIDAT A.

Optimization of OpAmp in Pipeline AD 6 90nm MOS, near subthreshold operation, and S levelshift have realized 0bit 80MHz AD with 0.8 operation and small power of 6.5mW FoM=00fJ/conv.step M. Yoshioka, M. Kudo, T. Mori, and S. Tsukamoto A 0.8 0b 80MS/s 6.5mW Pipelined AD with Regulated Overdrive oltage Biasing, ISS, Dig. Tech. paper, pp. 45 453, 007. 008.04.5 LSIDAT A.

Results 7 Excellent FoM has been attained in spite of pipeline AD. FoM=00fJ/conv.step 0.08mW/MHz Technology Resolution onversion Rate Active Area Input Range Supply oltage SNDR Total Power onsumption INL DNL P0M 90nm MOS with MIM apacitors 0bit 80MS/s.8mm x 0.54mm.pp Differential 0.8 55.0dB @MHz 5.4dB @4MHz 6.5mW <.0LSB < 0.8LSB. 56.9dB @MHz 55.6dB @4MHz 3.3mW < 0.5LSB < 0.4LSB SNDR [db] SNDR [db] Fclk=80MS/s, Fin=MHz Ta=73K Ta=373K 60 50 40 30 Slow/Slow 600.6 0.7 0.8 0.9...3 50 40 30 Fast/Fast 0.6 0.7 0.8 0.9...3 Supply oltage [] 008.04.5 LSIDAT A.

Process improvement of MOS transistor 8 No pocket transistor with low threshold voltage transistor offers low onresistance for switches M. Boulemnakher, E. Andre, J. Roux, F. Paillardet, A. 4.5mW 0b, 00MS/s Pipeline AD in a 65nm MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.505, Feb. 008. Lmin (HPA)=0.4um Ron [Ohms] 50 00 50 00 Ron versus input (in) w=cste Ron HPA Ron LT t [] 0,75 0,65 0,55 0,45 0,35 0,5 t versus length ( L) HPA LT 50 0,3 0,5 0,7 0,9 in [] 0,5 0 0, 0,4 0,6 0,8 L [ µ m] 008.04.5 LSIDAT A.

Optimization of MOS transistor 9 Nopocket MOS transistor can increase output resistance and results in increasing the D gain. 008.04.5 LSIDAT A.

Summary of performance 30 This pipeline AD has attained excellent low FoM compared with SA AD Resolution Sampling speed Input range Power onsumption SNDR DNL INL Active area Technology 0 bit 00MS/s.0ppd 4.5mW 59dB /0. LSB /0. LSB 0.07mm^ ST MOS 65nm FoM= 6fJ/conv.step Tech DD Fs Power SNDR FOM References (nm) () (MHz) (mw) (db) (pj/step) 30. 0 90 57..5 B.Hemes ISS004 90. 3.3 5.6 0.76 R.Wang ISS005 90. 00 35 56.9 0.6 G.Geelen ISS006 90.0 00 33 55.3 0.69 K.Honda JSS007 90 0.8 80 6.5 55 0.7 M.Yoshioka ISS007 65. 00 4.5 59 0.06 This work 008.04.5 LSIDAT A.

3 Our original work What determines FoM OpAmp based design vs. comparator based design 008.04.5 LSIDAT A.

OpAmp based vs. comparator based 3 Pipelined AD st stage nd stage Opamp base f Op amp f Op amp s Sample s Amplify MP DA MP DA SA AD omparator base st stage nd stage 4 8 6 6 008.04.5 LSIDAT A.

Noise of OpAmp 33 Amplification phase f 0 g s pi v m v g g i n po v o Op amp Op amp Op amp /g o v no n = 0 m L kt f i γ n kt = ( g β) ( ω ) βl γ n kt v no = β n=: ascode n=3: Folded ascode L kt 008.04.5 LSIDAT A. f df v nt f = s = o o 0 : : : kt v no v γ n kt β n = L n v = v n kt i N i kt vi = v i o i = N kt = i = β β v L ni L = v kt o ni γnkt β L

FoM calculation 34 OpAmp consumes power, however operating frequency is just f c and total power is only.5x of st OpAmp. v nt qn 0 kt γnkt γn = 0 βl β q dd eff = = N 3 3 γn kt > β qn kt 0 if nt = qn γn β kt o < qn f close > Nf g β > Nf g > Nf π π c m c m c o ds eff 3 π L 3 3β gm, I ds > Nf c o eff 3β I P.5 ( I ) = 0I d FoM P d = N f c 0.5 008.04.5 LSIDAT A. ds dd ds dd

Estimated FoM for pipeline ADs 35 kt n dd eff γ = =.0( ) = 0.5( ) β = 3 f = 00MHz c = 4. 0 = We are reaching the theoretical limit of FoM Resolution o (pf) I dd (ma) 0 0.37.75 6.0 33.6 Analog portion only 4 95 68 Recent AD dd pp =.( ) =.0 f c = 00MHz o = 0.4pF Pd = 4.5mW SNDR = 59dB FoM = 6fJ P d (mw) FoM(fJ).75 4 M. Boulemnakher, E. Andre, J. Roux, F. Paillardet, A. 4.5mW 0b, 00MS/s Pipeline AD in a 65nm MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.505, Feb. 008. 008.04.5 LSIDAT A. 33.6 6 68 54

SA AD 36 SA AD needs high speed switches, comparators, and logics. apacitor omparator Logics T bc Switches ref in ( N ) E b P f d c E b : Energy / conv T T T T bc set cmp Tc = f ( N ) T bc 008.04.5 LSIDAT A. c = Tdig : Logic delay time dig T T T bc set cmp : Bit cycle time : Switch settling time : omparator decision time

omparators 38 Dynamic comparators are widely used for not only SA ADs but also Flash ADs omp INp INn DD Dynamic comparators use the fast voltage fall depended on input voltage difference Fast voltage fall OUTn OUTp b FN INP LK LK GND INN FP. Giannini, P. Nuzzo,. hironi, A. Baschirotto, G. van der Plas, and J. raninckx, An 80uW 9b 40MS/s Noise Tolerant DynamicSAR AD in 90nm Digital MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.3839, Feb. 008. 0 b FN FP SP LK SN SP LK M. van Elzakker, Ed van Tujil, P. Geraedts, D. Schinkel, E. Klumperink, B.Nauta, A.9uW 4.4fJ/onversionstep 0b MS/s hargeredistribution AD, IEEE ISS 008, Dig. of Tech. Papers, pp.4445, Feb. 008. 0 0 SN 008.04.5 LSIDAT A.

Issue of comparator for SA ADs 39 A comparator has noise and this results in conversion error.. Giannini, P. Nuzzo,. hironi, A. Baschirotto, G. van der Plas, and J. raninckx, An 80uW 9b 40MS/s Noise Tolerant DynamicSAR AD in 90nm Digital MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.3839, Feb. 008. 5b harge Redistribution (R) SAR AD ref INp b0 b b b3 b4 OK! in INp INn 0/ SAR 7 ref LK Noise Distribution INn INp 0 b0 b b b3 ERROR! b4 8 3σ σ σ omparator Threshold 3σ 008.04.5 LSIDAT A. INn 0 0

omparator noise and ENOB 40 Low comparator noise is required for SA AD σ σ < < 0.5LSB 0.5LSB : bit deg rade : 0.5bit deg rade Ideal σ =LSB/3 σ >σ 9 8.75 σ/lsb=0.4 ENOB=8.09 Binary Output 0.5 ENOB 8.5 8.5 0 0.5 0 0.5 d/lsb. Giannini, P. Nuzzo,. hironi, A. Baschirotto, G. van der Plas, and J. raninckx, An 80uW 9b 40MS/s Noise Tolerant DynamicSAR AD in 90nm Digital MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.3839, Feb. 008. 008.04.5 LSIDAT A. 8 0 0.05 0. 0.5 0. 0.5 σ/lsb

Expected FoMs for comparators 4 FoM due to comparator is not negligibly small. Operating frequency is (N)f c and power increases with N. Recent SA ADs are reaching the limit. p d = FoM = ( N ) f c p f c L d N 0.5 dd L > 0 4 0 N f c =00MS/s γ =, dd =.0, eff = 0. Resolution 0 4 M. van Elzakker, Ed van Tujil, P. Geraedts, D. Schinkel, E. Klumperink, B.Nauta, A.9uW 4.4fJ/onversionstep 0b MS/s harge Redistribution AD, IEEE ISS 008, Dig. of Tech. Papers, pp.4445, Feb. 008. L (ff) P d (mw) FoM(fJ) 4 0..4 670.9 6.5 000 34 30 008.04.5 LSIDAT A.

Redundant architecture 4 ombination of Large and small comparators and one redundant conversion increase AD performance without serious FoM degradation. INp σln OUTp Monte arlo on 9b SSAR σhn compl OUTn alid 9 8.75 ENOB0.75 INn omp Noise comph. Giannini, P. Nuzzo,. hironi, A. Baschirotto, G. van der Plas, and J. raninckx, An 80uW 9b 40MS/s Noise Tolerant DynamicSAR AD in 90nm Digital MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.3839, Feb. 008. ENOB 8.5 8.5 8 Standard Redundant NoiseTolerant ENOB0.3 ENOB=8. omparators are sized so that σhn ~/6 LSB and σln ~/ LSB Good ENOB improvement with Noise Tolerant correction 7.75 σ/lsb=0.7 0 0.05 0. 0.5 0. 0.5 σ/lsb 008.04.5 LSIDAT A.

Technology trend of ADs 43 SA ADs become major, but. Architecture Flash Twostep parallel Pipeline SA Period 7888 88 95 95 x 06 Technology Bipolar/MOS BiMOS, MOS MOS MOS Parallel/Serial Parallel Twostep, Semiparallel Serial (Pipeline) Serial Base omparator omparator Amplifier omparator Gain No No (Yes Interpolation) Yes No Sampling No Yes Yes Yes Transistor mismatch omparator mismatch apacitor mismatch apacitor mismatch Accuracy omparator noise Amplifier gain omparator noise Settling OpAmp noise Settling Speed Device ft ReferenceSwitch OpAmp GBW omparatorlogic omparatorlogic Switch Switch Interpolation Redundancy Redundancy (.5b) Serial apacitor Averaging Interpolation Gain boost Dynamic comparator Design technique Folding Averaging OpAmp sharing Interleaving Dynamic comparator Gain boost alibration alibration Dynamic comparator 008.04.5 LSIDAT A.

Summary 44 Pipelined ADs, current major AD architecture are now facing serious issues; Low OpAmp gain Low voltage operation larger capacitance Scaled device is not suitable for higher resolution SA ADs becomes attractive and looks suitable for scaled MOS Extremely Low FoM Simple; needs only capacitors, switches, comparators, and logics. Free from OpAmp issues Pipelined ADs have fight backed Same FoM as SA AD, owing to process improvement What determines FoM and which is better. Pipeline: OpAmp SA AD: omparator SA is better in FoM, however the difference is not large. Attention to the sensitivity of comparator for SA AD design 008.04.5 LSIDAT A.