Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

Transcription

1 Modelg d ly o Ho Spu DLL-Bed Fequey Sytheze Oj, Behzd Megzdeh d tl lvdpou Lköpg Uvety Pot Pt.B.: Whe tg th wok, te the ogl tle. Oj, Behzd Megzdeh d tl lvdpou, Modelg d ly o Ho Spu DLL-Bed Fequey Sytheze, 4, IEEE to o Cut d Syte Pt : Regul Ppe, 6,, IEEE. Peol ue o th tel petted. Howeve, peo to ept/epublh th tel o dvetg o pootol pupoe o o etg ew olletve wok o ele o edtbuto to eve o lt, o to eue y opyghted opoet o th wok othe wok ut be obted o the IEEE. Potpt vlble t: Lköpg Uvety Eleto Pe

2 Modelg d ly o Ho Spu DLL-Bed Fequey Sytheze Oj, Studet Mebe, IEEE, Behzd Megzdeh, Mebe, IEEE, d tl lvdpou, Seo Mebe, IEEE btt Peod jtte e the ho pu t equey ytheze output petu, dow-ovetg the outo-bd teee to the deed bd d ouptg the wted gl. h ppe popoe opeheve behvol odel o pu htezto o edge-obg dely-loked loop DLL-bed ytheze, whh lude the eet o dely th, tt phe eo SPE, d duty yle dtoto DCD. Bed o the popoed odel d utlzg Foue ee epeetto o DLL output phe, lytl odel whh oulte the ytheze pu-to-e to SCR developed. Moeove, o tttl ly o the lytl devto, loed-o expeo o SCR obted, o whh pu-we ytheze deg low popoed. Eployg th low d wthout Mote Clo MC ethod, oe detee the equed tge-dely tdd devto SD o DLL-bed ytheze, t whh et puou peoe deded by tget wele tdd ted. deg exple peeted whh utlze the popoed deg low to ulll the SCR equeet o -45 db o WMed-UWB tdd. to-level MC ulto o the ytheze SCR o tdd 65- CMOS pleetto exhbt good ople wth lytl odel d pedto. Idex e dely th, DLL, duty yle dtoto, edge-obe, equey ytheze, ho pu, peod jtte, tt phe eo. D I. IRODUCIO ELY-LOCKED loop DLL-bed equey ultple hve expded the pplto dug the lt dede to wele outo yte []-[8]. Eetl DLL htet uh the eltvely wde loop-bdwdth, t lok- te, lted-uultve jtte, d t-ode tblty, dte the potetl o DLL-bed equey geeto hee [9]. Howeve, degg uh yte o RF pplto, whee e gl o et petl puty ut be povded, h t ow hllege. Se the uulted do jtte wth the dely le eet bk to zeo t evey eeee lok edge, edge-obg DLLbed ytheze exhbt lt phe oe pole [], [4]. O the othe hd, the DLL loked to the eeee peod d the e geeted by obg the equllyped DLL edge, y lget o thoe edge eult peod jtte d e the eeee ho pu t ytheze output petu, dow-ovetg the out-o-bd teee to the deed bd. Oe o the jo otbuto to the level o puou toe uh ytheze the duty yle dtoto DCD o the eeee lok well the tel DLL phe. I ddto, the tt phe eo SPE betwee the eeee d eedbk gl ued by up/dow pulewdth d uet ble phe deteto PD d hge pup CP epetvely, deteote the puou peoe. Moeove, dely the og dely tge the dely le, de by the lol utug peeto, wll lo led to ho pu. Ipled by the thg popete o MOS deve [], to ze the dely th betwee dely tge, lge-e deve hould be utlzed. Due to toht tue o the th, tttl ulto uh Mote Clo MC wth lge ube o ple hould be peoed o ute pedto o the ytheze puou peoe. Howeve, o uh oplex d lted-bdwdth eedbk yte whh eque lge ettlg te o eh MC ple, ut-level MC beoe exteely ubeoe. ow ode tht to ty et equeet o ho pu d to vod ove-zg the dely tge whh led to e d peed pelte, optl deve ze eed to be oud by tetvely povg the ut pete d peog ew et o ut-level MC to vey the obted peoe. Coequetly, to elete the deg poedue, t ul to develop ute behvol odel o the pu htet o DLL-bed ytheze, whh lude ll the oue o peod jtte. thoough lytl odel whh oulte the puou peoe te o DCD, SPE d dely tdd devto SD hee o get teet. ew wok [4], []-[] hve tuded the pu htet o edgeobg ytheze, o whh [4] d [] lt the ly olely to the eet o SPE. I [], the eet o dely th lo luded, but the odel utozed oly o g edge obe EC d doe ot ode the eet o DCD o ytheze ho pu. Whe both the lok edge o the DLL phe e ued by the EC, the duty yle vto o thoe phe wll geete peodty. h ple tht bede SPE d dely SD, the level o ho pu beoe lo uto o DCD, whh ot odeled []. heeoe, t ot be eployed geel odel o edge-obg ytheze o pu htezto. I th wok, we popoe opeheve behvol odel o edge-obg DLL-bed ytheze, whh lude

3 e PD Ф UP D CP -tge VCDL Edge Cobe Ф V ot e the pt o DCD well the SPE d dely th, o ytheze puou peoe. Utlzg th odel d the Foue ee epeetto o ultphe DLL output, lytl odel developed, oultg the ytheze pu-to-e to SCR. We uthe expd ou ly by d o tttl ethod, to obt loed-o expeo o e SCR d t pobblty dety uto PDF. Utlzg ou loed-o oul, we popoe pu-we ytheze deg ethodology. Eployg th deg low d wthout MC ulto, the equed dely SD whh te et SCR equeet, be utely etted. Bed o the lulted dely SD, oe deg the oepodg dely tge ut. he ppe ogzed ollow. Seto II popoe behvol odel o edge-obg DLL-bed ytheze. I Seto III, lytl odel deved o the Foue ee epeetto o ultphe DLL output. Stttl ly whh eult loe-o expeo o ytheze pu level peeted Seto IV. I Seto V, pu-we ytheze deg ethodology popoed whh utlzed the deg exple o Seto VI to d the equed tge-dely SD whh te the puou peoe o WMed ult-wdebd UWB tdd. Flly, the ppe oluded Seto VII. II. BEHVIORL MODEL OF DLL-BSED SYHESIZERS Code the edge-obg DLL-bed ytheze dg how Fg., whee the yte loked to eeee lok equey e d geete e t = e by obg evely-ped DLL phe. o hteze the puou peoe, we popoe behvol eedowd odel o the -lok ytheze, whh ode the eet o the dely th, DCD, d SPE. ote tht the odel developed bed o gllg uet uto EC [] whh eploy voltge-touet V-I ovete tge how Fg. b. he htetue eque voltge-otolled dely le VCDL wth odd ube o dely tge. evethele, the odel gee d be ppled to ytheze o othe type o DLL/EC oguto. o odel the dely th, we ue tht the dely o eh tge do vble o ol dtbuto. ote tht tve pleetto o the dely tge uh the oe Fg., pull-up d pull-dow pt epoble o delyg the llg d g edge V p V Ф I- Ф I+ Ф v+ Ф v- out Fg.. Blok dg o DLL-bed EC equey ytheze, b V-I ovete tge o EC, d tve pleetto o the dely tge. b e Ф Ф Ф e epetvely, e o deet phyl popete. h ple tht the g edge te dely Δt d, d llg edge te dely Δt d,, expeee deet th pole. heeoe, we odel the two depedet Gu do vble t ~,, t ~, d, d, whee µ, σ, µ, d σ e the e d ve o Δt d, d Δt d,, epetvely. wveo epeetto o the popoed ytheze odel llutted Fg.. o detee Δt d, d Δt d,, we ue tht the DLL loked to the eeee lok peod e, but wth te-do SPE o pe. So, the totl VCDL dely legth would be. VCDL lok We ue tht the e o the g d llg edge dely e equl. So, o the -lok DLL wth -tge VCDL,. 3 k e / dd e lok Hee, Δt d, d Δt d, o the th dely tge, e epeeted lok td, tvg G, lok td, tvg G 4 whee Є [, ], d G d G e depedet zeo-e Gu vble, epeetg the dely th o g d llg edge, epetvely, d extted o Δt d, d Δt d, to ply the ly. So, G,..., ~,, G,..., ~,. 5 G e µ -t vg +G µ -t vg+g +k µ -t vg +G +G µ -t vg +G + +G lok pe G ote tht t vg oet dely whh ppled by the lokedloop to ll the tge, uh tht depte the dely th, the totl VCDL dely legth t equl to lok. I ou eedowd odel, th tully odel the thvegg htet o the -lok DLL. o lulte t vg, we ue g-edge-loked yte. So, lok t d µ -t vg +G +G +k pe Fg.. Wveo epeetto o -tge DLL-bed ytheze ludg DCD, SPE d dely th eet. ω e t... Δe=µ - t vg +G Δll=µ - t vg +G Δe=µ - t vg +G +G Δll=µ - t vg +G +G... Δe=µ - t vg +G + +G Δll=µ - t vg +G + +G, +... ω e t+... Fg. 3. Popoed e-do eedowd odel o -lok DLL-bed EC ytheze.. 6

4 3 I ddto, we wte o 4 tht d, lok vg t t G. 7 ow, o 6 d 7, t vg oud do vble tht ot o the veged u o do vble tht t vg G ~,. 8 ote tht pete k Fg. odel the put lok pulewdth. So, the te-do DCD vlue dd wtte / k 9 dd e lo ote tht etoed pevouly, pt o the DCD o the eeee lok, the duty yle lo dtoted due to the heet deee phyl popete o pull-up d pulldow deve. By lety, t be how tht the o-lled tel duty yle dtoto IDCD wth dely tge ollow ol dtbuto deed IDCD t t ~. d, d,, he bove expeo ple tht ute to zg betwee the pull-up d pull-dow deve, ued 3, oly elte the e o IDCD, deottg tht the te-tge DCD oelted to the dely th. Fg. 3 dept the te-do blok dg o ou eedowd odel whee the obed output, otg the udetl well eeee ho opoet, geeted by uto o the te-hted veo o the g d llg eeee lok edge. he odel pleeted MLB d the SCR t ytheze output petu o eh MC ple o dozed G d G vlue lulted by tkg the t Foue to FF o the output gl. h odel eployed eeee o puou peoe ly upog eto. III. LYICL MODELIG USIG FOURIER SERIES Bed o the todued behvol odel Seto II, we develop lytl odel whh oulte the ytheze puou peoe te o DCD, SPE d dely SD. Cotg the gtude, phe d equey oto o peod gl, Foue ee e eet tool o lyzg the que wve ultphe DLL output. I ppedx, we deve the Foue ee o the EC output gl o thoe o the DLL output phe odg to Fg.. eult, Foue oeet o the ytheze output epeeted k G tvg o e t dt e Gtvg k e e pe o k e whee, ω e, d e the pltude, gul equey d tege ho dex o the eeee lok, epetvely, d d e do vble deed Fg. 4. MC htog o e SCR; behvol v. lytl odel 5. G G, G G. Slly, o b oeet o the EC output, we wte b k e e pe k 3 e We ow d the gtude o the veto, b whh epeet the output pu gtude o gve ho loted t = e. hu, S jb b. 4 he ytheze SCR gtude theeoe expeed SCR S jb b 5 C jb b whee C the udetl toe e gtude, loted t d lulted o 4 o =. o vey the deved lytl expeo, Fg. 4 ope the MC htog o the SCR dtbuto obted o ou eeee behvol odel, wth tht o tted o the lytl odel 5. ote tht o the ulto peeted the uet eto well Seto IV, we utlze the ollowg pete, ule othewe peed. he eeee lok e = 4 MHz d the VCDL h = 5 tge, geetg e t =5 4 MHz. he SCR ulted o the lget pu loted t = e =. Futheoe, dd d pe e ued to be % d % o the e tge-dely µ=p, whh e p d p, epetvely. lo, the uel g d llg edge dely SD vlue e σ /µ = σ /µ = % = p. ow, to que bette ght to 5, we dept the depedee o the e SCR, uto o the dely SD, DCD, SPE, d. It be obeved o Fg. 5 d b tht the SCR olely deed by the dely SD o ll vlue o DCD d SPE, epetvely, d thee pete get lge, the SCR beoe uto o DCD d SPE well. heeoe, t ul to t DCD d SPE uetly ll, o tht we eetly get beet o edug the dely SD. O the othe hd, o gve dely SD, ovepovg the SPE d DCD, ght ot hve gt otbuto loweg the level o pu, thee ext lowe boud o SCR deed by the dely SD. Fo th pe exple, t be obeved o Fg. 5 d b, tht eve wth qute ll dely SD o σ/µ =.%, puhg dd d pe below p d p, epetvely, would ot pove

5 4 b Fg. 5. Sulted e SCR o the ytheze o the lytl expeo 5, uto o olzed: DCD, b SPE, d tge-dely SD. b Fg. 6. Gphl tet o te 6 o d b = : -lok olty, b ope-loop olty, d zeo-e d equl-ve. SCR uh. lo o the e o σ/µ = %, t be oted o Fg. 5b tht by puhg pe below 5 p, we do ot g y uthe pu uppeo. Fg. 5 llutte how the SCR hge the dely SD ve o deet. be obeved, o xed DCD d SPE, d gve olzed dely SD o σ/µ = %, eg o 5 to 5 to heve hghe e equey o 5 te, eult bout 7 db degdto puou peoe, eve though the dely SD led wth to keep σ/µ ott. IV. CLOSED-FORM EPRESSIO FOR SYHESIZER SCR I th eto, we uthe expd ou lytl odel o the pevou eto by utlzg oet ethod d ylo ee ppoxto, d obt loed-o expeo o the e d PDF o SCR t ytheze output petu. eult, we ette the ytheze puou peoe wthout peog MC. I pt, we lyze the do vble S 4,.e. the ho pu gtude, d how tht t be ppoxted Rylegh do vble. o ette the SCR dtbuto 5, we how pt B tht the do vble C,.e. the e gtude, be ppoxted ott vlue tht equl to t e.. Mgtude o Spuou oe Povded tht the pu Foue oeet d b t the EC output epeeted by d 3, e two depedetly d detlly dtbuted d Gu do vble o zeo e d equl ve σ o,.e., ~,, b ~,, 6 o the the pu gtude S b o wll be Rylegh do vble [3]. ug d b e depedet, the te o 6 e ted, we eetly hteze the ho pu o the ytheze, ug the popete o Rylegh dtbuto. o vetgte 6, we tt o the olty tet. Stttl ppohe volve lulto o kewe d kuto o the oeet. I th wok, we ue gphl ppoh whh h le oplexty d wok well o ou ppoxto. Ug d 3, the MC htog o the output pu Foue oeet e plotted Fg. 6, dtg tht t well wth t oepodg Gu dhed uve. he obeved kew b htog due to the g-edge-dely th vegg htet o the DLL, whoe veged vlue t vg ppled to both the g d llg edge dely, odg to 4. h be veed by plottg the htog Fg. 6b, o opeloop e t vg =, whee o kew o b obeved. evethele, the kew the loed-loop e ll, b oeet lo odeed ol vble. o evlute the Foue oeet o the output pu uto o dely SD, we utlze the ve oul o v E E 7 whh E[] the expetto opeto. It be peted o Fg. 6, tht o ll dely SD, the ve d eod oet E[ ] e equl o eh oeet, dtg tht the oepodg e vlue E[] e uetly ll to be odeed zeo. I ddto, t be oted tht the ve o d b e lot detl o ll SD. h ple tht the te o 6 be odeed vld log the dely SD t uetly ll. h t the e the otext o equey ythe wth tget equeet o pu level. heeoe, we

6 5 ppoxte the gtude o the output pu S Rylegh do vble wth PDF d e tht e expeed epetvely exp x x x x x p o o 8 / o S E 9 whee σ o = v[ ] v[b ]. o detee 8 d 9, we eed to d the t d eod oet o the output Foue oeet, d lulte the ve o 7. So, we expd the expeo o oeet o o o o whee, e, e k, e k o d k pe e e o k pe e e. 3 I ppedx B, we t ply by utlzg the t d eod-ode ylo ee ppoxto o e d oe epetvely, d the obt the e o by dg t t oet. h be lly doe o b. eult, E 4 E b. 5 lo dued ppedx B, to d ve, we detee E[ ] d E[ ], d ubttute the 7 to get v. 6 Slly o b oeet, the ve deved b v. 7 he vlue o σ o 8 d 9 be ppoxted by the veged u o 6 d 7 v v e o b 4. 8 o vey the deved e d ve expeo, we plot the dhed le Fg. 7 d b, epetvely, d ope the wth thoe oepodg vlue tted o MC o ou lytl odel 5. be obeved, o ll dely SD, the deved expeo th the ulto. Fo lge dely SD, the uy degde due to the low-ode ylo ee whh w utlzed to ppoxte d b. oethele, hghe ode ylo ppoxto whh eult oplex devto would ot be eey, beue etoed beoe, the lge vlue o SD e t voded due to the tget equeet o ytheze output pu level. B. Mgtude o Spu-to-Ce Rto SCR dted pevouly by 5, the ytheze SCR the b Fg. 7. Pedted d ulted e, d b ve o the Foue oeet d b o the output pu, uto o olzed dely SD.

7 6 b Fg. 8. Sulted e d ve o the e d pu gtude C d S uto o olzed dely SD, b ulted e d ve o the e Foue oeet d b uto o olzed dely SD, d ulted d pedted ytheze SCR o the pu t = e. b Fg. 9. Cloed-o oul 33 v. MC o 5 o ytheze e SCR uto o olzed DCD: pe =, b pe = p, d pe = p. to dtbuto o Rylegh do vble S ove the do vble C,.e. the gtude o the udetl toe. Foue oeet o C,.e., d b, e lulted o d 3 epetvely, o =. I ode to hteze the to do vble SCR, we dept the e d ve o S d C uto o dely SD Fg. 8. It be obeved tht the e o the udetl toe E[C], uh lge th t ow ve v[c], well the e E[S] d ve v[s] o the ueto S. heeoe, we ppoxte the SCR dtbuto by eplg C wth t e, d ody 5 SCR S EC. 9 o d E[C], we plot the e oeet d b Fg. 8b d obeve tht the e vlue E[ ] d E[b ], e uh lge th the ve v[ ] d v[b ]. So, we ppoxte E[C] C E b E Eb E. 3 Show Fg. 8b, the ppoxted E[C] loely the t MC-ulted outept. Fo ll dely SD vlue, 3 be uthe pled to EC k e pe pe e e, pe 3 Flly, SCR the to o Rylegh vble S to ott, we ue lety to ppoxte SCR lo Rylegh vble wth PDF d e o x Rexp x R x p x 3 x whee / E SCR R 33 E C. 34 R o Logth epeetto o the PDF 3 obted by hge o vble, eultg Log-Rylegh PDF [4] o y y p y exp. 35 Y R R o vey the ly, the dtbuto o the ytheze SCR llutted Fg. 8. he dhed uve how the olzed loed-o SCR PDF o 35, d the b ht the SCR htog obted o MC o ou lytl odel. C. Cloed-Fo Expeo uy I th pt we evlute the uy o the popoed Rylegh-ppoxted loed-o oul, o lge vto SPE, DCD, d dely SD. o do o, we ode ou deet olzed dely SD vlue o σ/µ =.%,.8%,.4%, d %, well thee SPE vlue o pe =,, d p. he we weep DCD o dd =. to 3 p. Fg. 9 plot the lulted e SCR vlue o the loed-o expeo 33 d ope the wth the MC-ulted SCR o the lytl odel 5. Show Fg. 9, wth zeo SPE, the ulto d pedto ollow eh othe eve t lge DCD o 3 p. ll oet o le th db obevble o the lge dely SD o σ/µ = %, whh le wth ou duo the pevou pt, d dppe the dely SD get lle. O the othe hd, the DCD d SPE vlue get uh lge oped to the dely SD vlue, the uy get degded. ly o evel ulto

8 7 Set, e Fd SD x o 4 DCD, SPE Set SD = SD x P [db] IEEE 8. IEEE 8.b/g & WL BG 6 Bluetooth 7dB 65dB BG BG BG 3 BG 4 BG 5 Ette hevble DCD d SPE Fd σ o d σ R o 8, 3, [MHz] Fg.. WMed-UWB equey lloto d the oextg tdd. Redue SD o Clulte e SCR o 33 SCR SCR pe dte tht t lge DCD d SPE vlue o whh pe dd, 36 the te o 6 whh equed o Rylegh ppoxto, would ot ty yoe. Howeve, o eoble vlue o SPE, DCD, d dely SD the otext o equey ythe, the popoed loed-o expeo pedt the SCR o the lget pu, wth eptble uy. Fg. 9 deotte tht le th db eo SCR etto be obted eve o ll dely SD o σ/µ =.%, d wth eoble DCD d SPE vlue o dd = p d pe = p, hevble tte-o-the-t CMOS pleetto [], [6], [5]. V. SPUR-WRE SYHESIZER DESIG FLOW Bed o ou ly Seto IV whh led to loeo oul o the output SCR, we ow popoe puwe DLL-bed equey ytheze deg low. h ethodology detee the equed vlue o the tge-dely SD, t whh et puou peoe SCR t ytheze output heved. Se the popoed deg low doe ot eploy MC ulto, the ovell tetve deg poe to d the equed dely SD eleted. Po to dug the low, we t deve expeo o the bet SCR o gve dely SD, whh heved whe SPE d DCD e eglgbly ll. o do o, we t ply the ve o the output pu Foue oeet whh gve 6 d 7. Fo pe dd, we hve o / v, 37 / e o / vb, / e vb 38 v o, 39, / lo o vey ll SPE d DCD vlue, the e gtude o the e = 3 pled e E C. 4 e Ye e Bed o the lulted SD, ze the dely tge [] Fg.. Flowht o the popoed pu-we deg low. ow, by ubttuto o 39 d 4 to 33 d 34, the lowe boud o the hevble e SCR deteed E SCR. 4 / he bove expeo dte the bet hevble pu uppeo o gve dely th d vey ll SPE d DCD vlue. ow, by kowg the puou peoe peto SCR pe o the tget tdd,.e. the xu llowed pu-to-e level, we eoulte 4 to d uppe boud o the olzed dely SD, / SCR pe. 4 he popoed pu-we ethodology llutted o o low ht Fg.. Ft, o the peto o the tget wele tdd, whh povde oto uh the equey bd, hel pg, d wthg te, we detee the deg pete ludg the eeee lok equey e, d the ube o dely tge. he o 4 we d the uppe boud o the dely SD, SD x, by whh gve SCR pe te whe SPE d DCD e uetly ll. tewd, to ode the eet o ozeo SPE d DCD, we ue the tlly-lulted SD x well the etted hevble SPE d DCD vlue, to lulte σ o o 8, E[C] o 3, d lly σ R o 34. ow we detee the povded e SCR o 33. I t lge th SCR pe, the we pove ou tl dely SD d lulte the ew e SCR, d epet th poedue utl SCR SCR pe. Bed o the lulted vlue o the equed dely SD, oe do the zg o the dely tge tto ug l ppoh []. VI. WIMEDI-UWB SYHESIZER; CSE SUDY I th eto we eploy the popoed deg low Seto V to d the equed tge-dely SD o DLL-bed equey ytheze, whh te the puou peoe equeet o WMed-UWB bdgoup BG tdd [6].. Deg Poedue he petu lloto o the tdd well the oextg wele tehologe llutted Fg.. he pu uppeo equeet o WMed-UWB lulted o the teee eo [7]. be ee Fg., beue o the tog out-o-bd teee o IEEE 8. /b/g, thoe puou toe whh ll wth.4 to 5 GHz ge, hould t below -45 db [7], [8]. ote

9 8 V p = 37V V = 8V tht the SCR povded by the DLL be elxed by ew db depedg o the ytheze htetue. he V-I ovete-bed EC wth LC tk lod [] wll bd-p-lte the pu to oe extet, depedg o t Q to. I ddto, utlzg twe the equed put equey d peog equey dvo to geete qudtue e, wll lo uppe the pu level. heeoe, we ue 6 db o uppeo ledy povded, plyg tht SCR pe o - 39 db hould be delveed. Show Fg., WMed BG ot o thee ub-bd wth ete equee t 64 3, 64 5, d 64 7 MHz, epetvely. Hee, ub-bd 3 h the xu ube o dely tge = 7. Moeove, eeee lok o e = 64 MHz utlzed. Followg the popoed low, we lulte SD x o 4 whh povde SCR pe=-39 db o the lget ho pu = 6, /7 x.43%. 43 We ow ue th vlue log wth ou etted hevble vlue o SPE d DCD,.e. pe =.µ p d dd =.µ p, epetvely, to lulte the povded e pu uppeo o 33, E SCR 6, log R, / 38 db. 44 db Se th vlue lge th SCR pe, we edue the olzed dely SD o.43% to.4% e.g., σ = σ =.3 p d lulte the ew SCR E SCR 6, log R, / 39 db. 45 db Coequetly, we hve deteed the vlue o dely SD, o whh the equed SCR pe by WMed-UWB ted. ow by kowg the equed dely SD, tto zg o the dely tge ut tghtowd. he th htet o MOS tto well-tuded ubjet. he tdd devto o the d uet I d d thehold voltge V th due to the deve th debed by the ollowg equto [], I d Vth 46 I WL V V WL d V DD =. V 6/.8 V th =-3V 5/.4 5/.4 /.8 V th =98V V V 47 th WL whee WL the deve e, d β d Vth e the tehology-depedet ott. he bove equto dte tht eg the ovedve voltge wll edue the devto o I d, d eg the tto e WL lt the devto GS th 5/.4 V th =-36V out 5/.4 V th =358V Fg.. Dely tge; uet-tved vete wth output bue. th V p Duy D D 7 Duy e = 58 MHz dd = p pe p V Ф t vg = V-I out = 7 58 MHz Ф V-I Ф 7 V-I 7 Fg. 3. Sulted tetbeh o WMed-UWB ytheze. Due to opeloop opeto, tvg =, d pe y lghtly devte o p o eh MC ple. Fg. 4. SCR dtbuto t WMed-UWB ytheze output petu, o the ho pu t = + e. o both V th d I d. lyt odel o the dely tge l to tht [] be developed to ette the equed tto e. I ode to povde the equed thg wth optu deve e, we hve utlzed low thehold voltge LV deve to ee the ovedve voltge. he tto zg d bg detl egdg tdd 65- CMOS pleetto o uet-tved dely tge whh povde the lulted olzed dely SD o =.4%, e dted Fg.. ote tht to ytheze the e o ll thee ub-bd o BG, the ube o dely tge VCDL hould be eoguble [4], [9] og = 3, 5, d 7. h ple tht lthough deee whe the ytheze wthe to the lowe ubbd, the otol voltge lo dop. he voltge dop vlue deped o VCDL voltge-to-dely te uto. Hee, the SCR peto o the ytheze put lowe boud o the VCDL g by dtg the u toleble ovedve voltge t whh SCR pe lo te o ub-bd. B. Evluto o the Reult I th pt we peet the tto-level MC ulto eult egdg the puou peoe o the DLL-bed WMed-UWB ytheze, dued pt, d ope t wth ou lytl devto. he ulted ytheze tetbeh depted Fg. 3. I ode to edue the MC ulto te, we eple the DLL wth ope-loop VCDL o 7 uet-tved dely tge o Fg., whle ott loop otol voltge utlzed. We lo ue 7 del V-I ovete d hot the output to peo edge-obg uto d geete the ultpled e equey = 7 58 MHz. he MC ulto o the tto-level D

10 9 tetbeh peoed ug Spete Cdee tdd 65- CMOS poe. o ee the ulto uy, we et the tolee opto eltve tolee = -5, bolute voltge tolee = -8, d bolute uet tolee = - 3. lo, ode to peed up the ulto, we ebled the eleted pllel ulto PS d ultthedg wth 6 thed o 6 vlble poeo. he b ht Fg. 4 how the tto-level MC htog o the WMed-UWB ytheze output SCR, o the eeee ho t = + e = 954 MHz. he dhed le epeet the olzed pedted PDF o the WMed-UWB ytheze SCR, ug the popoed loed-o oul o Log-Rylegh ppoxto 35. ote tht og thoe ulto pete lted Fg. 4, the ued SPE vlue o pe = p be lghtly deet o the e o tto-level MC ulto, ope loop VCDL utlzed t vg=. Wth the bove oguto d ettg, the eued ulto te egdg gle deg teto ug 4 MC ple o the ope-loop VCDL bout /ple. ote tht the ulto te beoe eve hghe whe utlzg loed-loop DLL o ulto. By eployg the popoed ethodology o the othe hd, the deg teto e peoed o the loed-o expeo Fg., whee o ulto volved. It be obeved o Fg. 4 tht the pedted SCR PDF egdg the lget out-o-bd ho pu t DLL-bed WMed-UWB ytheze output petu ollow the oepodg MC htog. lo the equed SCR pe o -39 db ted d the pedted d ulted e SCR vlue e loely thed wth le th db eo. Codeg the utlzed vlue o DCD, SPE, d dely SD, th eult le wth the uy odto 36. VII. COCLUSIO Fxed-ptte jtte DLL-bed edge-obg equey ytheze geeted due to phe lget o the DLL output edge. he eultg ho pu dow-ovet the out-o-bd teee to the wted hel, ouptg the deed gl. h ppe popoe opeheve behvol odel o DLL-bed equey ytheze whh lude the eet o dely th, SPE, d DCD o ytheze puou peoe. Fo the popoed odel d eployg the Foue ee ly o the DLL output edge, lytl odel obted whh oulte the pu-to-e to SCR, t ytheze output. he lytl expeo uthe developed by eployg tttl ethod, to deve loe-o expeo o the ho SCR. Bed o ou loed-o devto, puwe deg low todued whh detee the equed tge-dely SD o gve SCR peoe wthout ug MC ulto, whh peed up the ovell tetve deg poedue. expeetl e, the popoed deg ethodology utlzed to lulte the tge-dely SD o DLL-bed ytheze, t whh the SCR o WMed-UWB tdd ted. Bed o the lulted dely SD, the dely tge the deged tdd 65- CMOS poe. to-level MC ulto egdg the ytheze puou peoe deotte good ople wth behvol odel d lytl pedto. PPEDI he Foue ee o the th DLL output phe egletg the DC opoet expeed t, o e t b, e t. 48 Fo the wveo epeetto o Fg., the Foue oeet,φ d b,φ 48 e expeed k G tvg, e Gtvg k G tvg b, e Gtvg o t dt 49 e t dt. 5 Se the EC output otuted by uto o the ultphe DLL gl, t Foue ee be wtte out t t o t, e b, e t o e t, e t b,. 5 Ipled by lety 5, Foue oeet o the EC output e the u o Foue oeet o the DLL phe,,, b b, PPEDI B e. 5 pplyg ylo ee ppoxto to, we get. 53 he e o deved o t t oet E E E E E. 54 o lulte E[ ], we t utlze to wte E E 55, E E. 56 he o lety, we lulte the equed expetto E E 57 E E

11 o obt ve, E[ ] d E[ ] e equed. he oe deteed o 54. he ltte deved by lultg o 53, d the pplyg the expetto. Subttutg the eultg ppoxted expeo to 7, v B C 6 whee E 6 B E 6 C E 63 REFERECES [] G. Che d P. R. Gy, 9-MHz Lol Ollto ug DLL- Bed Fequey Multple ehque o PCS pplto, IEEE J. Sold Stte Cut, vol. 35, o., pp , De.. [] J. Zhug, Q. Du, d. Kwewk, -7 db khz e oet -GHz DLL-bed equey ytheze, Po. IEEE Cuto Iteg. Cut Co., pp. 3 34, Sep. 3. [3]. C. Lee d K. J. Ho, DLL-bed equey ultple o MBO-UWB yte, Po. Syp. VLSI Cut Dg. eh. Ppe, pp. 4 45, Ju. 5. [4]. C. Lee d K. J. Ho, he Deg d ly o DLL-Bed Fequey Sytheze o UWB pplto, IEEE J. Sold Stte Cut, vol. 4, o. 6, pp. 45 5, Ju. 6. [5] S. Gekk, 8 MHz - db/hz-t- khz lok ultple bed o obto o PLL d eultg DLL, Po. IEEE It. Sold-Stte Cut Co., pp , Feb 8. [6] P. C. Mulk d D.. Mee, DLL-bed pogble lok ultple.8μ CMOS wth -7 db eeee pu, IEEE J. Sold-Stte Cut, vol. 4, o. 8, pp , ug. 7. [7]. Kh, M. Ho, K.L.E. Lw, Low Powe Fequey Sytheze o 6-GHz Wele Peol e etwok, IEEE. Cut Syt. II: Exp. Be, vol.58, o., pp. 6 66, Ot.. [8] H. J. g et l., DLL-Suppoted, Low Phe oe Ftol- PLL wth Wdebd VCO d Hghly Le Fequey Rp Geeto o FMCW Rd, IEEE. Cut Syt. I: Reg. Ppe, vol. 6, o., pp , De. 3. [9]. Elhzly et l.,.5ghz 89uW Dgtl MDLL wth 4 Itegted Jtte, -55.6dB Reeee Spu d /V Supply-oe Setvty Ug b DC, Po. IEEE It. Sold-Stte Cut Co., Dg. eh. Ppe, pp. 4 44, Feb.. [] M. J. M. Pelgo,. C. J. Duje, d. P. G. Welbe, Mthg popete o MOS tto, IEEE J. Sold-Stte Cut, vol. 4, o., pp , Ot [] J. Zhug, Q. Du d. Kwewk, oe, pu htet d -lok eo eduto o DLL-bed equey ytheze, Po. It. Co. Cou., Cut Syt., pp , Ju. 4. [] O. Ch et l., ly o the Spu Chtet o Edge- Cobg DLL-Bed Fequey Multple, IEEE. Cut Syt. II: Exp. Be, vol. 56, o., pp. 3 36, Feb. 9. [3] J.G. Pok, d M. Sleh, Dgtl Couto, 5 d Edto, MGw Hll, 8. [4] B. Rvet, L. G d C. Jutte, Log-Rylegh Dtbuto: Sple d Eet Stttl Repeetto o Log-Spetl Coeet, IEEE. udo, Speeh, Lg. Poe., vol. 5, o. 3, pp , M. 7. [5]. l, et l., 4.6GHz MDLL wth -46dB eeee pu d petue poto tug, Po. IEEE It. Sold-Stte Cut Co. Dg. eh. Ppe, pp ,. [6] Hgh te Ult Wdebd PHY d MC Stdd, ECM d Edto, De. 8 [Ole]. [7] K. Iewk, Wele ehologe: Cut, Syte, d Deve. ew Yok: CRC Pe, 7. [8] M. M. Izd d C. Hg Pule Shpg ehque o Spu Suppeo Ijeto-Loked Sytheze, IEEE J. Sold Stte Cut, vol. 47, o. 3, pp , M.. [9]. Oj, B. Megzdeh, d. lvdpou, DLL-Bed Ijeto-Loked Fequey Sytheze o WMed UWB, Po. IEEE It. Sypou Cut Syt., pp. 7 3, My. Oj S eeved the M.S. degee eletl egeeg o Lköpg Uvety, Lköpg, Swede, 8. He uetly wokg towd the Ph.D. degee t Lköpg Uvety. Betwee 8 d 9, he w wth Eo B, Lud, Swede, whee he woked o lok geeto d dtbuto o Eo oble plto. H eeh teet lude pheloked yte d RF ytheze. Behzd Megzdeh S M 9 eeved the B.S. degee eletl egeeg o Sh Uvety o ehology, eh, I,, d the M.S. d Ph.D. degee eletl egeeg o Lköpg Uvety, Lköpg, Swede, 4 d 8, epetvely. He uetly tt Poeo t the Deptet o Eletl Egeeg, Lköpg Uvety. H eeh teet lude lowpowe lokg tehque, lok geeto d equey ytheze, d hgh-dt-te wele outo yte. D. Megzdeh w the epet o the 5th IEEE Mdwet Sypou o Cut d Syte Bet Studet Ppe wd 7. tl lvdpou M 99 SM 4 eeved the M.S. d Ph.D. degee o Lköpg Uvety, Swede, 995 d 999, epetvely. Fo 999 to 3, he w eo eeh ett wth Cut Reeh Lb, Itel Copoto. I 3, he joed the deptet o Eletl Egeeg, Lköpg Uvety, Poeo o VLSI deg. Se 4, he the hed o Eleto Deve dvo. H eeh teet lude vou ue deg o tegted ut d yte dved ole tehologe, wth pel ou o eet dt ovete, wele teve ot-ed, ohp lok geeto d ytheze, eo tee eleto, lowpowe/hgh-peoe dgtl ut d eoe, d hp deg tehque. He h publhed oe th ppe tetol joul d oeee, d hold 4 U.S. ptet. Po. lvdpou eo ebe o IEEE, d h eved o y tehl pog ottee o IEEE d othe tetol oeee, ludg the IEEE Sold-Stte Cut Coeee ISSCC, d Euope Sold-Stte Cut Coeee ESSCIRC. He h lo eved guet edto o IEEE JOURL OF SOLID-SE CIRCUIS.