Analysis and design of a high-efficiency zero-voltage-switching step-up DC DC converter

Transcription

1 Sādhanā Vol. 38, Par 4, Augus 2013, pp c Indian Academy of Sciences Analysis and design of a high-efficiency zero-volage-swiching sep-up DC DC converer JAE-WON YANG and HYUN-LARK DO Deparmen of Elecronic & Informaion Engineering, Seoul Naional Universiy of Science and Technology, Seoul , Souh Korea hldo@seoulech.ac.kr MS received 22 Sepember 2011; revised 13 June 2013; acceped 26 June 2013 Absrac. A high-efficiency zero-volage-swiching (ZVS) sep-up DC DC converer is proposed. The proposed ZVS DC DC sep-up converer has fixed swiching frequency, simple conrol, and high efficiency. All power swiches can operae wih ZVS. The oupu diodes are under zero-curren-swiching (ZCS) during urn-off. Due o sof-swiching operaion of he power swiches and oupu diodes, he proposed ZVS DC DC converer shows high efficiency. Seady-sae analysis of he converer is presened o deermine he circui parameers. A laboraory prooype of he proposed converer is developed, and is experimenal resuls are presened for validaion. Keywords. DC DC converer; sof-swiching; high volage gain; zero-volage-swiching; zero-curren-swiching. 1. Inroducion Recenly, high-efficiency power conversion echniques have been researched due o he increasing emphasis on he environmen proecion and energy saving. Also, high efficiency is one of he mos imporan facors in sep-up DC DC converers used in applicaions such as elecric vehicles, uninerrupible power supplies, fuel cells, and phoovolaic sysems (Wai e al 2008; Wang & Nehrir 2008; Wai & Wang 2008; Prudene e al 2008;Ismaile al 2008). The sep-up DC DC converers can be classified ino wo ypes; volage-fed ype and currenfed ype. The curren-fed converers are ofen used in sep-up applicaions due o heir inheren low inpu curren ripple characerisic (Zhu e al 2003; Chae al 2008; Adib & Farzanehfard 2009). However, in he curren-fed converers, he volage sresses of he swiches are serious. In order o clamp he volages across he swiches and provide ZVS feaures, acive snubbers are ofen employed. However, since he snubbers cause addiional conducion losses, he sysem efficiency decreases. On he oher hand, he volage-fed converers shows low volage sress of For correspondence 653

2 654 Jae-Won Yang and Hyun-Lark Do C f1 S 1 D 1 S 3 D 3 V in T 1p N 1p C B1 N 2p T 2p T 2s N 2s T 1s N 1s C B2 D o1 C o R L V o C f2 S 2 D 2 S 4 D 4 D o2 Figure 1. Circui diagram of he proposed converer. he swiching devices, which is confined o he inpu volage. Among hem, phase-shif fullbridge converers are widely used. They feaure fixed swiching frequency and ZVS of power swiches. However, hey have some drawbacks such as large conducion loss due o circulaing curren, duy cycle loss, and he volage spikes across oupu recifiers. The large volage spikes of he oupu recifiers are serious problems especially in high volage applicaions. To remedy hese problems, many opologies have been proposed in (Jang & Jovanovic 2004; Borage e al 2008; Jang & Jovanovic 2007; Ordonez & Quaicoe 2011; Chene al 2008; Redle al 1991). In some of hem, auxiliary snubbering circuis are employed o suppress he volage spikes a he secondary side. However, he complexiy and he overall cos are raised and he sysem efficiency decreases due o he addiional circuis. In order o overcome hese problems, a high-efficiency ZVS sep-up DC DC converer shown in figure 1 is proposed. Asymmerical pulse widh modulaion (APWM) conrol echnique suggesed in (Imberson & Mohan 1993) is applied o he proposed converer o eliminae swiching losses and mainain low conducion loss. The proposed converer feaures fixed swiching frequency, sof-swiching operaions of all power swiches and oupu diodes, and clamped volage across power swiches and oupu diodes wihou any auxiliary circui. Moreover, he reverserecovery problem of he oupu diodes is significanly alleviaed due o he leakage inducance of he ransformers. Therefore, he proposed converer shows high efficiency and i is suiable o high volage applicaions. 2. Analysis of he proposed DC DC converer Figure 1 shows he circui diagram of he proposed high-efficiency ZVS sep-up DC DC converer. The proposed converer has wo spli inpu filer capaciors C f 1 and C f 2 and wo dcblocking capaciors C B1 and C B2. In order o obain a high volage gain, he oupu sage of he proposed converer has a volage doubler srucure which consiss of wo secondary windings N 1s and N 2s of wo ransformers, he capacior C B2, and he oupu diodes D o1 and D o2. APWM conrol echnique in (Imberson & Mohan 1993) is applied o he proposed converer o eliminae swiching losses and mainain low conducion loss. The equivalen circui of he proposed high-efficiency ZVS sep-up DC DC converer is shown in figure 2. The diodes D 1 hrough D 4 are he inrinsic body diodes of all swiches. The capaciors C 1 hrough C 4 represen heir parasiic oupu capaciances. The ransformer T 1 is modelled as he magneizing inducance L m1 and he ideal ransformer which has a urn raio of 1:n 1 (n 1 = N 1s /N 1p ). Is leakage inducance is included in he oal leakage inducance. Similarly, he ransformer T 2 is modelled as he magneizing inducance L m2 and he ideal ransformer which has a urn raio of 1:n 2 (n 2 = N 2s /N 2p ). To simplify he analysis, he volages across he capaciors are assumed o be

3 High-efficiency ZVS sep-up DC DC converer 655 i S1 i S3 C f1 V Cf1 V in Lm1 i V B1 m1 i m2 C f2 V Cf1 T 1p v m1 S 1 ip1 S 2 D1C 1 i p2 i S2 v S1 C B1 L m2 T 2p v m2 S 3 v S3 D3 C 3 i S4 v S2 S 4 v S4 D2C 2 D4C 4 L k vk T 2s T 1s i B2 sec Do1 D i C o1 V B2 D o2 i Do2 C o R L V o Figure 2. Equivalen circui of he proposed converer. consan under a seady sae. The heoreical waveforms of he proposed ZVS DC DC converer are shown in figure 3. The swich S 1 (S 4 ) and he swich S 2 (S 3 ) are operaed asymmerically and he duy raio D is based on he swich S 1 (S 4 ). The operaion of he proposed converer during a swiching period T s can be divided ino four modes and hey are shown in figure 4. Before 0, he swiches S 1 and S 4, and he oupu diode D o1 are conducing. A 0, he magneizing currens i m1 and i m2 and he oupu diode curren i Do1 arrive a heir maximum values I m1, I m2,andi Do1, respecively. Mode 1 [ 0, 1 ]: A 0, he swiches S 1 and S 4 are urned off a he same ime. Then, he energy sored in he magneic componens sars o charge/discharge he parasiic capaciances C 1 hrough C 4. Therefore, he volages v S1 and v S4 sar o rise from zero and he volage v S2 and v S3 sar o fall from he inpu volage V in. Since all he parasiic oupu capaciances C 1 hrough C 4 are very small, his ransiion ime inerval is very shor and i can be ignored. When he volages v S2 and v S3 arrive a zero, heir body diodes D 2 and D 3 are urned on. Then, he gae signals are applied o he swiches S 2 and S 3 a he same ime. Since he currens have already flown hrough D 2 and D 3 and he volages v S2 and v S3 are clamped as zero before he swiches S 2 and S 3 are urned on, zero-volage urn-on of S 2 and S 3 is achieved. Wih he urn-on of S 2, he volage v m1 across L m1 is V Cf2. Then, he curren i m1 decreases linearly from is maximum value I m1 as follows: i m1 () = I m1 V Cf2 L m1 ( 0 ). (1) The volage v m2 across L m2 is (V in V B1 ). Therefore, he curren i m2 decreases linearly from is maximum value I m2 as follows: i m2 () = I m2 V in V B1 ( 0 ) (2) L m2 Since he volage v k across is (n 1 V Cf2 + n 2 (V in V B1 ) + V o V B2 ), he curren i sec decreases from is maximum value I Do1 as follows: i sec () = I Do1 n 1V Cf2 + n 2 (V in V B1 ) + V o V B2 ( 0 ). (3) In his mode, he swich currens i S2 and i S3 can be wrien by i S2 () = i m1 () i m2 () (n 1 + n 2 ) i sec (), (4) i S3 () = i m2 () n 2 i sec (). (5)

4 656 Jae-Won Yang and Hyun-Lark Do v gs1 =v gs4 =v gs3 =v S4 =v S3 v gs2 v S1 v S2 v m1 i m1 v m2 i m2 v Lk i Lk i Do1 i Do2 i S1 i S2 i S3 i S Mode : d 1 T s d 2 T s DT s T s Figure 3. Theoreical waveforms. Mode 2 [ 1, 2 ]: A 1, he curren i Do1 decreases o zero and he diode D o1 is urned off. Then, he oupu diode D o2 is urned on and is curren increases linearly. Since he curren changing rae of D o1 is conrolled by he leakage inducance of he ransformers T 1 and T 2, is

5 High-efficiency ZVS sep-up DC DC converer 657 Figure 4. Operaing modes. reverse-recovery problem is alleviaed. Since he volage v k is (n 1 V Cf2 + n 2 (V in V B1 ) V B2 ) in his mode, he curren i sec are given by i sec () = n 1V Cf2 + n 2 (V in V B1 ) V B2 ( 1 ). (6) Since he volages v m1 and v m2 are no changed in his mode, he equaions of (1), (2), (4), and (5) are sill effecive. A he end of his mode, he currens i m1, i m2,andi sec arrive a heir minimum value I m1, I m2,and I Do2, respecively.

6 658 Jae-Won Yang and Hyun-Lark Do Mode 3 [ 2, 3 ]: A 2, he swiches S 2 and S 3 are urned off a he same ime. Similar o mode 1, he parasiic capaciors C 2 and C 3 sar o be charged from zero, whereas he parasiic capaciors C 1 and C 4 sar o be discharged from V in due o he energy sored in he magneic componens. Since all he parasiic capaciors C 1 hrough C 4 have very small values, his ransiion ime inerval is very shor and i can be ignored. Afer he parasiic capaciors are fully charged and discharged, he volages v S1 and v S4 become zero and he body diodes D 1 and D 4 are urned on. Then, he gae signals are applied o he swiches S 1 and S 4. Since he currens have already flown hrough D 1 and D 4 and he volages v S1 and v S4 are clamped as zero before he swiches S 1 and S 4 are urned on, zero-volage urn-on of S 1 and S 4 is achieved. Wih he urn-on of S 1, he volage v m1 across L m1 is V Cf1. Then, he curren i m1 increases linearly from is minimum value I m1 as follows: i m1 () = I m1 + V Cf1 ( 2 ). (7) L m1 The volage v m2 across L m2 is V in + V B1. Therefore, he curren i m2 increases linearly from is minimum value I m2 as follows: i m2 () = I m2 + V in + V B1 ( 2 ). (8) L m2 Since he volage v k across is n 1 V Cf1 + n 2 (V in + V B1 ) + V B2, he curren i sec increases from is minimum value I Do2 as follows: i sec () = I Do2 + n 1V Cf1 + n 2 (V in + V B1 ) + V B2 ( 2 ). (9) In his mode, he swich currens i S1 and i S4 can be wrien by i S1 () = i m1 () + i m2 () + (n 1 + n 2 ) i sec (), (10) i S4 () = i m2 () + n 2 i sec (). (11) Mode 4 [ 3, 4 ]: A 3, he curren i Do2 decreases o zero and he diode D o2 is urned off. Then, he oupu diode D o1 is urned on and is curren increases linearly. Since he curren changing rae of D o2 is conrolled by, is reverse-recovery problem is significanly alleviaed. Since he volage v k is n 1 V Cf1 + n 2 (V in + V B1 ) V o + V B2, he curren i sec is given by i sec () = n 1V Cf1 + n 2 (V in + V B1 ) V o + V B2 ( 3 ). (12) Since he volages v m1 and v m2 are no changed in his mode, he equaions of (7), (8), (10), and (11) are sill effecive. A he end of his mode, he currens i m1, i m2,andi Lk arrive a I m1, I m2, and I Do1, respecively. 3. Design parameers 3.1 Volages across he spli inpu filer capaciors C Cf1 and C Cf2 Since he average inducor volage mus be zero under a seady-sae condiion, he capacior volages V Cf1 and V Cf2 are equal o he average values of he swich volages v S1 and v S2,

7 High-efficiency ZVS sep-up DC DC converer 659 respecively. Therefore, hey are given by V Cf1 = (1 D) V in, (13) V Cf2 = DV in. (14) 3.2 Volage across he dc-blocking capacior C B1 Similarly, he volage V B1 across C B1 is equal o he difference beween he average values of he swich volages v S4 and v S2 as follows: V B1 = (1 2D) V in. (15) 3.3 Maximum values of he magneizing currens i m1 and i m2 From (1) and(14), he maximum magneizing curren I m1 is derived by I m1 = D (1 D) V int s. (16) 2L m1 From (2) and(15), he maximum magneizing curren I m2 is derived by I m2 = D (1 D) V int s L m2. (17) 3.4 Volage gain From (3) and(12), he maximum diode curren I Do1 is derived by I Do1 = n 1V Cf2 + n 2 (V in V B1 ) + V o V B2 d 1 T s = n 1V Cf1 + n 2 (V in + V B1 ) V o + V B2 (D d 2 ) T s. (18) From (13), (14), (15), and (18), he following relaion can be obained by V o V B2 = D (1 D) Dd 1 (1 D) d 2 (n 1 + 2n 2 ) V in. (19) D + d 1 d 2 Similarly, from (6) and(9), he maximum diode curren I Do2 can be wrien as follows: I Do2 = n 1V Cf2 + n 2 (V in V B1 ) V B2 (1 D d 1 ) T s = n 1V Cf1 + n 2 (V in + V B1 ) + V B2 d 2 T s. (20) From (13), (14), (15), and (20), V B2 can be obained by V B2 = D (1 D) Dd 1 (1 D) d 2 1 D d 1 + d 2 (n 1 + 2n 2 ) V in. (21)

8 660 Jae-Won Yang and Hyun-Lark Do Figure 5. Volage gain M wih k = From figure 3, he oupu curren I o can be represened by I o = (D + d 1 d 2 ) I Do1 2 From (18) hrough (22), d 1 and d 2 is obained by = (1 D d 1 + d 2 ) I Do2. (22) 2 d 1 = k (1 D), (23) d 2 = kd, (24) ( ) k = 1 8 I o 1 1. (25) 2 (n 1 + 2n 2 ) D (1 D) V in T s From (19)and(21), he volage gain M of he proposed converer is obained by M = V o (n 1 + 2n 2 )(1 2k) D (1 D) = V in (D (2D 1) k)(1 D + (2D 1) k). (26) Figure 5 shows he volage gain M according o D. 3.5 ZVS condiions for he swiches S 1 hrough S 4 Since he currens i m1, i m2,andi sec arrive a I m1, I m2,andi Do1 a he end of mode 4, he ZVS condiions for S 2 and S 3 are given by I m1 + I m2 + (n 1 + n 2 ) I Do1 > 0, (27) I m2 + n 2 I Do1 > 0. (28)

9 High-efficiency ZVS sep-up DC DC converer 661 Similarly, since he currens i m1, i m2,andi sec arrive a I m1, I m2,and I Do2,aheendof mode 2, he ZVS condiions for S 1 and S 4 are given by I m1 + I m2 + (n 1 + n 2 ) I Do2 > 0, (29) I m2 + n 2 I Do2 > 0. (30) Figure 6. Simulaion resuls.

10 662 Jae-Won Yang and Hyun-Lark Do Since n 1, n 2, I m1, I m2, I Do1,andI Do2 always have posiive values, i can be easily seen ha he ZVS of all swiches is achieved. For a proper ZVS operaion, deadimes of S 1 and S 2 (S 3 and S 4 ) also need o be considered. I is because he gae signal should be applied o he swich before he curren flowing hrough he ani-parallel diode changes is direcion. This condiion can deermine he leakage inducance. From (25), he leakage inducance can be deermined as follows: = (n 1 + 2n 2 ) V in D (1 D) T [ s 1 ( 1 2k ) ] 2, (31) 8I o where k = a predeermined value of k. 4. Experimenal resuls The performance of he proposed converer was verified on a 60 W prooype. The prooype was designed o operae from a 48 V inpu volage and provide 240 V oupu volage. Is operaing frequency was 75 khz. The required volage gain was 5. The value of k was seleced as According o (26), he urn raios n 1 and n 2 were seleced as 2 wih an assumpion ha he duy raio D was 0.3. The magneizing inducances L m1 and L m2 were seleced as 82 μh. The oal leakage inducance was 90 μh. The filer capaciors C f 1 and C f 2 and he dc-blocking capaciors C B1 and C B2 were chosen as 6.6 μf. Figure 6 shows p-spice simulaion resuls based on he specificaions and he circui parameers of he prooype. The key waveforms and he sof-swiching waveforms of he power swiches S 1 hrough S 4 and he oupu diodes D o1 and D o2 are shown in figure 6. The ZVS urn-on of he power swiches and he ZCS urn-off of he oupu diodes are achieved. Figure 7 shows he measured waveforms of he proposed highefficiency ZVS DC-DC converer wih a high volage gain a fixed swiching frequency 75 khz. Figure 7 shows he currens i p1, i p2, i sec, he oupu volage V o, and he swich volage v S2.Since he magneizing curren of T 2 is wo imes larger han ha of T 1, he peak value of he curren i p2 is larger han ha of i p1. I can be seen from figure 7 ha he experimenal waveforms agree wih he heoreical analysis and he simulaion resuls. The measured sof-swiching waveforms of all swiches and diodes are shown in figure 8. The ZVS operaions of he full-bridge swiches are shown in figure 8a. The volages across he swiches go o zero before he gae pulses are applied o he swiches. Since he swich volages are clamped as zero before he gae pulses are applied, he ZVS urn-on of he swiches is achieved. Figure 8b shows he ZCS of he oupu Figure 7. Measured key waveforms.

11 High-efficiency ZVS sep-up DC DC converer 663 (a) (b) Figure 8. D o2. Measured sof-swiching waveforms of all swiches and diodes: (a) S 1 hrough S 4,(b) D o1 and diodes. Afer he diode currens fall o zero, he volages across he diode rise o he oupu volage V o. Therefore, he ZCS urn-off of he oupu diodes is achieved. I can be seen ha he volages v Do1 and v Do2 are confined o V o wihou a clamping circui and a snubbering circui.

12 664 Jae-Won Yang and Hyun-Lark Do 100 Proposed Phase-shif full-bridge 96 Efficiency [%] Po [W] Figure 9. Measured efficiency. Figure 9 shows he measured efficiency of he proposed ZVS sep-up DC DC converer. The efficiency was measured wih WT230-Digial Power Meer from YOKOGAWA from 5 W o 60 W load. The proposed converer exhibis he efficiency of 96.1% a full load. Due o is sofswiching characerisic and alleviaed reverse-recovery problem, i shows a higher efficiency han he previous phase-shif full-bridge converer. 5. Concluding remarks The analysis, design, and experimenal resuls of a high-efficiency ZVS sep-up DC DC converer have been presened. The ZVS of all power swiches and ZCS of he oupu diodes are achieved. The proposed converer shows a higher efficiency han previous works. Also, wihou any auxiliary circuis, he volages across he swiches and he oupu diodes are confined o he inpu volage and he oupu volage, respecively. Therefore, he proposed sep-up DC DC converer is suiable for high volage applicaions. Experimenal resuls on a prooype are provided for validaion. Acknowledgemen This work was suppored by Basic Science Research Program hrough he Naional Research Foundaion of Korea (NRF) funded by he Minisry of Educaion, Science and Technology ( ). References Adib E and Farzanehfard H 2009 Zero-volage ransiion curren-fed full-bridge PWM converer. IEEE Trans. Power Elecron. 24: Borage M, Tiwari S, Bhardwaj S and Koaiah S 2008 A full-bridge DC DC converer wih zero-volageswiching over he enire conversion range. IEEE Trans. Power Elecron. 23:

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