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2 1 Radiation-Induced Multi-bit Upsets in SRAM-Based FPGAs Paul Graham, Heather Quinn, Jim Krone, and Michael Caffrey Los Alamos National Laboratory, Los Alamos, NM Sana Rezgui Xilinx Corporation, San Jose CA, Abstract This paper provides a methodology for estimating the proton static saturation cross-section for multi-bit upsets (MBUs) in Xilinx FPGAs and describes a methodology for determining MBUs effects on TMRprotected circuits. Experimental results are provided. to fail. This paper quantifies the occurrence of protoninduced MBUs in three generations of Xilinx FPGAs and estimates how likely these MBUs are to cause logic-level TMR techniques to fail. I. INTRODUCTION In recent years, field-programmable gate arrays (FP- GAs) with volatile programming memory, such as the Xilinx Virtex and Virtex-II families, have made inroads into space-based processing tasks [1]. SRAM-based FP- GAs offer many advantages in space-based computing. Custom hardware implementations of applications are often faster than traditional microprocessor implementations without the cost of manufacturing applicationspecific integrated circuits. Reprogrammability also allows designers to reconfigure the device with different application implementations or completely new applications while deployed, which should increase the usable lifetime of the entire system. Using commercial-off-theshelf (COTS) devices with available, mature design tools should reduce the cost of designing space-based systems. The main challenge of using FPGAs in the space environment is mitigating the effects of radiation-induced single-event upsets (SEUs) within these devices. These upsets could modify both the data being processed and the function and wiring of the digital circuits themselves. Several engineers and researchers [2] [5] have demonstrated that logic-level triple-modular redundancy (TMR) with scrubbing of the FPGA s programming (or configuration) data effectively mitigates the results of radiation-induced SEUs. Single-bit upsets are not the only concern, though. A possibility exists for multi-bit upsets (MBUs) caused by a single charged particle. MBUs have been seen in FPGAs [6] as well as other integrated circuits (ICs) with memory structures [7], [8]. Little is known about how well TMR mitigates MBUs effects, although it is suspected that in some cases MBUs may cause TMR II. METHODOLOGY To achieve our goals of understanding the frequency and effects of proton-induced MBUs, we must first identify the proton static saturation cross-sections for MBUs for each device. Once quantified, the frequency of the MBUs and resources they affect are analyzed to understand their potential effect on FPGA designs employing TMR. Further, we analyze the MBU phenomenon using three generations of Xilinx FPGAs to identify any MBU trends that may exist as newer CMOS process technologies continue to shrink transistor sizes. Table I describes several characteristics of the FPGAs that we tested. Though commercial-grade parts were used in our tests, the results should indicate how radiation-tolerant versions of these FPGAs should behave since they use the same fabrications masks. Note that the Virtex, Virtex- II, and Virtex-4 FPGA families use 220-nm, 150-nm, and 90-nm CMOS technologies, respectively. Though Virtex-4 uses a 90-nm process, Xilinx implemented the configuration memory using a 130-nm technology to improve its reliability with regards to terrestrial neutron effects. Family Part Config. CLBs Block IOB Bits RAM Pads (Kb) Virtex XCV1000 5,810,048 6, Virtex-II XC2V250 1,588, Virtex-II XC2V1000 3,744,768 1, Virtex-4 XC4VLX25 7,900,864 24,192 1, TABLE I XILINX PARTS TESTED

3 2 A. Cross-section Methodology Normally when static saturation cross-sections for FPGAs and other devices are determined, a part is irradiated and the number of upsets that occurred are counted, assuming that each upset was independent. As our results will show, this approach does not account for MBU events and, depending of the device tested, can lead to skewed results. To understand the frequency of MBUs due to proton radiation, we used the following test methodology. For our data collection procedure, we used a 63.3-MeV proton beam at UC-Davis s Crocker Nuclear Laboratory to irradiate the FPGAs. During irradiation, we would repeat a simple two-step cycle: we would completely reprogram the FPGA and then immediately read back the programming memory to identify and record any upsets. Since having a large proportion of bits upset per cycle would make it hard to distinguish true MBU events from false ones (i.e., when two or more proton events upset physically adjacent bits), we limited the flux such that each sample cycle observed relatively few upsets when compared with the size of the entire bitstream (less than 0.01% of the bitstream for each case). As an example, there were between one and ten upsets per readback for the Virtex 1000 FPGA experiments, resulting in a worsecase probability of about 6.2x10 6 for creating a false two-bit MBU. With the resulting data, the physical layout of the memory bits was used to determine the adjacency of upsets. For the most part, the local, logical arrangement of the FPGAs configuration data is related to the physical layout, but some exceptions had to be accounted for. Using physical layout information for the bits, we classify a bit as adjacent to another if it lies within one of the eight neighboring memory cells surrounding that bit. Figure 1 illustrates the adjacency neighborhood that we used. Additionally, we used a clustering algorithm that uniquely labels each cluster of bits such that each bit within the cluster is adjacent to at least one other bit within the cluster. In this way, we found the largest possible clusters of bits so we could understand the sizes of MBU events. Because our experimental methodology ensures the low probability of multiple particles causing these clusters, we assume that a single particle event is the most likely explanation for each cluster of upset bits. The location of each cluster is also recorded since the location is important for determining what FPGA resources are affected and frequency of MBUs by resource type. Fig. 1. Upset Adjacency Neighborhood B. TMR Effects Methodology Next, with the above information, we analyze the FPGA resources that are affected by the MBUs and reason whether or not each given MBU event might affect more than one domain within a TMR digital circuit and how often this might occur. Normally, with only single upset present in the configuration data, only one of the redundant circuit domains will be affected for fully redundant circuits. In the case of an MBU, there are potential cases where the affected bits cross TMR domains. For instance, if bits controlling the routing or logic from two different TMR domains are upset, TMR is defeated. We expect that not all MBU events will affect TMR. For example, if an MBU upset multiple bits within a single 4-input look-up table, only one TMR domain is affected and the MBU does not break the TMR scheme. Therefore, the frequency at which these critical MBUs occur may be quite small and design-dependent, resulting in a very low probability of TMR failure. III. RESULTS In this section we present the cross-section results from testing the Xilinx FPGAs. The data for the Virtex XCV1000 and Virtex-II XC2V250 has been fully analyzed. The data for the Virtex-II XC2V1000 and Virtex-4 XC4VLX25 parts has only been recently collected and is still being analyzed. Our preliminary analysis shows that the Virtex-II XC2V1000 and Virtex-4 results are consistent with the results from our Virtex-II XC2V250 experiments. The full paper on this research will provide a complete analysis for the other two parts, as well a breakdown of MBUs by resource type and a model for using these results to predict the number of MBUs in related FPGAs. Table II provides the frequencies for SEU events that cause four different sizes of upsets per event. With Virtex, only 96 MBU events were observed, all of which were two-bit events. With Virtex-II we observed a larger variety of events, including very infrequent fourbit events. Based on this collected data, MBUs are 27 times more common in Virtex-II than in the earlier

4 3 Virtex family. We note that the Virtex MBU data does not include any events that may have occurred in the Virtex BlockRAM content data while the data for all of the other FPGAs does include MBUs in this data. Since BlockRAM data accounts for less than 2.3% of the programming data bits within the Virtex XCV1000, this has only a small effect on the comparisons with other architectures. Table III illustrates the relative orientations of bits within the MBUs found. For Virtex, no MBUs were found within a column of configuration data, whereas with Virtex-II column adjacencies dominate the MBU bit orientations. These results reflect the geometrical properties of the Virtex-II layout, where adjacent bits within a single column of configuration data are closer physically than two bits that reside in adjacent columns. Device Adjacent Adjacent Diagonal Column Bits Row Bits Bits (% of Total) (% of Total) (% of Total) XCV (0.0%) (95.8%) (4.2%) XC2V (88.4%) (5.9%) (5.7%) XC2V1000 * (%) (%) (%) XC4VLX25 * (%) (%) (%) TABLE III FREQUENCY OF RELATIVE POSITIONS FOR UPSET EVENTS INDUCED BY PROTON RADIATION (63.3 MEV) FOR FOUR XILINX FPGAS IV. DISCUSSION In this section, we present a discussion of the results from Section III. First we present how to calculate cross-sections for single- and multi-bit upsets and then present the calculated cross-sections for the XCV1000 and XC2V250 parts. Next, we compare these results to SEFI cross-sections to show the relevance of single- and multi-bit upsets. We close this section with a discussion of how TMR is affected by MBUs. Since MBUs are more common for Virtex-II and later architectures, the usual equation for cross-section (σ = #of events/f luence) is skewed by MBU events. When using newer FPGA families, the cross-sections are more accurately determined as: σ device = σ 1 bit + σ 2 bit + σ 3 bit +... (1) = events 1 bit fluence + events 2 bit fluence +... (2) where the cross-sections of each event size (1-bit upsets, 2-bit upsets, etc.) are individually calculated. We used these formulas to calculate the cross-sections for singleand multi-bit upsets for the XC1000 and XC2V250 parts in Table IV. These results are within a factor of two with the published Xilinx results. In the full paper, we will extend these results to include cross-sections per resource type. Comparing the results of the previous section with the known SEFI cross-sections [9], [10], Table IV provides some interesting insight into the relevance of MBUs. These results show that, while still not as significant as SEUs, MBUs are more common than SEFIs the limiting factor to the effectiveness of TMR in Xilinx FPGAs and have the potential for affecting the performance of TMR schemes. Device σ 1 Bit σ MBU σ SEF I (cm 2 /device) (cm 2 /device) (cm 2 /device) XCV x x x10 13 (config SEFI) XC2V x x x10 13 XC2V1000 * 9.46x10 13 XC4VLX25 * Unknown TABLE IV COMPARISON OF THE SEU, MBU, AND SEFI SATURATION CROSS-SECTIONS FOR PROTONS (63.3 MEV) FOR FOUR XILINX FPGAS The full paper will provide the complete analysis of the effects of MBUs on TMR, but, we have seen one trend that suggests a way of avoiding these effects on TMR. During our analyses of Virtex and Virtex-II MBUs, we never saw an MBU that affected neighboring columns of similar or different resources (i.e., two adjacent CLB columns, an adjacent CLB and Block RAM interconnect column, etc.). This suggests that one approach to improving the reliability of TMR with respect to MBUs is to floorplan circuits such that no two TMR domains reside in the same resource column (i.e., only one TMR domain per CLB column, Block RAM column, etc.). This level of circuit design should be effective, though, it may not be necessary for many applications that do not require extreme levels of reliability. V. CONCLUSIONS AND FUTURE WORK In this paper we have presented a methodology for measuring the proton saturation cross-sections for MBUs in Xilinx FPGAs and described our proposed methodology for understanding the effects of MBUs on logiclevel TMR schemes used for FPGA applications. Current results for the Virtex-II 2V250 indicate that MBUs are on the rise in newer Xilinx FPGAs and are expected

5 4 Device Total 1-Bit 2-Bit 3-Bit 4-Bit Events Events Events Events Events (% of Total) (% of Total) (% of Total) (% of Total) XCV , , (99.96%) (0.04%) (0%) (0%) XC2V , , (98.76%) (1.22%) (0.01%) (0.0006%) XC2V1000 * (%) (%) (%) (%) XC4VLX25 * (%) (%) (%) (%) TABLE II FREQUENCY OF UPSET EVENTS INDUCED BY PROTON RADIATION (63.3 MEV) FOR FOUR XILINX FPGAS to be approximately 1% of the upsets induced by 63.3 MeV proton radiation. These results indicate that MBUs may be frequent enough to affect TMR reliability. The effectiveness of TMR in the presence of MBUs needs to be fully understood before commercially-based FPGAs can be used reliably in the space environment. The complete paper on this research will provide the MBU cross-sections for all three generations of Xilinx SRAM FPGAs. In the full paper, we will also suggest a method for predicting the MBU rates for related FPGAs through calculating the MBU frequency by resource type and appropriately scaling these frequencies for other devices based on the amount of resources each device has. The full paper will also analyze the potential of MBUs affecting the reliability of TMR-based FPGA designs and the frequency at which these effects may occur. [6] R. Koga, J. George, G. Swift, C. Yui, L. Edmonds, C. Carmichael, T. Langley, P. Murray, K. Lanes, and M. Napier, Comparison of Xilinx Virtex-II FPGA SEE sensitivities to protons and heavy ions, IEEE Transactions on Nuclear Science, vol. 51, no. 5, pp , October [7] G. M. Swift and S. M. Guertin, In-flight observations of multiple-bit upset in DRAMs, IEEE Transactions on Nuclear Science, vol. 47, no. 6, pp , December [8] R. Koga, K. B. Crawford, P. B. Grant, W. A. Kolasinski, D. L. Leung, T. J. Lie, D. C. Mayer, S. D. Pinkerton, and T. K. Tsubota, Single ion induced multiple-bit upset in IDT 256K SRAMs, in Proceedings of the Second European Conference on Radiation and its Effects on Components and Systems (RADECS), St. Malo, France, September 1993, pp [9] C. Carmichael, E. Fuller, J. Fabula, and F. D. Lima, Proton testing of SEU mitigation methods for the Virtex FPGA, in Proceedings of the IEEE Microelectronics Reliability and Qualification Workshop, Pasadena, CA, December [10] G. M. Swift, Virtex-II static SEU characterization, Xilinx Radiation Test Consortium, Tech. Rep. 1, REFERENCES [1] M. Caffrey, M. Echave, C. Fite, T. Nelson, A. Salazar, and S. Storms, A space-based reconfigurable radio, in Proceedings of the 5th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), September 2002, p. A2. [2] C. Carmichael, Triple module redundancy design techniques for Virtex FPGAs, Xilinx Corporation, Tech. Rep., November 1, 2001, xapp197 (v1.0). [3] F. Lima, C. Carmichael, J. Fabula, R. Padovani, and R. Reis, A fault injection analysis of Virtex FPGA TMR design methodology, in Proceedings of the 6th European Conference on Radiation and its Effects on Components and Systems (RADECS 2001), [4] N. Rollins, M. Wirthlin, M. Caffrey, and P. Graham, Evaluating TMR techniques in the presence of single event upsets, in Proceedings fo the 6th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD). Washington, D.C.: NASA Office of Logic Design, AIAA, September 2003, p. P63. [5] G. M. Swift, S. Rezgui, J. George, C. Carmichael, M. Napier, J. Maksymowicz, J. Moore, A. Lesea, R. Koga, and T. F. Wrobel, Dynamic testing of xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs), IEEE Transactions on Nuclear Science, vol. 51, no. 6, pp , December 2004.