ITTC Introduction to Digital Logic Design The University of Kansas EECS 140 / 141 Summary

Transcription

1 Introduction to Digital Logic Design The University o Kansas EECS 140 / 141 Summary James P.G. Sterbenz Department o Electrical Engineering & Computer Science Inormation Technology & Telecommunications Research Center The University o Kansas jpgs@eecs.ku.edu 21 October James P.G. Sterbenz

2 NOT Name (VHDL) Boolean lgebra Math. Logic + logic Set Theory Venn Diagram buer a a a a L L H H NOT inverter not a ~a a a a a L H H L complement 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-2

3 ND / NND Name (VHDL) Boolean lgebra Math. Logic + logic Set Theory Venn Diagram ND conjunction and a b ab a b a b a b L L L L H L H L L H H H B intersection B NND nand a b ab a b a b a b L L H L H H H L H ( B) B H H L 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-3

4 OR / NOR Name (VHDL) Boolean lgebra Math. Logic + logic Set Theory Venn Diagram OR disjunction or a + b a b a b a b L L L L H H H L H H H H B union B NOR nor a + b a b a b a b L L L L H L H L L ( B) B H H H 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-4

5 XOR / XNOR Name (VHDL) Boolean lgebra Math. Logic + logic Set Theory Venn Diagram XOR xor a b a b a b a b L L L L H H H L H H H L B B B XNOR equivalence xnor a b a b a b a b a b L L H L H L H L L B H H H 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-5

6 Tri-State Non-Inverting Buers Name Logic Function tri-state buer i e=1 then =x e x 0 0 Z 0 1 Z x e e 0 Z 1 x gate with drive (when enabled) tri-state buer (active low enable) i e=0 then =x e x Z 1 1 Z x e e 0 x 1 Z gate with drive (when enabled) 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-6

7 Tri-State Inverting Buers Name Logic Function tri-state inverting buer i e=1 then =x e x 0 0 Z 0 1 Z x e e 0 Z 1 x inverter with drive (when enabled) tri-state inverting buer (active low enable) i e=0 then =x e x Z 1 1 Z x e e 0 x 1 Z inverter with drive (when enabled) 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-7

8 Tri-State Balanced Output Buers Name Logic Function tri-state buer i e=1 then =x =x e x 0 0 ZZ 0 1 ZZ a e e 0 ZZ 1 xx inverter with drive (when enabled) tri-state buer (active low enable) i e=0 then =x =x e x ZZ 1 1 ZZ a e e 0 xx 1 ZZ inverter with drive (when enabled) 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-8

9 Transmission Name Logic Function transmission gate i s=1 ND s=0 then y=x s s x y 01 0 Z 01 1 Z x s s y s s y 01 Z 10 x bidirectional switch with no drive s and s inputs must be inverted with respect to one another 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-9

10 Multiplexor and Demultiplexor Name Logic Function 2:1 multiplexor y = x s y = sx 0 + sx 1 s x 1 x Block Diagram x 0 x 1 0 y 1 s s y 0 x 0 1 x 1 choose one o 2 inputs 1:2 demultiplexor y 0 = sx y 1 = sx s x y 1 y x 0 1 s y 0 y 1 s y 1 y x 1 x 0 steer to one o 2 outputs 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-10

11 Multiplexor 4:1 Name Logic Function Block Diagram 4:1 multiplexor = x s= s 1 s 0 x 0 + s 1 s 0 x 1 + s 1 s 0 x 2 + s 1 s 0 x 3 + x 0 x 1 00 x 01 2 x s 1 s 0 s 1 s 0 00 x 0 01 x 1 10 x 2 11 x 3 choose one o 4 inputs 1:4 demultiplexor steer to one o 4 outputs 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-11

12 Multiplexor 4:1 Name Logic Function Block Diagram (alternate) 4:1 multiplexor = x s= s 1 s 0 x 0 + s 1 s 0 x 1 + s 1 s 0 x 2 + s 1 s 0 x 3 + x s 2 s 1 s 0 00 x 0 01 x 1 10 x 2 11 x 3 choose one o 4 inputs 1:4 demultiplexor steer to one o 4 outputs 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-12

13 Multiplexor n :1 Name Logic Function Block Diagram n :1 multiplexor = x s x 0 n 1 n s 0 x 0 choose one o n inputs s log 2 n n 1 x n 1 n normally a power o 2 1:n demultiplexor steer to one o n outputs 21 October 2010 KU EECS 140/141 Digital Logic Summary DLD-LS-13