NGD8201N, NGD8201AN. Ignition IGBT. 20 A, 400 V, N Channel DPAK. 20 A, 400 V V CE(on) = 1.3 I C = 10 A, V GE 4.5 V

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1 NGD2N, NGD2AN Ignition IGBT 2 A, 4 V, N hannel DPAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Overvoltage clamped protection for use in inductive coil drivers applications. Primary uses include Ignition, Direct Fuel Injection, or wherever high voltage and high current switching is required. Features Ideal for oil on Plug and Driver on oil Applications DPAK Package Offers Smaller Footprint for Increased Board Space Gate Emitter ESD Protection Temperature ompensated Gate ollector Voltage lamp Limits Stress Applied to Load Integrated ESD Diode Protection Low Threshold Voltage for Interfacing Power Loads to Logic or Microprocessor Devices Low Saturation Voltage High Pulsed urrent apability These are Pb Free Devices Applications Ignition Systems MAXIMUM RATINGS (T J = 25 unless otherwise noted) Rating Symbol Value Unit ollector Emitter Voltage V ES 44 V ollector Gate Voltage V ER 44 V Gate Emitter Voltage V GE 5 V ollector urrent T = 25 Pulsed I 2 5 A D A A ontinuous Gate urrent I G. ma Transient Gate urrent (t 2 ms, f Hz) I G 2 ma ESD (harged Device Model) ESD 2. kv ESD (Human Body Model) R = 5, = pf ESD. kv ESD (Machine Model) R =, = 2 pf ESD 5 V Total Power T = 25 Derate above 25 P D 25.3 W W/ Operating & Storage Temperature Range T J, T stg 55 to +75 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability. G 2 A, 4 V V E(on) =.3 I = A, V GE 4.5 V R G DPAK ASE 369 STYLE 7 Device Package Shipping NGD2NT4G ORDERING INFORMATION DPAK (Pb Free) E MARKING DIAGRAM Y WW NGD2x x G G E NGD2ANT4G R GE YWW NGD 2xG = Year = Work Week = Device ode = N or A = Pb Free Package DPAK (Pb Free) 25 / Tape & Reel 25 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD/D. Semiconductor omponents Industries, LL, 23 March, 23 Rev. Publication Order Number: NGD2N/D

2 NGD2N, NGD2AN UNLAMPED OLLETOR TO EMITTER AVALANHE HARATERISTIS ( 55 T J 75 ) haracteristic Symbol Value Unit Single Pulse ollector to Emitter Avalanche Energy V = 5 V, V GE = 5. V, Pk I L = 6.7 A, R G =, L =. mh, Starting T J = 25 V = 5 V, V GE = 5. V, Pk I L = 4.9 A, R G =, L =. mh, Starting T J = 5 V = 5 V, V GE = 5. V, Pk I L = 4. A, R G =, L =. mh, Starting T J = 75 Reverse Avalanche Energy V = V, V GE = 2 V, Pk I L = 25. A, L = 6. mh, Starting T J = 25 E AS 25 2 E AS(R) 2 THERMAL HARATERISTIS Thermal Resistance, Junction to ase R J.2 /W Thermal Resistance, Junction to Ambient (Note ) R JA 95 /W Maximum Temperature for Soldering Purposes, / from case for 5 seconds (Note 2) T L 275. When surface mounted to an FR4 board using the minimum recommended pad size (76x76x.6mm board size, 6 sqmm oz. opper). 2. For further details, see Soldering and Mounting Techniques Reference Manual: SOLDERRM/D. mj mj ELETRIAL HARATERISTIS haracteristic Symbol Test onditions Temperature Min Typ Max Unit OFF HARATERISTIS ollector Emitter lamp Voltage BV ES I = 2. ma T J = 4 to V I = ma T J = 4 to Zero Gate Voltage ollector urrent I ES V GE = V, V E = 5 V T J = 25.. A Reverse ollector Emitter lamp Voltage Reverse ollector Emitter Leakage urrent B VES(R) I ES(R) V E = 2 V, V GE = V I = 75 ma V E = 24 V NGD2N V E = 24 V NGD2AN T J = A T J = * T J = T J = V T J = * T J = T J = ma T J = T J = T J = T J = T J = Gate Emitter lamp Voltage BV GES I G = 5. ma T J = 4 to V Gate Emitter Leakage urrent I GES V GE = 5. V T J = 4 to * A Gate Resistor R G T J = 4 to 75 7 Gate Emitter Resistor R GE T J = 4 to k ON HARATERISTIS (Note 3) Gate Threshold Voltage Threshold Temperature oefficient (Negative) V GE(th) *Maximum Value of haracteristic across Temperature Range. 3. Pulse Test: Pulse Width 3 S, Duty ycle 2%. I =. ma, V GE = V E T J = V T J = T J = * mv/ 2

3 NGD2N, NGD2AN ELETRIAL HARATERISTIS haracteristic Symbol Test onditions Temperature Min Typ Max Unit ON HARATERISTIS (Note 3) ollector to Emitter On Voltage V E(on) T J = V I = 6.5 A, V GE = 3.7 V NGD2N T J = T J = T J = I = 6.5 A, V GE = 3.7 V NGD2AN T J = T J = T J = I = 9. A, V GE = 3.9 V NGD2N T J = T J = T J = I = 9. A, V GE = 3.9 V NGD2AN T J = T J = T J = I = 7.5 A, V GE = 4.5 V T J = T J = * T J = I = A, V GE = 4.5 V T J = T J = * T J = I = 5 A, V GE = 4.5 V T J = T J = * T J = I = 2 A, V GE = 4.5 V NGD2N T J = T J = T J = I = 2 A, V GE = 4.5 V NGD2AN T J = T J = Forward Transconductance gfs I = 6. A, V E = 5. V T J = Mhos DYNAMI HARATERISTIS Input apacitance ISS 3 5 pf Output apacitance OSS f = khz, V E = 25 V T J = Transfer apacitance RSS 2 22 *Maximum Value of haracteristic across Temperature Range. 3. Pulse Test: Pulse Width 3 S, Duty ycle 2%. 3

4 NGD2N, NGD2AN ELETRIAL HARATERISTIS haracteristic Symbol Test onditions Temperature Min Typ Max Unit SWITHING HARATERISTIS Turn Off Delay Time (Resistive) t d(off) T J = Sec V = 3 V, I = 9. A T J = Fall Time (Resistive) t f R G =. k, R L = 33, V GE = 5. V T J = T J = Turn Off Delay Time (Inductive) t d(off) T J = V = 3 V, I = 9. A T J = Fall Time (Inductive) t f R G =. k, L = 3 H, V GE = 5. V T J = T J = Turn On Delay Time t d(on) T J = V = 4 V, I = 9. A T J = Rise Time t r R G =. k, R L =.5, V GE = 5. V T J = T J =

5 NGD2N, NGD2AN TYPIAL ELETRIAL HARATERISTIS 4 3 SIS ENERGY (mj) T J = 25 T J = 75 V = 4 V 5 V GE = 5. V R G = INDUTOR (mh) I A, AVALANHE URRENT (A) L =. mh L = 3. mh L = mh V = 4 V V GE = 5. V R G = 5 75 Figure. Self lamped Inductive Switching Figure 2. Open Secondary Avalanche urrent vs. Temperature V E, OLLETOR TO EMITTER VOLTAGE (V) V GE = 4.5 V I = 25 A I = 2 A I = 5 A I = A I = 7.5 A I, OLLETOR URRENT (A) V GE = V 5 V T J = V E, OLLETOR TO EMITTER VOLTAGE (V) 4.5 V 4 V 3.5 V 3 V 2.5 V Figure 3. ollector to Emitter Voltage vs. Junction Temperature Figure 4. ollector urrent vs. ollector to Emitter Voltage I, OLLETOR URRENT (A) V GE = V 5 V T J = V 4 V 3.5 V 3 V 2.5 V V E, OLLETOR TO EMITTER VOLTAGE (V) I, OLLETOR URRENT (A) V GE = V 5 V T J = V V E, OLLETOR TO EMITTER VOLTAGE (V) 4 V 3.5 V 3 V 2.5 V Figure 5. ollector urrent vs. ollector to Emitter Voltage Figure 6. ollector urrent vs. ollector to Emitter Voltage 5

6 NGD2N, NGD2AN TYPIAL ELETRIAL HARATERISTIS I, OLLETOR URRENT (A) V E = 5 V.5 T J = 25 T J = 75 T J = OLLETOR TO EMITTER LEAKAGE URRENT ( A).. 5 V E = 24 V V E = 2 V V GE, GATE TO EMITTER VOLTAGE (V) Figure 7. Transfer haracteristics Figure. ollector to Emitter Leakage urrent vs. Temperature GATE THRESHOLD VOLTAGE (V) Mean + 4 Mean 4 Mean , APAITANE (pf). iss oss rss V E, OLLETOR TO EMITTER VOLTAGE (V) Figure 9. Gate Threshold Voltage vs. Temperature Figure. apacitance vs. ollector to Emitter Voltage SWITHING TIME ( s) t fall t delay V = 3 V V GE = 5. V R G = I = 9. A R L = 33 SWITHING TIME ( s) V = 3 V V GE = 5. V R G = I = 9. A L = 3 H t delay t fall Figure. Resistive Switching Fall Time vs. Temperature Figure 2. Inductive Switching Fall Time vs. Temperature 6

7 NGD2N, NGD2AN R(t), TRANSIENT THERMAL RESISTANE ( /Watt) Duty ycle = D URVES APPLY FOR POWER P (pk) PULSE TRAIN SHOWN. t READ TIME AT t Single Pulse t 2 T J(pk) T A = P (pk) R JA (t) DUTY YLE, D = t /t 2 For D=: R J R(t) for t. s t,time (S) Figure 3. Minimum Pad Transient Thermal Resistance (Non normalized Junction to Ambient) R J(t), TRANSIENT THERMAL RESISTANE ( /Watt). Duty ycle = DUTY YLE, D = t Single Pulse /t t,time (S) P (pk) Figure 4. Best ase Transient Thermal Resistance (Non normalized Junction to ase Mounted on old Plate) t t 2 D URVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T J(pk) T A = P (pk) R J (t) 7

8 NGD2N, NGD2AN PAKAGE DIMENSIONS DPAK ASE 369 ISSUE D L3 L4 b2 e E b b A D B DETAIL A c.5 (.3) M A c2 H L2 GAUGE PLANE L L DETAIL A ROTATED 9 W A H Z SEATING PLANE NOTES:. DIMENSIONING AND TOLERANING PER ASME Y4.5M, ONTROLLING DIMENSION: INHES. 3. THERMAL PAD ONTOUR OPTIONAL WITHIN DI- MENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXEED.6 INHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTI BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. INHES MILLIMETERS DIM MIN MAX MIN MAX A A b b b c c D E e.9 BS 2.29 BS H L L. REF 2.74 REF L2.2 BS.5 BS L L4.4. Z SOLDERING FOOTPRINT* STYLE 7: PIN. GATE 2. OLLETOR 3. EMITTER 4. OLLETOR SALE 3: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SILL s product/patent coverage may be accessed at Marking.pdf. SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 27 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NGD2N/D