BUD43D. High Speed, High Gain Bipolar NPN Transistor with Antisaturation Network and Transient Voltage Suppression Capability
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1 BUDD High Speed, High Gain Bipolar NPN Transistor with Antisaturation Network and Transient Voltage Suppression Capability The BUDD is a state of the art bipolar transistor. Tight dynamic characteristics and lot to lot minimum spread make it ideally suitable for light ballast applications. Features Free Wheeling Diode Built In Flat DC Current Gain Fast Switching Times and Tight Distribution 6 Sigma Process Providing Tight and Reproducible Parameter Spreads Epoxy Meets UL 9 in These Devices are Pb Free and are RoHS Compliant Two Versions BUDD : Case 69D for Insertion Mode BUDD, BUDDT: Case 69C for Surface Mount Mode MAXIMUM RATINGS Rating Symbol Value Unit Collector Emitter Sustaining Voltage V CEO 5 Vdc Collector Base Breakdown Voltage V CBO 65 Vdc Collector Emitter Breakdown Voltage V CES 65 Vdc Emitter Base Voltage V EBO 9 Vdc Collector Current Continuous I C. Adc Collector Current Peak (Note ) I CM 8. Adc Base Current Continuous I B. Adc Base Current Peak (Note ) I BM. Adc Total Device T C = 5 C Derate above 5 C P D 5. Operating and Storage Temperature T J, T stg 65 to +5 W W/ C ESD Human Body Model HBM B V ESD Machine Model MM C V TYPICAL GAIN Typical I C = A, V CE = V Typical I C =. A, V CE = V h FE h FE 6 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Pulse Test: Pulse Width = 5. ms, Duty Cycle = % C AMPERES 65 VOLTS, 5 WATTS POWER TRANSISTOR DPAK CASE 69C STYLE DPAK CASE 69D STYLE A Y WW BUDD G MARKING DIAGRAMS Collector Collector Base Emmitter Base AYWW BU DDG Collector AYWW BU DDG Collector Emmitter = Assembly Location = Year = Work Week = Device Code = Pb Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, August, Rev. 6 Publication Order Number: BUDD/D
2 BUDD THERMAL CHARACTERISTICS Characteristic Symbol Value Unit Thermal Resistance, Junction to Case R JC 5. C/W Thermal Resistance, Junction to Ambient R JA 7. C/W Maximum Lead Temperature for Soldering Purposes: /8 in from Case for 5 seconds T L 6 C ELECTRICAL CHARACTERISTICS (T C = 5 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Collector Emitter Sustaining Voltage V (I C = ma, L = 5 mh) ÎÎÎÎ CEO(sus) ÎÎÎ 5 ÎÎÎÎ ÎÎÎ ÎÎÎ Vdc Collector Base Breakdown Voltage ÎÎÎÎ V CBO ÎÎÎÎ (I CBO = ma) 65 ÎÎÎÎ 78 ÎÎÎ ÎÎÎ Vdc Emitter Base Breakdown Voltage ÎÎÎÎ V EBO ÎÎÎ (I EBO = ma) 9. ÎÎÎ Vdc Collector Cutoff T ÎÎÎÎÎ (V CE = Rated V CEO, I B = ) ÎÎÎÎÎ C = T C = 5 CÎÎÎÎ CEO ÎÎÎ ÎÎÎ ÎÎÎ Adc ÎÎÎÎÎ Collector Cutoff Current T C = 5 C ÎÎÎÎ I CES ÎÎÎ ÎÎÎÎÎ (V CE = Rated V CES, V EB = ) T C = 5 C ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Adc Emitter Cutoff Current ÎÎÎÎ I EBO ÎÎÎÎ Adc (V EB = 9 Vdc, I C = ) ON CHARACTERISTICS ÎÎÎÎÎ Base Emitter Saturation Voltage V (I C = Adc, I B =. Adc) ÎÎÎÎ BE(sat) ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ.85. ÎÎÎ Vdc Collector Emitter Saturation Voltage ÎÎÎÎ V CE(sat) ÎÎÎ ÎÎÎÎ. ÎÎÎ. ÎÎÎ Vdc (I C = Adc, I B =.5 Adc) DC Current Gain h (I C = Adc, V CE ÎÎÎÎ FE ÎÎÎÎ = Vdc) (I C = Adc, V CE = 5 Vdc) 8. ÎÎÎÎ ÎÎÎ ÎÎÎ DIODE CHARACTERISTICS Forward Diode Voltage ÎÎÎÎ V EC ÎÎÎ (I EC =. Adc) ÎÎÎÎ ÎÎÎ ÎÎÎ V.9.5 SWITCHING CHARACTERISTICS: Resistive Load (D.C. %, Pulse Width = s) ÎÎÎ Turn Off Time T off ÎÎÎÎ (I C =. Adc, I B =. A, I B =. A, V CC = V).6ÎÎÎÎ ÎÎÎ 6.55ÎÎÎ s Fall Time ÎÎÎÎ T f ÎÎÎÎ (I C =.5 Adc, I B = I B =.5 A, V CC = 5 V, V BE = V).8 ÎÎÎ s DYNAMIC SATURATION VOLTAGE s I ÎÎ Dynamic Saturation Î C = T C = 5 C ÎÎÎÎ T C = 5 C CE(dsat)ÎÎÎ ÎÎÎÎ.8 ÎÎÎ ÎÎÎ V. I B = ma ÎÎ ÎÎ Voltage: V Î CC = T ÎÎ C = 5 T ÎÎÎÎ Determined s and C = 5 C ÎÎÎ.75. ÎÎÎ ÎÎÎ ÎÎ s respectively T C = 5 C ÎÎÎ ÎÎ rising I B reaches Î I C = A T C = 5 C. ÎÎÎ ÎÎÎÎ.7 ÎÎÎ ÎÎÎ 9% of final I ÎÎ B I Î B = ma V CC = V T C = 5 C ÎÎÎÎ.5 ÎÎÎ T C = 5 C.6
3 BUDD TYPICAL STATIC CHARACTERISTICS hfe, DC CURRENT GAIN T J = 5 C T J = 5 C T J = - C hfe, DC CURRENT GAIN T J = 5 C T J = 5 C T J = - C Figure. DC Current V CE = V Figure. DC Current V CE = 5 V T J = 5 C I C /I B = 5 VCE, VOLTAGE (VOLTS) I C =. A A. A A.5 A VCE, VOLTAGE (VOLTS). T J = 5 C T J = - C T J = 5 C... I B, BASE CURRENT (AMPS).... Figure. Collector Saturation Region Figure. Collector Emitter Saturation Voltage I C /I B = 8 I C /I B = T J = - C VCE, VOLTAGE (VOLTS). T J = - C T J = 5 C T J = 5 C VCE, VOLTAGE (VOLTS). T J = 5 C T J = 5 C Figure 5. Collector Emitter Saturation Voltage Figure 6. Collector Emitter Saturation Voltage
4 BUDD TYPICAL STATIC CHARACTERISTICS I C /I B = 5 I C /I B = 8 VBE, VOLTAGE (VOLTS) T J = - C T J = 5 C T J = 5 C VBE, VOLTAGE (VOLTS) T J = - C T J = 5 C T J = 5 C Figure 7. Base Emitter Saturation Region Figure 8. Base Emitter Saturation Region VBE, VOLTAGE (VOLTS) I C /I B = T J = - C T J = 5 C T J = 5 C FORWARD DIODE VOLTAGE (VOLTS) V EC(V) = - C V EC(V) = 5 C V EC(V) = 5 C REVERSE EMITTER-COLLECTOR CURRENT Figure 9. Base Emitter Saturation Region Figure. Forward Diode Voltage
5 BUDD TYPICAL SWITCHING CHARACTERISTICS 9 C ib T J = 5 C f (test) = MHz 8 C, CAPACITANCE (pf) C ob (VOLTS) VCER B I CER = ma l C = 5 mh I CER = ma T C = 5 C V R, REVERSE VOLTAGE (VOLTS) R BE ( ) Figure. Capacitance Figure. B VCER = f(r BE ) 8 9 t, TIME (ns) h FE = 5 h FE = V CC = V P W = s t, TIME (ns) 6 V CC = V P W = s h FE = 5 T J = 5 C T J = 5 C.5.5 T J = 5 C T J = 5 C.5 h FE =.5 Figure. Resistive Switching, t on Figure. Resistive Switching, t off V CE = 5 V V Z = V L C = H T J = 5 C T J = 5 C V CE = 5 V V Z = V L C = H t, TIME ( μ s) T J = 5 C t, TIME ( μ s) T J = 5 C Figure 5. Inductive Storage Time, t h FE = 5 Figure 6. Inductive Storage Time, t h FE = 5
6 t BUDD TYPICAL SWITCHING CHARACTERISTICS 5 V CC = 5 V V Z = V L C = H T J = 5 C T J = 5 C T J = 5 C t, TIME (ns) t c t, TIME (ns) T J = 5 C t fi 5 V CE = 5 V V Z = V L C = H Figure 7. Inductive Fall and Cross Over Time, t fi and t h FE = 5 Figure 8. Inductive Fall Time, t h FE = 5 5 t, TIME (ns) V CC = 5 V V Z = V L C = H T J = 5 C t, TIME ( s) V CC = 5 V V Z = V L C = H I C = A T J = 5 C T J = 5 C T J = 5 C I C =. A h FE, FORCED GAIN Figure 9. Inductive Cross Over Time, t h FE = Figure. Inductive Storage Time, t si, FALL TIME (ns) fi V CC = 5 V V Z = V L C = H I C = A I C =. A T J = 5 C T J = 5 C CROSS-OVER TIME (ns) I C = A T J = 5 C T J = 5 C 6 I C =. A 8 V CC = 5 V V Z = V L C = H h FE, FORCED GAIN h FE, FORCED GAIN Figure. Inductive Fall Time, t f Figure. Inductive Cross Over Time, t c 6
7 t BUDD TYPICAL SWITCHING CHARACTERISTICS t, TIME ( s).5.5 V CC = 5 V V Z = V L C = H I B & = ma 5 ma ma 5 ma fr, FORWARD RECOVERY TIME (ns) 8 6 di/dt = A/ s, T C = 5 C I F, FORWARD CURRENT (AMPS) Figure. Inductive Storage Time, t si Figure. Forward Recovery Time, t fr V CE Dyn s 8 I C t si 9% I C t fi Dyn s 6 % V clamp % I C V I B 9% I B s s V clamp I B 9% I B t c TIME TIME 6 8 Figure 5. Dynamic Saturation Voltage Measurements Figure 6. Inductive Switching Measurements 7
8 I BUDD TYPICAL SWITCHING CHARACTERISTICS Table. Inductive Load Switching Drive Circuit +5 V F 5 W W MTP8P F V CE PEAK I C PEAK + V MPF9 MPF9 MUR5 MTP8P R B A I out V CE I B I B COMMON -V off 5 5 F 5 W MJE MTPN R B F V (BR)CEO(sus) L = mh R B = V CC = Volts I C(pk) = ma I B Inductive Switching L = H R B = V CC = 5 Volts R B selected for desired I B RBSOA L = 5 H R B = V CC = 5 Volts R B selected for desired I B V FRM V FR (. V F ) UNLESS OTHERWISE SPECIFIED F V F. V F t fr % I F Figure 7. t fr Measurement 8
9 I BUDD MAXIMUM RATINGS C, COLLECTOR CURRENT (AMPS). dc 5 ms ms s s EXTENDED SOA 5 V BE(off) = -5 V T J = 5 C GAIN L C = 5 H. V BE = V V BE(off) = -.5 V V CE, COLLECTOR-EMITTER VOLTAGE (VOLTS) V CE, COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 8. Forward Bias Safe Operating Area Figure 9. Reverse Bias Safe Operating Area POWER DERATING FACTOR SECOND BREAKDOWN DERATING THERMAL DERATING T C, CASE TEMPERATURE ( C) Figure. Power Derating There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate I C V CE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 8 is based on T C = 5 C; T j(pk) is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to % but must be derated when T C > 5 C. Second Breakdown limitations do not derate like thermal limitations. Allowable current at the voltages shown on Figure 8 may be found at any case temperature by using the appropriate curve on Figure. T j(pk) may be calculated from the data in Figure. At any case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. For inductive loads, high voltage and current must be sustained simultaneously during turn off with the base to emitter junction reverse biased. The safe level is specified as reverse biased safe operating area (Figure 9). This rating is verified under clamped conditions so that the device is never subjected to an avalanche mode. 9
10 BUDD D =.5 r(t) TRANSIENT THERMAL RESISTANCE (NORMALIZED) SINGLE PULSE P (pk) t t DUTY CYCLE, D = t /t R JC (t) = r(t) R JC R JC = 5 C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T J(pk) - T C = P (pk) R JC (t)... t, TIME (ms) Figure. Thermal Response ORDERING INFORMATION BUDD G BUDDTG Device Package Shipping DPAK Straight Lead (Pb Free) DPAK (Pb Free) 75 Units / Rail 5 Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D.
11 BUDD PACKAGE DIMENSIONS L L b e E b b A D B DETAIL A c.5 (.) M C A C c H L GAUGE PLANE 6.. DPAK CASE 69C ISSUE D L L DETAIL A ROTATED 9 CW SOLDERING FOOTPRINT*.58. A H..8 C Z SEATING PLANE NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.5M, 99.. CONTROLLING DIMENSION: INCHES.. THERMAL PAD CONTOUR OPTIONAL WITHIN DI- MENSIONS b, L and Z.. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED.6 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. INCHES MILLIMETERS DIM MIN MAX MIN MAX A A..5.. b b b c c D E e.9 BSC.9 BSC H L L.8 REF.7 REF L. BSC.5 BSC L L.. Z.55.9 STYLE : PIN. BASE. COLLECTOR. EMITTER. COLLECTOR SCALE : mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
12 BUDD PACKAGE DIMENSIONS IPAK CASE 69D ISSUE C V B R C E NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 98.. CONTROLLING DIMENSION: INCH. S T SEATING PLANE F G A K D PL J. (.5) M T H Z INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D E F G.9 BSC.9 BSC H J K R S V Z.55.9 STYLE : PIN. BASE. COLLECTOR. EMITTER. COLLECTOR ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 56, Denver, Colorado 87 USA Phone: or 8 86 Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 79 9 Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative BUDD/D
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