CMOS Digital Integrated Circuits Analysis and Design. Chapter 6 MOS Inverters: Switching Characteristics and Interconnect Effects

Transcription

1 MOS Digial Iegraed ircuis Aalysis ad Desig haer 6 MOS Iverers: Swichig haracerisics ad Iercoec Effecs

2 Iroducio he arasiic caaciace associaed wih MOSFE gd gs gae overla wih diffusio db sb volage deeda jucio caaciace g he hi-oxide caaciace over he gae area i he limed iercoec caaciace Load caaciace gd gd db db i g sb ad sb have o effec o he rasie behavior of he circui sice SB 0 he delay imes calculaed usig may slighly overesimae he acual iverer delay hargig dischargig

3 3 Delay-ime defiiios ( D rise A B fall OL OL OL OL PLH PHL P PLH PHL OL OL OL 0.9 ( 0. ( / ( / 90% 0% %

4 alculaio of delay ime he simles aroach for calculaig he roagaio delay imes PHL ad PLH Esimaig he average caaciace curre durig charge dow ad charge u I I PHL PLH avg avg Iavg HL Iavg LH HL [ i( LH [ i( HL LH i i OL ( I ( I avg HL avg LH i i No very accurae esimae of he delay ime 50% 50% 50% OL ( i ( i OL 50% OL ] 4

5 alculaio of delay ime( he roagaio delay imes ca be foud more accuraely by solvig he sae equaio of he u ode i he ime domai d d Firs we he MOS o sarig o discharge MOS off i i D D ' 0 0 k d ' k id d cosider he ( ( ( ' A he u vol age is ( a he sauraio - liear regio boudary. osideri g MOS liear PHL PHL 0 i i k k [ ( ] ( i k k( k( k( i d d ( D i i ( l( [ [ resig - iu case for a MOS iverer k d id D D 50% ( d id l( ( - [ ] 50% 4( l( 4( l( for k ad he rasiso r will be 50% < ( - OL ] for d 50% ( k[( 5 d ] ou

6 Examle 6. 6

7 Examle 6. 7

8 8 alculaio of delay ime ( ( ( [ ] 50% 50% 50% 50% ( ( ( ( ( l ( ( ( for ( ( for ( above rises is age u vol whe he liear eer ad i sauraio iiially MOS he oe ( o chargig MOS off MOS low from high o swiches age iu vol Whe he for i.e. delays roagaio for balaced codiios sufficie he 4( l ( ( l ( iu for risig eve dow - charge he o aalogous comleely is siio iu ra for fallig e caaciac u he of eve u - charge he iverer MOS I a > f PLH PLH r PHL PHL OL PLH D OL D PLH D D D PLH PHL P PLH OL OL P OL PLH seiu acual seiu acual k liear i d sa i d k i - k i i d d /µ µ /W or W k ad k k k

9 alculaio of delay ime (3 osiderig he iu volage waveform is o a ideal (se ulse waveform bu has fiie rise ad fall imes Usig a emirical exressio as he former exressio based o he gradual chael aroximaio a sill be used for sub-micro MOS rasisors wih roer arameer adjusmes Ye he curre drivig caabiliy of sub-micro rasisors is sigificaly reduced as a resul of chael velociy sauraio (W/L-raio I dee-sub-micro MOS sauraio curre o loger ( GS - I sa κw ( GS - PHL ( 50% /I sa [ ( /]/ κw ( GS - he roagaio delay has oly a weak deedece od he ower suly Beer esimae ca be obai by usig a accurae shorchael MOSFE model 9

10 Iverer desig wih delay cosrais he caaciace cosis of Irisic comoes arasiic drai caaciaces which deed o rasisor dimesios Exrisic comoe iercoec/wirig caaciace ad fa- caaciace If maily cosiss of exrisic comoes ad if his overall caaciace ca be esimaed accuraely ad ideedely of he rasisor dimesios Give a required (arge delay value of * PHL he (W/L-raio ca be foud as W 4( L W L µ ( l PHL ox µ ( 4( l PLH ox 0

11 Examle 6.3

12 If Iverer desig wih delay cosrais have o ake io accu ha he irisic comoe he fa - caacoace oderig he simlified lay i Fig. 6.8 he relaively small gae - he drai arasiic caaciace are : db db gd ( W ( W j0 he oal caaciive ca be exressed as : WDdrai WDdrai where α 0 D α K α K K α 0 αw eq eq j0 j0 eq drai ( ( ( gd K K eq j0 eq αw j0 ( W jsw g o - drai caaciaces ( W is also a fucio of he device dimesios i he ex - sage gaes ( W Wj0 D D K drai eq drai K eq db D D ( W D jsw jsw drai jsw drai drai K ( W eq db jsw K jsw ( W eq K eq i gd D drai g i ad g gd jsw K f ( W W will be egleced i he aalysis eq ( W D drai jsw K eq i g

13 Iverer desig wih delay cosrais he roagaio delay : α 0 αw α 0 αw αw L 4( PLH l ( W µ ox Noe ha he chael leghs L ad L are usually fixed ad equal o each oher he rasiso r PHL PHL where Γ α 0 ( α Γ Γ W µ µ L ( Give arg e delay value ox ox ( α α αw asec ra io α W W L ( µ ad L ( P 4( l limi limi α PHL Γ PLH Γ α he roagaio delay ca o be reduced beyod hese limi valu es which are dicaed he roagaio delay ime is ideede of he exrisic caaciac e comoe saisfy h ese delay cosrai s ca be calculaed from (6.46a ad (6.46b by solvig for W 4( l W be defied as : (asec r aio W * PHL PLH ox α α 0 ( α W Γ W * PLH 4( l P Icreasig W ad W o reduce he roagaio delay ime s will have a dimishig ifluece uo delay beyod cerai va lues he miimum chael widhs of he MOS rasiso r ad he MOS rasiso r which i by echol ogy - relaed ad ad W g resecive ly. arameers. 3

14 Examle 6.4 4

15 Examle 6.4 5

16 MOS rig oscillaor circui his circui does o have a sable oeraig oi he oly D oeraig oi: he iu ad u volages of all iverers are equal o he logic hreshold h (usable A closed-loo cascade coecio of ay odd umber of iverer will dislay asable behavior will oscillae oce ay of he iverer iu or u volages deviae from he usable oeraig oi h OL rigger o fall OL differece bewee he 50% - crossig imes of ad PHL rigger 3 o rise OL differece bewee he 50% -crossig imes of ad 3 PHL3... PHL PHL PHL PHL PHL3 PHL3 6 P f//( P P /f 6

17 Esimaio of iercoec arasiics he lassical aroach caaciive ad lumed Ieral arasiic caaciace of he rasisor Iercoec (lie caaciaces Iu caaciaces of he fa gaes Now he iercoec lie iself hree dimesioal srucure i meal ad/or olysilico No-egligible resisace he (legh/widh raio of he wire disribued makig he iercoec a rue rasmissio lie A iercoec is rarely isolaed from oher ifluece 7

18 Esimaio of iercoec arasiics If he ime of fligh across he iercoecio lie is much shorer ha he sigal rise/fall imes he wire ca be modeled as a caaciive or as a lumed or disribued ework If he iercoecio lies are sufficie log ad he rise imes of he sigal comarable o he iducace becomes imora Modeled as rasmissio lies l rise( fall <.5 { rasmissio lie modelig} v l l eiher rasmissio - lie.5 < rise( fall < 5 v v or lumed modelig l rise( fall > 5 { lumed modelig} v Here l is he iercoec lie legh ad v is he roagaio seed he loges wire o a LSI chi (cm frigh ime 33s shorer ha rise/fall ime caaciive or model 0 cm muli-chi module s he same order as rise/fall ime cosiderig LG 8

19 he rasmissio lie effec IN MOS LSI chis No serious cocer he gae delay due o caaciive comoe domiaed he lie delay he sub-micro desig rules he irisic gae delay ed o decrease sigificaly he overall chi size ad he worse-case lie legh o a chi ed o icrease Maily due o icreasig chi comlexiy he widhs of meal lies shrik while hickess icrease he rasmissio lie effecs ad sigal coulig bewee eighborig lies become eve more roouced o oimize a sysem for seed chi desiger mus have reliable ad efficie meas for Esimaig he iercoec arasiics i a large chi Simulaig he rasie effec 9

20 Iercoecio delay he hierarchical srucure of mos LSI desig hi Modules Ier-module coecio loger Logic gaes rasisors Ira-module coecio shorer 0

21 Iercoec caaciace esimaio A comlicaed ask Frigig-field facor FF oal /

22 Esimaio of iercoecio caaciace he formulas rovide accurae aroximaio of he arasiic caaciace values o wihi 0% error eve for very small values of (w/h ad (/h he liear dash-doed lie arallel-lae ca. W/ decreases ca. Decreases Level off a aroximaely F/cm whe he wire widh is aroximaely equal o isulaor hickess w.47 l w l < for h h h h h w for h h h h w π ε π ε

23 aaciace coulig osiderig he iercoecio lie is o comleely isolaed from he surroudig srucures bu is couled wih oher lies ruig i arallel he oal arasiic caaciace icreased by Frigig-field effecs aaciive coulig bewee he lies Whe he hickess of he wire is comarable o is widh coulig caaciace Sigal crossalk» rasiios i oe lie ca cause oise i he oher lies 3

24 aaciace of a iercoec lie he caaciace of a lie which is couled wih wo oher lies o boh sides If boh of he eighborig lies are biased a groud oeial he oal arasiic caaciace ca be more ha 0 imes as large as he simle arallel-lae caaciace 4

25 aaciace bewee various layers 5

26 Iercoec resisace esimaio he oal resisace wire shee shee l l ρ shee w w : he shee resisiviy of ρ he lie ( Ω/square he shee resisiviy Polysilico: 0-40 Ω/square Silicided loysilico: -4 Ω/square Alumium: 0. Ω/square Meal-oly meal-diffusio coac: 0-30 Ω ia resisace: 0.3 Ω We ca esimae he oal arasisic resisace of a wire segme based o is geomery Shor disace egligible Log disace he oal lumed resisace coec i series wih he oal lumed caaciace 6

27 alculaio of iercoec delay- delay models If he ime of fligh across he iercoec lie is sigifica shorer ha he sigal rise/fall imes a be modeled as a lumed ework Assumig ha he caaciace is discharged iiially ad assumig ha he iu sigal is a risig se ulse a ime 0 ( ex he risig u volage reaches he 50% - oi a PLH 50% ( ex ad he roagaio delay for he simle lumed ework is foud as PLH 0.69 PLH Uforuaely his simle lumed ework rovides a very rough aroximaio he accuracy of he simle lumed model ca be sigifica imroved by Dividig he oal resisace io wo equal ars More accuracy ladder ework 7

28 alculaio of iercoec delay- he Elmore delay osider a geeral ree ework here are o resisor loos i his circui All of he caaciors i a ree are coeced bewee a ode ad a groud here is oe iu ode i he circui here is a uique resisive ah from he iu ode o ay oher ode i he circui Pah defiiios Le P i deoe he uique ah from he iu ode o ode i i3.. Le P ij P i P j deoe he orio of he ah bewee he iu ad he ode i which is commo o he ah bewee he iu ad ode j 8

29 9 alculaio of iercoec delay- he Elmore delay ( ( ( ( ( ( ( ( lumed ework a of ha ha disribued lie is cosiderable a we see ha he roagaio delay of hus for ad eleme ideical cosisig of uiform ladder ework assume a If simle ladder ework ree ework he geeral A secific case of smaller N N N N N N N N N (/N (/N DN j k N j DN j k k N j j DN D D

30 Examle 5 30

31 Examle 5 3

32 3 Swichig ower dissiaio of MOS iverers ( f P P P d d d d d d P d i v P avg avg avg avg avg ( (

33 Power meer simulaio Power meer Esimaig he average ower dissiaio of a arbirary device or circui drive by a eriodic iu wih rasie circui simulaio osisig A liear-corolled curre source A caacior A resisor d y y d y β i β ( ex i ( y Assumig y s he iiial codiio of 0 y y y yy >> he ode volage y d β ( i ( ( ( y 0 y is ae as ( 0 0 d y y If β he y i d 0 he righ-had side of (6.75 corresods o he average ower draw from he ower suly source over oe eriod he value of he ode volage y a gives he average ower dissiaio 33

34 Examle 6 34

35 Power-delay roduc For measurig he qualiy ad he erformace of a MOS rocess ad gae desig he average eergy required for a gae o swich is u volage from low o high ad from high o low PDP (6.76 Dissiaed as hea durig swichig o kee ad as low as ossible PDPP* avg (6.77 P* avg is he average swichig ower dissiaio a maximum oeraig frequecy is he average roagaio delay he facor of accouig wo rasiios of he u from low o high ad from high o low his resul may misleadig ierreaio ha he amou of eergy required er swichig eve is a fucio of he oeraig frequecy PDP ( f max PHL PLH PHL PLH 35

36 Suer buffer desig ( Suer buffer A chai of iverers desiged o drive a large caaciive wih miimal sigal roagaio delay ime A major objecive of suer buffer desig Give he caaciace faced by a logic gae desig a scaled chai of N iverers such ha he delay ime bewee he logic gae ad he caaciace ode is miimized he desig ask is o deermie he umber of sages N he oimal scale facor α 36

37 37 Suer buffer desig ( For he suer buffer g : he iu caaciace of he firs sage iverer d : he chai caaciace of he firs sage iverer he iverers i he chai are scaled u by a facor of α er sage α N g All iverers have ideical delay of 0 ( d α g /( d g 0 : he er gae delay i he rig oscillaor circui wih caaciace ( d g ( ( ( ( However i realiy he drai arasiics cao be igored 78 umber scale facor becomes he aural he oimal I ha case 0. egleced; i.e. whe he drai caaciace is he above equaio occurs case of A secial l scale facor he oimal 0 l l l l l l l e N From N d g d g d g g d g d g oal oal g d g d g oal g g N g d g d oal α α α α α α α α α α α α &