Systematic and Optimal Design of CMOS Two-Stage Opamps with Hybrid Cascode Compensation

Transcription

1 Sysemic d Opiml Desig of MOS Two-Sge Opmps wih Hybrid scode ompesio Mohmmd Yvri, Omid Shoei, d Agel Rodriguez-Vzquez* I Desig borory, EE Deprme, Uiversiy of Tehr, Tehr , Ir * Isiue of Microelecroics of Seville (IMSE-NM, 411 Seville, Spi Absrc This pper preses sysemic d opiml desig of hybrid cscode compesio mehod which is used i fully differeil wo-sge MOS operiol rscoducce mplifiers (OTAs. The closed loop lysis resuls re give o obi desig procedure. A simple desig procedure for he miimum selig ime of he hybrid cscode compesio echique for wosge cl A/A mplifier is proposed. Opiml desig iues of power diipio re cosidered o chieve he lowes power cosumpio for he required selig ime. Filly, desig exmple is preseed o show boh he usefule of he hybrid cscode compesio d he proposed desig procedure. The proposed desig echique c help circui desigers s well s i c be used i compuer ided circui desig ools. 1. Iroducio Severl frequecy compesio echiques such s Miller d cscode compesios re used o desig he sble wo-sge opmps [1, ]. The mi drwbcks of Miller compesio scheme re he low speed d low power supply rejecio rio (PSRR compred o he cscode compesio. scode compesio scheme chieves higher speed d higher PSRR compred o Miller compesio he cos of complex desig d lysis procedure [, 3]. A ovel cscode compesio scheme clled hybrid cscode compesio hs bee iroduced i [4, 5] by he uhors. I his mehod, wo disic cpciors re used bewee wo low-impedce odes of he firs sge d he oupu ode. I ur, his compesio echique merges Ahuj [] d improved Ahuj syle [6] compesio mehods. This scheme of compesio yields higher mplifier bdwidh compred o he sdrd Miller d coveiol cscode compesio echiques he cos of more complex desig procedure for he selig behvior of he mplifier. This echique lso offers ll dvges of he cscode compesio echique such s high PSRR, ec. I [4, 5] closed loop lysis of he hybrid cscode compesio hs bee iroduced d lso closed loop desig procedure hs bee proposed. I order o ge more isigh i he desig of his compesio scheme d lso show is usefule furher, is ope loop sigl rsfer fucio hs bee obied i [7] o ccurely esime is poles d zeros. However, i [4, 5] fourh order sysem hs bee lyzed o obi desig procedure mkig he desig more compliced d eed solvig se of equios by umericl equios solvig ools. As show i [7] cosiderig severl good pproximios resul i he sysem order o be reduced o hree mkig he closed loop desig more relxed s will be preseed here. This pper uses he ope loop lysis resuls of [7] o chieve simple sysemic desig procedure for wo-sge opmps wih hybrid cscode compesio mkig heir desig very srighforwrd. Opiml desig iues of power diipio re lso cosidered i he proposed desig procedure here. The pper is orgized s follows. Secio preses he closed loop lysis of wo-sge opmp employig he hybrid cscode compesio mehod. I Sec. 3 opiml desig procedure is preseed o chieve miimum selig ime cosiderig he power opimizio. Secio 4 gives he simulio resuls i he coex of desig exmple. oclusios re give i secio 5.. losed oop Alysis Figure 1 shows wo-sge cl A/A OTA composed of folded-cscode s he firs sge d he cl A mplifier wih cive curre mirrors s he secod sge h employs he hybrid cscode compesio echique [4, 5]. I is worh meioig h he compesio mehod c esily be pplied o he oher wo-sge OTAs. As show i Fig. 1 wo sepre cpciors, d s, hve bee used for compesio of he opmp where is used i sigl ph d s i o-sigl ph. The secod sge is cl A mplifier wih cive curre mirrors similr o [8] /DATE6 6 EDAA

2 Vdd od vou+ M4 s ou Vdd M9 M7 M3 M Vb4 Vb3 Vb vi+ oup Vb4 cmfb1 M1 M1 M1b A A Vb1 ou M7b M3b Mb Vdd M9b s oup M4b Vb3 Vb vi- vou- od M5 M8 M6 M6b M8b M5b Fig. 1: A wo-sge cl A/A OTA wih hybrid cscode compesio. I c redily be show h usig he similr pproch preseed i [7] o clcule he ope loop loops d zeros of wo-sge cl A mplifier wih hybrid cscode compesio he closed loop sigl rsfer fucio of he opmp show i Fig. 1 wih cosiderig g m = g m3 d = s is obied s follows: ( g ( g + g s v ou g Av ( s = = vi d 1 + d (1 where d 3 m1 m m4 m5 3 s d 3 + s d + s d g m( + s + f g m1 ( g g d 1 ( g m4+ g m5 m + m3 d f g g ( g + g 5 m1 m m4 m = db db3 gs4 gd gd 3 gs9 = + + od db4 db5 d f is he feedbck fcor i closed loop cofigurio. I hese clculios, i ws umed h he prsiic cpcices of he odes A,, d re much smller h he compesio cpciors, s d he lod cpcice. I ws lso umed h he rscoducce of rsisors, g mi, is much greer h he coducces see he odes A,,, d oupu d he mirror pole d zero re greer h he oher o-domi poles d zeros. This c be chieved by properly choosig he bis curre of he cive curre mirrors. I ws lso umed h he rscoducce of rsisors M8 d M9 o be equl. s 3. Desig Procedure 3.1 Selig of Sdrd 3 rd Order Sysem As show i he previous secio d lso i [7], he g m = g m3 d = s umpio reduces he order of he ope loop d closed loop sysem rsfer fucios o hree. So, i order o ivesige he selig behvior of he hybrid cscode compesio echique, sdrd hird order sysem wih he followig rsfer fucio is cosidered: k( γ ζ ω s H ( s = ( ( s + αζω ( s + ζω s + ω As i is see, here re four sysem prmeers, α, γ, ω, d ζ i he rsfer fucio. ω d ζ re clled he url frequecy d dmpig fcor, respecively. The selig error i defiie ime period of s defied ε s αζ e + (1 αζ αζ e + (1 αζ s( s( = s( + α ζ 1 ε s = e (1 αζ + α ζ ζω ζω is obied by: αζω ( ζ + αζ cos( ω (1 ζ + αζ si( ω + α ζ 1 ζ 1 ζ 1 ζ where s( is he sep respose. I he clculio of he sep respose, i ws umed h γ goes o ifiiy sice i he prcicl cses he righ d lef-ple zero pir i he closed loop rsfer fucio re much higher (3

3 frequecies h he oher poles d zeros. However, his equio is very complex o iuiively expli how o choose he sysem prmeers o opimize he selig behvior. Therefore, umericl clculios re used. Figure shows he selig error for differe vlues of he sysem prmeers. For exmple, he obied sysem prmeers for 8 d selig error re α = 1, ζ =. 9, d ω = 11. Selig error (d Selig error (d α = 1 ( ζ =.75 ζ =.8 ζ =.85 ζ =.9 ζ = ω ζ =.9 (b α =.7 α =.8 α =.9 α = 1 α = ω Fig. : Selig error s fucio of ω for differe vlues of ( ζ, d (b α. 3. Smll Sigl Selig Usig he obied sysem prmeers for specific selig error i defied ime d he opmp closed loop rsfer fucio give i (1, he device prmeers c be deermied wih he followig equios: ( + α ω (4 g m ( + + s f g m1 ζ = g m + g m3 ( g m4+ g m5 = 3 f g m1 g m ( g m4+ g m5 = ( ( 1 + ω αζ (5 α ζ ω (6 I hese equios, wo of sysem prmeers, α d ζ, re kow. The vlue of ω is o kow. However he vlue of ω is kow. The opiml vlue of lier selig ime,, is obied i he ex subsecios o deermie he ω efficiely. 3.3 lculio of he ompesio d od pciors The lod d compesio cpciors,,, d s re deermied due o he circui oise cosiderios. I c be show usig he similr pproch iroduced i [9], he ol oupu herml oise power of he opmp show i Fig. 1 wih he hybrid cscode compesio i closed loop cofigurio umig g m = g m3 d = s wih feedbck fcor of f is s follows: kt g m6 g m7 S N, ou = f ( + s g m1 g m1 (7 ( + α (1+ αζ 1+ α ζ + α ζ As i is see from he bove relio, he sum of he compesio cpciors, i.e. d s, is obied i such wy o chieve he required oise budge. The lod cpcior is deermied by he oher cpcices of he swiched-cpcior circui h employs he opmp d lso is circui srucure. I is worh meioig h he vlue of he cpcices of swiched-cpcior circuis is deermied by he kt/ oise of he swiches, mchig of he elemes, ec. 3.4 Opimizio of he is urres The ol selig ime of opmp cosiss of wo disic regios [1]. I he firs regio, he opmp slews sice whe he ipu sigl is lrge, oe of he ipu rsisors my ur off. The secod regio of selig is he lier selig where i his regio he smll sigl prmeers of he opmp c be used o describe is selig behvior s employed i he previous secio. The lrge sigl selig behvior of opmp is described by quiy clled he slew re d is relio for he circui show i Fig. 1 is s follows: I DS1 SR = (8 + s where he bis curre of boh ipu sge d cscode rsisors re umed equl. To opimize he bis curres of he opmp d hece o reduce is power diipio, he curre of he ipu rsisors, M1, is chose equl wih he vlues obied from he slewig relio [1], i.e.: 1 1 V FS 1 I DS1 = ( + s SR = ( + s = g m1 V eff 1 (9 = + (1 s ls ls

4 where V FS is he differeil oupu sigl sep d ls d re he lrge d smll sigl selig imes, respecively. The rscoducce of he ipu rsisors c be obied usig he equios (4-6 s follows: g m1 α ζ ω 1 = (11 f 1+ α ζ So, he opiml bis curre of he ipu rsisors d lso he opiml lier selig ime re obied s follows: I DS1, op 1 1 α ζ ω = ( + + s V FS V eff 1 (1 s f 1+ αζ α ζ ω V eff 1 = s (13 f V ( 1+ α ζ + α ζ ω V FS eff 1 The opiml bis curre of he oupu rsisors is deermied usig he followig relio: 1 I DS4, op = g m4 V eff 4 (14 where he vlue of V eff4 is obied from he required oupu sigl swig. g m4 is deermied by solvig he smll sigl equios of (4-6. The vlue of ω is obied from Fig. for specific selig error d he vlue of is derived from relio (13. So, he opiml vlue of ω is lso obied. 3.5 Solvig he Smll Sigl Equios The smll sigl equios of (4-6 c be solved o deermie he rscoducce of he criicl devices, i.e. M1, M, M3, M4, d M5. However, sice he vlue of is ukow before he circui is desiged, so o solve hese equios suible vlue for is cosidered firsly. osiderig is kow, he device rscoducces will be obied by solvig he equios (4-6 s follows: α ζ ω g m1 = (15 f 1 + α ζ g ( g m m4 ( + α (1 + α ζ + α = ζ ω (16 (1 + α ζ ( g m5 ( = + s + ω (1 + α ζ ( + α (1+ α ζ ζ + α ζ s (17 Afer obiig he rscoducce vlue of he criicl rsisors d he vlue of bis curres, he rsisors dimesios re deermied. The, circui level simulors c be used o derive he opmp s specificios. A he circui level simulios, he vlue of is deermied. The rscoducce of criicl rsisors re derived ccurely usig he bovemeioed relios gi. This procedure c be repeed for few imes o ccurely iclude he effec of i he relios ( A he ls sep of desig few circui level ierios re lso performed o refie he rsisors dimesios. The desig procedure proposed i his pper is summrized s follows: 1. Derive he sysem prmeers for required selig ccurcy from Fig... Esime he vlue of he compesio cpciors from he relio (7 o chieve he required oupu oise volge. Aume suible iiil vlue for he firs sge oupu ode prsiic cpcice,. The vlue of is obied from he circui srucure h employs he opmp. 3. lcule he bis curres d lier selig ime from he relios (1-14 for he required oupu sigl swig. 4. lcule he rscoducce vlue of he criicl rsisors, i.e. M1, M, M3, M4, d M5, from he relios ( Size ll of he rsisors d ru circui level simulios o obi he required specificios d lso he vlue of he firs sge oupu ode prsiic cpcice,. If he vlue of is differe from is iiil vlue, repe he desig procedure from sep 4. lcule he oupu oise power usig he circui level simulor d djus he compesio cpciors d go o sep 3 if he oupu oise power is le or greer h he required vlue. 6. heck he oher circui requiremes d perform few ierios he circui level simulios o refie he rsisors dimesios if he required desig specificios re o sisfied. 4. Desig Exmple 4.1 Desig Prmeers d lculios To verify he usefule of he proposed desig procedure for he hybrid cscode compesio OTA wih he srucure show i Fig. 1 ws desiged d simuled usig.18-µm SIM3v3 level 49 mixed-sigl MOS models wih HSPIE. The desig is rgeed for relizio of fully differeil swiched-cpcior

5 iegror o be used i sigm-del modulor wih he specificios show i Tble 1. The vlue of he smplig cpcior is deermied by he kt/ oise budge. Is vlue is cosidered o be 5-pF resulig i he SNR due o he kt/ oise of he swiches o be more h 94-d. The vlue of iegrig cpcior is cosidered s 1-pF o chieve gi of.5. Tble 1: Desig prmeers Prmeer Vlue Selig ccurcy 15-bi Smplig frequecy 4-MHz Mximum oupu sigl swig 1.5-V PP, differeil SNDR 9-d Gi ( 1/.5 D gi 7-d Oversmplig rio 8 Mximum differeil oupu sigl sep (V FS.5-V Power supply volge (V DD 1.5-V Techology.18-µm MOS To ge 15-bi ccurcy, i.e..% or -94-d selig error, he sysem prmeers re obied usig Fig. s α =1, ζ =. 9, d ω =1. 5. The compesio cpciors is chose 1.5-pF resulig i he SNR due o he opmp s herml oise o be more h 95-d. The vlue of he lod cpcice,, is obied 8-pF cosiderig he iegror lodig, prsiic d boom ple cpcices. To sisfy he required oupu sigl swig wih sufficie lieriy he effecive overdrive volge of M4 d M5 is cosidered.v. The effecive volge of he ipu rsisors ws lso cosidered.v o chieve he required lieriy. The vlue of is esimed o be.3- pf, firsly. Tble shows he derived sysem prmeers usig he proposed desig equios d lso heir simuled vlues i he fil desig. Tble : lculed d simuled device sizes lculed Vlue Simuled Vlue Prmeer g (W/ g m (ma/v (W/ m (ma/v M1, M1b / M, Mb / M3, M3b / M4, M4b / M5, M5b / M6, M6b / M7, M7b / M8, M8b / M9, M9b / M / The bis curre of he ipu d oupu sges were obied.7ma d.1ma, respecively. A he circui level simulios oly he bis curre of he oupu sge ws icresed (bou 3 imes mily i order o move he mirror pole d zero of cive curre mirrors o higher frequecy. The oher circui prmeers hve o bee chged cosiderbly. The bis curre of cive curre mirrors ws se o oe hird of he oupu rsisors. 4. Simulio Resuls The desiged opmp ws simuled wih HSPIE wih he device prmeers show i Tble. The commo mode ipu volge ws.v. The body ermil of ll NMOS d PMOS rsisors were coeced o he V SS d V DD, respecively. Tble 3 shows he simuled d clculed ope loop poles d zeros of he hybrid cscode compesio. I hese clculios, he circui prmeers exrced from HSPIE simulios d show i Tble 4 were used i he relios preseed i [7]. These simulios furher idice h he umpios used o reduce he sysem order o hree hve he sufficie ccurcy. Figures 3 d 4 show he ope loop frequecy respose d selig performce of ll hree cscode compesio schemes, respecively. A summry of he simulio resuls is show i Tble 5. Tble 3: Simuled d clculed poles d zeros vlues Prmeer Simulio lculio f p1 (khz f p (MHz f p3, 4 (MHz f z1 (MHz f z, 3 (MHz Tble 4: Device sizes d circui prmeers Prmeer R A R R R A, s Vlue.85 kω kω.77 kω 4.4 kω.13pf.65pf.8pf 8pF 1.5pF I hese simulios, equl vlues for he rsisors dimesios d bis curres hve bee used excep he ipu rsisor sizes of he coveiol cscode compesio hve bee desiged o ge he sme phse mrgi for boh hybrid d coveiol cscode compesio circuis d lso he ipu d o-sigl ph cscode rsisors of he improved cscode compesio hve bee sized o chieve beer selig performce. Simulio resuls show h he hybrid cscode compesio scheme chieves uiy-gi bdwidh greer h h of he coveiol cscode

6 compesio which resuls i smller selig ime s show i Fig. 4. Simulio resuls of he improved cscode compesio show h is zero is so close o he uiy-gi bdwidh which resuls i lrge phse mrgi d so degrded selig behvior. To improve is selig performce he dimesios of is ipu d osigl ph cscode rsisors, M1 d M3, hve bee sized bou.65 d wo imes of hose of he hybrid cscode compesio mehod, respecively. The hybrid cscode compesio lso chieves bou 1-d D gi greer h he coveiol d improved cscode compesios. The slew re d ipu referred herml oise of ll hree cscode compesio schemes re pproximely he sme. Oupu volge (V D gi (d D gi (d D gi (d ( (b (c Frequecy (Hz Fig. 3: Frequecy respose simulio resuls: ( hybrid, (b coveiol d (c improved cscode compesio mehods Hybrid cscode compesio oveiol cscode compesio. Improved cscode compesio Time (s Fig. 4: Selig simulio resuls Phse mrgi (degree Phse mrgi (degree Phse mrgi (degree Tble 5: Simulio resuls summry Prmeer Hybrid scode oveiol scode Improved scode Uiy-gi bdwidh MHz 16.7 MHz 1.1 MHz Phse mrgi D gi 76. d 75.1 d 75. d.% selig ime 11. s 15.7 s 3.1 s Power diipio 3.64 mw 3.64 mw 3.64 mw 5. oclusios I his pper, sysemic desig procedure for he hybrid cscode compesio mehod ws preseed. The oly drwbck of he hybrid cscode compesio ws is complex desig procedure for required selig ccurcy. I order o reduce is desig ime d lso chieve efficie power opimized desig, he rscoducce of he criicl rsisors d he bis curres re seleced opimlly. The proposed desig mehod c lso be exeded for oher cscode compesio mehods efficiely. 6. Refereces [1]. Rzvi, Desig of Alog MOS Iegred ircuis, New York: McGrw-Hill, 1. []. K. Ahuj, A improved frequecy compesio echique for MOS operiol mplifiers, IEEE J. Solid-Se ircuis, vol. 18, o. 6, pp , Dec [3] D.. Riber d M. A. opeld, Desig echiques for cscoded MOS op mps wih improved PSRR d commo-mode ipu rge, IEEE J. Solid-Se ircuis, vol. S-19, o. 6, pp , Dec [4] M. Yvri d O. Shoei, ow-volge low-power fsselig MOS operiol rscoducce mplifiers for swiched-cpcior pplicios, Proc. ISPED, pp , Aug. 3. [5] M. Yvri d O. Shoei, ow-volge low-power fsselig MOS operiol rscoducce mplifiers for swiched-cpcior pplicios, IEE Proc. ircuis, Devices, d Sysems, vol. 151, pp , Dec. 4. [6]. Yo, M. Seyer, d W. Sse, Fs-selig MOS wo-sge operiol rscoducce mplifiers d heir sysemic desig, Proc. ISAS, vol., pp , My. [7] M. Yvri, Hybrid cscode compesio for wo-sge MOS opmps, IEIE Trs. Elecro., vol. E88-, o. 6, pp , Jue 5. [8] S. Rbii d. A. Wooley, A 1.8-V digil-udio sigmdel modulor i.8-µm MOS, IEEE J. Solid-Se ircuis, vol. 3, o. 6, pp , Jue [9] A. Feldm, High-speed, low-power sigm-del modulors for RF bsebd chel pplicios, Ph.D. Dierio, Uiversiy of lifori, erkeley, A, [1] R. ofi, M. Therzdeh, M.Y. Azizi, d O. Shoei, A low-power desig mehodology for high-resoluio pipelied log-o-digil coverers, Proc. ISPED, pp , Aug. 3.