On the difference between thermal cycling and thermal shock testing for board level reliability of soldered interconnections

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1 Microelectronics Reliability 47 (27) On the difference between thermal cycling and thermal shock testing for board level reliability of soldered interconnections J.W.C. de Vries a, *, M.Y. Jansen a, W.D. van Driel b,c a Philips Applied Technologies, High Tech Campus 7 (3A), 5656AE Eindhoven, The Netherlands b Philips Semiconductors, IMO Backend Innovation, Gerstweg 2, 6534AE Nijmegen, The Netherlands c Delft University of Technology, Mekelweg 2, 2628CD Delft, The Netherlands Received 8 November 25; received in revised form 15 May 26 Available online 1 July 26 Abstract In this work, the endurance behavior of a ball grid array package is determined at two different temperature cycle conditions: a thermal cycle test and a thermal shock test. The observed failure distributions and failure modes allow deriving a translation factor between the two test conditions. Finite element analyses are carried out to design a predictive simulation model for the fatigue lifetime. Using an isothermal approach, a discrepancy is found between the experimental and simulated results. Incorporating the experimentally measured temperature gradients into a semi-transient model leads to a better match with the observed lifetimes. In particular for the fast thermal shock loading this turns out to be necessary. The results prove that temperature gradients in BGA-packages play an important role in board level reliability testing. Ó 26 Elsevier Ltd. All rights reserved. 1. Introduction One of the challenges in reliability testing of electronic components, assemblies, and systems is to find translations or acceleration factors for the lifetime between field conditions and test conditions. For many applications the electrical interconnection between the component and the printed circuit board is the most critical one, and reliability studies will concentrate on test structures on sub-assembly or board level. Although the introduction of portable products has led to failures related to all kinds of mechanical stress, because of the increased power density the larger part of failure modes will probably still be attributed to the influence of temperature. In particular repetitive changes of temperature, either from external heat sources or from internal dissipation, lead to fatigue cracks in the soldered interconnections. Usually a series of test structures is subjected to * Corresponding author. Tel.: ; fax: address: j.w.c.de.vries@philips.com (J.W.C. de Vries). a more or less standardized stress condition, for instance, a temperature cycle, and the failure rate is monitored against the number of cycles. By means of the empirical Coffin Manson relation the number of cycles to failure from the accelerated test is converted to the expected number of cycles to failure under user s conditions. Further, finite element analysis (FEA) is commonly used in combination with experiments to assist in explaining the reason for failure of products, and where and under which conditions high stresses occur [1 4]. FEA is instrumental in predicting stresses in configurations after design changes and under different test conditions, and thus it is a tool used for design optimization. However, models are simplifications of the real situation because they contain assumptions. Therefore it is necessary to check the validity of the models by means of experiments. In this work, finite element analyses and experiments are done on ball grid array (BGA) packages that are subjected to two types of thermal stress tests. The basic difference between the two tests lies in the ramp rates of the temperature. As will be shown, eventually a significant modification of the numerical model is necessary /$ - see front matter Ó 26 Elsevier Ltd. All rights reserved. doi:1.116/j.microrel

2 J.W.C. de Vries et al. / Microelectronics Reliability 47 (27) On the one hand there are many publications on the above subjects, however remarkably few cover the same combination as presented in the current work. Syed and Darveaux [5] and Lee and Lau [6] address amongst other subjects thermal loading of ball grid array packages in combination with finite element modeling. In the work of Ghaffarian and Kim, very similar packages (such as PBGA256) and tests are described [7]. Bartelo et al. have studied the effect of various temperature load profiles on the endurance behavior of ceramic BGA-packages [8]. Still, a good explanation on the difference between thermal cycling tests, with relatively slow ramping, and thermal shock tests, with faster ramping, has not been published. 2. Experimental and simulation aspects Solder fatigue cracks usually begin to become manifest in the situation where the thermal expansion mismatch is largest, which is obviously at the extremes in a thermal cycling test, while at ambient conditions the crack can be tightly closed. Thus using an off-line measurement method one runs the risk of falsely measuring a low resistance of the soldered joints. On-line measurement of the resistance of the daisy-chained interconnections is then necessary. In the present work, event detection was used to follow the resistance degradation of packages. With this continuous monitoring technique intermittent high-resistance events can be detected. Also elsewhere this method is used [6 8]. For the present study ball grid array packages with 256 solder balls in four peripheral rows were soldered onto a four-layer panel of 1.6 mm thickness. Prior to assembly, the packages were dried at 125 C. Solder paste (Multicore SnPbAg, eutectic composition) was printed with a 15 lm thick stencil onto the panels. The assemblies were soldered in a reflow furnace with a set peak temperature of 26 C. Further geometrical data of this BGA-package are listed in Table 1. Both the package and the printed circuit board were designed with a daisy chain structure incorporating all 256 soldered interconnections. This has become an accepted method to check the integrity of interconnections. In particular for ball grid array packages or chip scale packages where visual inspection to investigate the reliability is nearly impossible, this is a convenient solution. The experiments consisted of 9 packages divided over six panels, three of which were subjected to a thermal cycling test (TCT) and the other three to a thermal shock test (TST, air to air). The duration of the cycles was Table 1 Geometrical data of BGA256 Package size (mm 2 ) Package thickness (mm) 2.3 Pitch (mm) 1.27 Die size (mm 2 ) Die thickness (mm).28 Table 2 Test conditions [9] Test T min d min r up T max d max r down TCT TST Thermal cycling (TCT) and thermal shock (TST) test. Temperature extremes (T min/max, C), ramp times (r,min), dwell times at the extremes (d min/max,min) Fig. 1. Profiles of cycle (top) and shock test (bottom). Conditions as in Table 2. The symbols show one cycle of the simulated profiles. 6 min for the cycle and 4 min for the shock test. The tests were carried out according to JESD22-A14-B [9] with conditions as listed in Table 2. In Fig. 1, typical temperature profiles are shown as they were measured with thermocouples on the products. The effective dwell times and ramp rates are estimated from these curves using the JEDEC tolerances on the extreme temperatures of T max 5 C/+1 C and T min +5 C/ 1 C and are listed in Table 2. The ramp rates are defined as the tangents to the temperature curves. The cycle test was carried out in a single-chamber system, while the shock test was done in a two-valve system by which the experiment is alternately exposed to a hot and a cold buffer. In an accompanying experiment, thermocouples were mounted on four locations on a test board with BGA256-packages as shown in Fig. 2: one on top of the package ( top ), one on the bottom of the package ( bot ), one in a solder ball ( bmp ), and one on the board between the products ( pcb ). This assembly was exposed to the same temperature profiles as the test boards, using the same test load. Doing such, six temperature differences could be determined for each temperature profile.

3 446 J.W.C. de Vries et al. / Microelectronics Reliability 47 (27) pcb top BGA256 bot bmp Fig. 2. Schematic of the location of the four thermocouples. Δ Δ Fig. 3. Geometry of the finite element model. The failure distributions were analyzed with commercially available statistical software assuming a lognormal distribution. A selection of failed products was inspected by cross sectioning to determine the failure mode. A quarter model was made of a single BGA mounted on a printed circuit board as shown in Fig. 3. The critical solder ball has a detailed shape, which was determined with surface evolver [1]. The other solder balls were modeled by adjusted linear elastic beam elements [11]. The properties of the beams were adjusted to fit the behavior of the solder joint well. Their behavior was tested in a two solder ball model, described in [12]. The critical solder ball has creep and plasticity properties [13]. The molding compound and PCB are visco-elastic with 15 time constants. Other materials are elastic. Two load profiles were used derived from the experimental temperature tests (see Fig. 1). During one cycle the increase in inelastic strain was calculated and averaged over a 1 lm thick disk at the top of the solder bump. The mean time to failure was calculated from this value. Two cycles were simulated. The inelastic strain value in the first cycle was equal to that of the second cycle. The stress-free temperature of the assembly was chosen to be 125 C. This is lower than the melting temperature of the solder. A higher stress-free temperature will not change the lifetime much, since the inelastic strain in one cycle is used as a measure for lifetime and this does not change much when the stress-free temperature rises a bit Fig. 4. Temperature differences between locations as defined in Fig. 2. Top: cycle test; bottom: shock test. Temperature profile (right axis, ). DT (left axis): top-bot ( ); top-bmp ( ), top-pcb ( ); bot-bmp ( ); bot-pcb ( ); bmp-pcb ( ). (For colour interpretation of this figure, the reader is referred to the web version of this article.) In Fig. 4, the results of the temperature differences as measured with the thermocouples in the two types of thermal stress tests are shown. The measured minimum and maximum temperature differences between the bottom of the package and the board are DT min/max = 3/9 C in the cycle test and DT min/max = 14/13 C in the shock test. Between top and bottom of the package these gradients are 4/1 C in the cycle and 14/11 C in the shock test. Clearly, in the temperature shock test these differences are largest. Cross sections were made of failed products. In Fig. 5, some typical examples are presented. Cracks can be seen starting in the solder and running close to the Cu 6 Sn 5 -intermetallic layer at the side of the component. From the appearance of the deformation and the location of the cracks, the majority of which runs through the solder, the conclusion can be drawn that in both tests the failure mode is the same. The failure distribution that results from the thermal cycling test (see Fig. 6) is mono-modal, whereas the 3. Results Fig. 5. Typical failures after test. Fatigue cracks run at side of the component. Left: cycle test; right: shock test.

4 J.W.C. de Vries et al. / Microelectronics Reliability 47 (27) cumulative failures (%) thermal shock test leads to a distribution with a tail towards a low number of cycles. Neither during the inspection of the samples directly after assembly, nor from the failure analysis could an indication be found for the mechanism of this additional small set of failures. Still, the two main branches of the distributions are parallel, as the statistical data in Table 3 show; the three early failures from the thermal shock test were treated as suspended data, and excluded from the evaluation. In combination with the failure analysis this means that the failure mechanism evoked by the two tests is very certainly identical and is due to solder fatigue. Also the value of the shape parameter strongly points to this mechanism. Only after having established this, it is allowed to compare the test results of both experiments and estimate an acceleration factor. 4. Discussion N-cycles Fig. 6. Log-normal distributions BGA256. (r): shock ( 55 C/125 C/ 4 ) three early failures; (s): cycle ( 4 C/125 C/6 ). Table 3 Log-normal statistical parameters TCT TST N l r % Number of products (N), scale (l) and shape (r) parameters, cycles to 5% failures. Data are fitted with a mono-modal distribution. The number of cycles to failure from the shock test (332) matches quite well to the 38 cycles of the PBGA256-package mentioned elsewhere [7]. Likewise the lifetime in the cycle test (467 cycles) comes very close to the 4917 cycles obtained for PBGA324 [6]. In both studies the packages were of equal size as in the current study (27 27 mm 2 ). The authors note that in the latter reference only the nominal and not the actual temperature profile was reported. Bartelo et al. [8] did measure the temperature on mm 2 ceramic BGA625-components in a thermal cycling test ( 4 C/+125 C), but only the relative number of cycles to failure is reported. One of the most common models to relate the thermally induced deformation to the number of cycles to failure (or lifetime, N 5 ) is the Coffin Manson equation: N 5 = C(De in ) b [14,15]. This is a convenient way to translate between the results of different test conditions. For eutectic SnPb-solder, the exponent b is quite often taken as 2. Other authors have estimated the exponent b for ball grid array packages as 1.2 [16] and for a time dependent creep model as 1 [17]. Adopting these latter two values in the present situation and taking in the above equation De in / DT, this would lead to an acceleration factor between the temperature cycle test ( 4 C/+125 C) and the shock test ( 55 C/+125 C) of 1.1. Using b = 2 this is 1.2. Experimentally the acceleration factor, the ratio between the two observed lifetimes (see Table 3), is 1.4 ±.1 within a confidence level of 95%. Obviously, this rather simple model approach is not sufficient to treat such different situations as addressed in this work. For the isothermal calculations Fig. 7 shows the averaged accumulated inelastic strain in the critical solder ball in one cycle in the thermal shock test and the thermal cycle test. The inelastic strain is mainly creep strain. The plastic strain is less than 1% of the total inelastic strain. Most of the creep is established during the temperature ramp up and ramp down. During dwell there is just a very little creep. At low temperature this is caused by very slow creep processes. At high temperatures this is caused by low stresses, because the product is close to the stress-free temperature. The cycle test gives more inelastic strain in one cycle than the shock test. So the product will fail earlier in a thermal cycle than in a thermal shock test according to these simulations. This is also shown in Fig. 8, which shows the normalized mean time to failure calculated from the inelastic strains (N 5 ¼ C e 1:2 in fitted to the experimental values of the thermal cycle [16]). This is in contradiction with the experimental results that clearly show a higher mean time to failure for the temperature cycle test. The ε in ( ) Fig. 7. Averaged accumulated inelastic strain in solder ball as function of time. ( ): TCT isothermal, ( ): TST isothermal, : TCT semitransient, : TST semi-transient. (For colour interpretation of this figure, the reader is referred to the web version of this article.) 6

5 448 J.W.C. de Vries et al. / Microelectronics Reliability 47 (27) N5% (-) TCT TST Fig. 8. Cycles to failure for experiments and simulations on TCT and TST. Black: measured value, white: isothermal simulation, hatched: semitransient simulation. The results are normalized to the TCT test. acceleration factor from the simulation model is.9, which differs markedly from the experimental value of 1.4. From Fig. 4, it is clear that higher temperature gradients occur in the shock test than in the cycle test. This effect is investigated in a simple way with the finite element model. A simplified thermal transient calculation was done. Therefore the model was split up in four parts (see Fig. 9). The top part contains the molding compound, the die and die attach. The bottom part contains the solder mask and the substrate. The bumps and the printed circuit board are the third and fourth part. Elements in one part have the same temperature. For every part a different simplified temperature profile was derived from the measurement. In Fig. 7, the inelastic strain for the isothermal and semitransient calculations is given. The semi-transient calculations give more inelastic strain for both tests. However the difference for thermal cycling is small compared to thermal shock test where the temperature gradients add considerably more to the inelastic strain. The shock test is now the more critical one of the two, which is also shown in the expected number of cycles to failure, shown in Fig. 8. The trend in experiments and semi-transient calculation is similar. The modified model leads to a lifetime-ratio between the two test conditions of 1.8, which compares much better to the experimental factor of 1.4. The increase in inelastic strain is mainly caused by an increase in creep strain. The thermal cycle test has still no Fig. 9. Model with semi-transient thermal behavior. plastic strain. The inelastic strain in the thermal shock test now accounts for 1.5% of the plastic strain. 5. Conclusion Thermal cycle and thermal shock experiments were done with a BGA256 package soldered on a printed circuit board, showing that the product survives significantly longer in the cycle test. Detailed temperature measurements on various locations on the package and the board revealed appreciable temperature gradients. These are different for the two types of tests, and largest for the shock test. The experiments were simulated with finite element analyses. Isothermal simulations give opposite trends compared to the experimental results. The model was split up in four sections with different temperature profiles according to the temperature measurements. Although this is a very coarse representation of the real temperature field, it changes the results completely bringing the trends in line with experiments. So thermal shock tests seem advantageous, because they strongly accelerate failures. However care should be taken. In thermal cycle tests stresses are mainly caused by mismatch of thermal expansion coefficients, which depend on the combination of materials that is used. In thermal shock tests additional stresses can be generated due to temperature gradients, which depend on the thermal behavior of the tested system. This can cause different test results for systems that have the same performance in a temperature cycle test. The thermal shock test could even give different types of failures. As a final remark the authors emphasize that this study concerns some additional experimental and numerical tools to address the fatigue behavior of soldered interconnections. Although the presented examples are based on lead-containing solder, the methodology should also be applicable to lead-free solder compositions as well, because they are also known for creep dominated failures. References [1] Syed A. Thermal fatigue reliability enhancement of plastic ball grid array (PBGA) packages. In: Proc ECTC, p [2] van Driel WD, Zhang GQ, de Vries JWC, Jansen MY, Ernst LJ. Virtual prototyping and qualification of board level assembly. In: Proc EPTC, 24. p [3] Syed A. Accumulated creep strain and energy density based thermal fatigue life prediction models for SnAgCu solder joints. In: Proc ECTC, 24. p [4] Jansen KMB, Wang L, Yang DG, van t Hof C, Ernst LJ, Bressers HJL, et al. Constitutive modeling of molding compounds. In: Proc ECTC, 24. p [5] Syed A, Darveaux R. LGA vs. BGA: what is more reliable? A 2nd level reliability comparison. In: Proc SMTA, 2. p [6] Ricky Lee SW, Lau D. Computational model validation with experimental data from temperature cycling tests of PBGA assemblies for the analysis of board level solder joint reliability. In: Proc EuroSimE, 24. p

6 J.W.C. de Vries et al. / Microelectronics Reliability 47 (27) [7] Ghaffarian R, Kim NZ. Reliability and failure analysis of thermally cycled ball grid array assemblies. IEEE Trans Compon Pack Technol 2;23: [8] Bartelo J, Cain SR, Caletka D, Darbha K, Gosselin T, Henderson DW, et al. Thermomechanical fatigue behavior of selected lead-free solders. In: Proc IPC SMEMA Council, APEX, 21, LF2-2. p [9] Temperature cycling. JEDEC standard JESD22-A14-B, July 2. [1] Brakke KA. Surface evolver, free of charge. Available from: [11] Davuluri P. A multi scale modeling approach for stress analysis of electronic interconnects. PhD thesis, University of Maryland, 21. [12] Jansen MY, de Vries JWC, van Driel WD. An efficient method for assessing board level reliability for micro-electronic packages using combined experimental numerical techniques. In: Proc EuroSimE, 26. p [13] Dudek R, Doring R, Michel B. Reliability prediction of area array solder joints. In: Proc EuroSime, 21. p [14] Coffin LF. A study of the effect of cyclic thermal stress on a ductile material. Trans ASME 1954;76: [15] Manson SS. Fatigue: a complex subject some simple approximations. Exp Mech 1965;5: [16] Vandevelde B. Thermo-mechanical modeling of solder joint reliability for electronic package systems. PhD thesis, Katholieke Universiteit Leuven, 22. [17] Syed A. Predicting solder joint reliability for thermal, power & bend cycle within 25% accuracy. In: Proc ECTC, 21. p