PCIe* 4.0 Retimer Supplemental Features and Standard

Transcription

1 PCIe* 4.0 Retimer Supplemental Features and Standard BGA Footprint November 07 Document Number: US

2 Legal Lines and Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Copies of documents which have an order number and are referenced in this document may be obtained by calling or by visiting Intel, the Intel logo, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright 07, Intel Corporation. All Rights Reserved. PCIe* 4.0 Retimer Supplemental Features and Standard BGA Footprint November 07

3 Contents Introduction...7. Overview...7. Terminology...9. Specification References Retimer Supplemental Features Beyond PCIe* 4.0 Specification...9 Mechanical Specification.... Overview... Signal Description.... x6 Retimer Interface Signals..... Signal Descriptions x6 Retimer Ballmap (Package Side) x6 Retimer, Platform side Pin Arrangement....4 x6 Retimer Package-side Ball Arrangement....5 x6 Retimer Platform-side Land Pattern....6 x8 Retimer Interface Signals Signal Descriptions x8 Retimer Ballmap X8 Retimer, Platform-side Land Pattern x8 Retimer Package-side Ballmap x8 Retimer Platform-side Land Pattern x4 Retimer Interface Signals Signal Descriptions.... x4 Retimer Ballmap.... x4 Retimer, Platform side Land Pattern x4 Retimer, Physical Ballmap (Package Side) X4 Retimer Platform-side Land Pattern Electrical Characteristics Absolute Maximum Ratings Power Consumption Power Supply Decoupling Retimer Latency Package Thermal Considerations SMBus and EEPROM Register Configuration Global Parameter Register Global Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register PCIe* 4.0 Retimer Supplemental Features and Standard BGA Footprint November 07

4 6.7 Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Physical Pseudo Port Parameter Register Register Offsets for Different Link Subdivision (Bifurcation) Register Bit Level Details...55 Figures - Platform Configuration with an Add-in Card and Retimer on Mother Board Platform Configuration with an Add-in Card and Riser, Retimer on Riser Platform Configuration with a Riser and Cable, Retimer is on Riser Platform Configuration with a Backplane, Retimer on both Mother Boards Retimer Form Factors... - x6 Retimer Block Diagram... - x6 Retimer, Package Side Pin Arrangement (Top View) x6 Retimer, Platform side Pin Arrangement (Top View) x6 Retimer, Physical Ballmap on Package (Top View) x6 Retimer, Platform Side Land Pattern with Spacing Details (Top View) x8 Retimer, Package-side Pin Arrangement (Top View) x8 Retimer, Platform-side Pin Arrangement (Top View) x8 Retimer, Physical Ballmap on Package (Top View) x8 Retimer, Platform-side Land Pattern with Spacing Details (Top View) x4 Retimer, Package-side Pin Arrangement (Top View)... - x4 Retimer, Platform-side Land Pattern (Top View) x4 Retimer, Physical Ballmap on Package (Top View) x4 Retimer, Platform-side Land Pattern with Spacing Details (Top View)...6 Tables - Abbreviations Retimer Feature Comparison x6 Retimer Signal Descriptions... - x8 Retimer Signal Descriptions... - x4 Retimer Signal Descriptions Absolute Maximum Voltage Ratings Recommended Absolute Maximum Power Ratings Register Offsets Register Bit Level Details (Sheet of 7) PCIe* 4.0 Retimer Supplemental Features and Standard BGA Footprint November 07

5 Revision History Document Number Revision Number Description Date Initial Release November 07 PCIe* 4.0 Retimer Supplemental Features and Standard 5 BGA Footprint November 07

6 6 PCIe* 4.0 Retimer Supplemental Features and Standard BGA Footprint November 07

7 Introduction. Overview PCI Express* Gen4 capable retimers extend the channel reach on a platform to beyond what is possible otherwise. With PCI Express Gen4 (6 GT/s), data rate has increased by x compared to previous generation (8 GT/s), resulting in shorter channel reach. Common use cases include channels expanding over system boards, backplanes, cables, risers, and add-in cards. Such long channels can have loss that far exceeds the spec loss target of -8 db at 8 GHz. Retimer is now part of PCI Express 4.0 base specification. PCI-SIG is expected to implement compliance program for testing retimers. It is expected that significant number of platforms using PCI Express Gen4 will require retimers. Multiple sources of retimers will make adoption of PCIe 4.0 technology easier. Common footprint simplifies the platform design process. Pinout is optimized for 6 GT/s signal integrity and thermal challenges. Figure - to Figure -4 show few example configurations involving Riser, Mother Board and Add-in Card. Various other configurations are possible. Figure -. Platform Configuration with an Add-in Card and Retimer on Mother Board PCIe* 4.0 Retimer Supplemental Features and Standard 7

8 Figure -. Platform Configuration with an Add-in Card and Riser, Retimer on Riser Figure -. Platform Configuration with a Riser and Cable, Retimer is on Riser Figure -4. Platform Configuration with a Backplane, Retimer on both Mother Boards 8 PCIe* 4.0 Retimer Supplemental Features and Standard

9 . Terminology The # symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When # is not present after the signal name, the signal is asserted when the signal is at a high voltage level. The following notations are used to describe the various signal types: Table -. Abbreviations Term I O I/O PU PWR Host NC VD SSC SRIS RX TX N/A Description Input Output Bi-Directional Pull-up Power Ground This term is synonymous with platform or system No Connect Vendor Defined Spread Spectrum Clocking Separate Reference Clock Independent SSC PCIe Receiver PCIe Transmitter Not Applicable. Specification References This specification requires references to other specifications or documents that will form the basis for some of the requirements stated herein. PCI Express Card Electromechanical (CEM) Specification, Revision 4.0, Version 0.5, December 8, 05 PCI Express Base Specification, Revision 4.0, Version 0.7, November, 06 System Management Bus (SMBus) Specification, Version.0, August, 000 JTAG Specification (IEEE 49.) IC* BUS Specifications, Version., January Retimer Supplemental Features Beyond PCIe* 4.0 Specification Table -. Retimer Feature Comparison (Sheet of ) Feature PCIe 4.0 Base Specification for Retimers PCIe 4.0 for Retimers Supplemental Features and Standard BGA Footprint Specification SRIS Optional Required Slave Loopback Optional Required Receiver Lane Margining (Voltage) Optional Required PCIe* 4.0 Retimer Supplemental Features and Standard 9

10 Table -. Retimer Feature Comparison (Sheet of ) Feature PCIe 4.0 Base Specification for Retimers PCIe 4.0 for Retimers Supplemental Features and Standard BGA Footprint Specification Dynamic Link Subdivision () Not defined explicitly but can be (Bifurcation) supported Required LPM Substates () Optional Required SMBus Programmable Configurations N/A Required Support for EEPROM load configuration N/A Required Retimer Common (size, pinout) Footprint N/A Required Reference Clock Out N/A Optional Notes:. Dynamic link subdivision should be implemented such that no power reset is required.. LPM Substate support for retimers as defined in Section 4..0 in PCIe Base Specification. 0 PCIe* 4.0 Retimer Supplemental Features and Standard

11 Mechanical Specification. Overview Three different retimer package sizes are specified. x4: Supports 4 lanes in upstream direction and 4 lanes in downstream direction x8: Supports 8 lanes in upstream direction and 8 lanes in downstream direction x6: Supports 6 lanes in upstream direction and 6 lanes in downstream direction The following figure shows the overall package dimensions for the three retimer form factors. Note that all the dimensions are in mm and the tolerance is ±0.5 mm. Figure -. Retimer Form Factors PCIe* 4.0 Retimer Supplemental Features and Standard

12 PCIe* 4.0 Retimer Supplemental Features and Standard

13 Signal Description This chapter provides a detailed description of retimer signals. The signal descriptions are arranged in functional groups according to their associated interface. Signal directions in Table -, x6 Retimer Signal Descriptions, Table -, x8 Retimer Signal Descriptions and Table -, x4 Retimer Signal Descriptions are from retimer perspective. that is, O indicates output from the retimer device and I indicates input to the retimer device. Signals labeled VD are Vendor Defined and it is assumed that VD balls carry signals that are not critical to retimer basic functionality and are used for providing enhanced or debug features. Common footprint for following link widths are defined for the PCIe 6 GT/s retimers:. x6 (Link with 6 physical lanes). x8 (Link with 8 physical lanes). x4 (Link with 4 physical lanes) The following figure shows the x6 retimer block diagram. Channel A and Channel B are ports that can be configured to be upstream or downstream. Figure -. x6 Retimer Block Diagram. x6 Retimer Interface Signals The following table lists pin numbers and functions for each of the pins in the x6 pinout, along with voltage level wherever applicable. Table -. x6 Retimer Signal Descriptions (Sheet of 6) Pin# Signal Name Signal Direction Signal Description Voltage Level High Speed Differential I/O M6 0 O P9 0 O Transmitter differential pair, A Channels, Lane 0 PCIe* 4.0 Retimer Supplemental Features and Standard

14 Table -. x6 Retimer Signal Descriptions (Sheet of 6) Pin# Signal Name Signal Direction Signal Description Voltage Level W6 O AA9 O AF6 O AH9 O AN6 O AR9 O AY6 4 O BB9 4 O BG6 5 O BJ9 5 O BP6 6 O BT9 6 O CA6 7 O CC9 7 O CH6 8 O CK9 8 O CR6 9 O CU9 9 O DB6 0 O DD9 0 O DJ6 O DL9 O DT6 O DV9 O EC6 O EE9 O EK6 4 O EM9 4 O EU6 5 O EW9 5 O N4 0 I R5 0 I Y4 I AB5 I AG4 I AJ5 I AP4 I AT5 I BA4 4 I BC5 4 I Transmitter differential pair, A Channels, Lane Transmitter differential pair, A Channels, Lane Transmitter differential pair, A Channels, Lane Transmitter differential pair, A Channels, Lane 4 Transmitter differential pair, A Channels, Lane 5 Transmitter differential pair, A Channels, Lane 6 Transmitter differential pair, A Channels, Lane 7 Transmitter differential pair, A Channels, Lane 8 Transmitter differential pair, A Channels, Lane 9 Transmitter differential pair, A Channels, Lane 0 Transmitter differential pair, A Channels, Lane Transmitter differential pair, A Channels, Lane Transmitter differential pair, A Channels, Lane Transmitter differential pair, A Channels, Lane 4 Transmitter differential pair, A Channels, Lane 5 Receiver differential pair, B Channels, Lane 0 Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane 4 4 PCIe* 4.0 Retimer Supplemental Features and Standard

15 Table -. x6 Retimer Signal Descriptions (Sheet of 6) Pin# Signal Name Signal Direction Signal Description Voltage Level BH4 5 I BK5 5 I BR4 6 I BU5 6 I CB4 7 I CD5 7 I CJ4 8 I CL5 8 I CT4 9 I CV5 9 I DC4 0 I DE5 0 I DK4 I DM5 I DU4 I DW5 I ED4 I EF5 I EL4 4 I EN5 4 I EV4 5 I EY5 5 I R p0 I N n0 I AB p I Y n I AJ p I AG n I AT p I AP n I BC p4 I BA n4 I BK p5 I BH n5 I BU p6 I BR n6 I CD p7 I CB n7 I CL p8 I CJ n8 I Receiver differential pair, B Channels, Lane 5 Receiver differential pair, B Channels, Lane 6 Receiver differential pair, B Channels, Lane 7 Receiver differential pair, B Channels, Lane 8 Receiver differential pair, B Channels, Lane 9 Receiver differential pair, B Channels, Lane 0 Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane 4 Receiver differential pair, B Channels, Lane 5 Receiver differential pair, A Channels, Lane 0 Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane 4 Receiver differential pair, A Channels, Lane 5 Receiver differential pair, A Channels, Lane 6 Receiver differential pair, A Channels, Lane 7 Receiver differential pair, A Channels, Lane 8 PCIe* 4.0 Retimer Supplemental Features and Standard 5

16 Table -. x6 Retimer Signal Descriptions (Sheet 4 of 6) Pin# Signal Name Signal Direction Signal Description Voltage Level CV p9 I CT n9 I DE p0 I DC n0 I DM p I DK n I DW p I DU n I EF p I ED n I EN p4 I EL n4 I EY p5 I EV n5 I M7 0 O P0 0 O W7 O AA0 O AF7 O AH0 O AN7 O AR0 O AY7 4 O BB0 4 O BG7 5 O BJ0 5 O BP7 6 O BT0 6 O CA7 7 O CC0 7 O CH7 8 O CK0 8 O CR7 9 O CU0 9 O DB7 0 O DD0 0 O DJ7 O DL0 O DT7 O DV0 O Receiver differential pair, A Channels, Lane 9 Receiver differential pair, A Channels, Lane 0 Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane 4 Receiver differential pair, A Channels, Lane 5 Transmitter differential pair, B Channels, Lane 0 Transmitter differential pair, B Channels, Lane Transmitter differential pair, B Channels, Lane Transmitter differential pair, B Channels, Lane Transmitter differential pair, B Channels, Lane 4 Transmitter differential pair, B Channels, Lane 5 Transmitter differential pair, B Channels, Lane 6 Transmitter differential pair, B Channels, Lane 7 Transmitter differential pair, B Channels, Lane 8 Transmitter differential pair, B Channels, Lane 9 Transmitter differential pair, B Channels, Lane 0 Transmitter differential pair, B Channels, Lane Transmitter differential pair, B Channels, Lane 6 PCIe* 4.0 Retimer Supplemental Features and Standard

17 Table -. x6 Retimer Signal Descriptions (Sheet 5 of 6) Pin# Signal Name Signal Direction Signal Description Voltage Level EC7 O EE0 O EK7 4 O EM0 4 O EU7 5 O EW0 5 O Transmitter differential pair, B Channels, Lane Transmitter differential pair, B Channels, Lane 4 Transmitter differential pair, B Channels, Lane 5 Reference Clock FJ6 REFCLK+ I FF8 REFCLK- I 00MHz. Reference Clock (Differential Pair) to be used in Common Clock configuration, as defined by the PCIe Base Specification PCI Express Auxiliary Signals F PERST# I Fundamental Reset; Active Low.8 V (. V tolerant) G5 CLKREQ# I Used by LPM Substates; Active Low.8 V (. V tolerant) JTAG B6 JTAG_TDI I JTAG Test Data In.8 V(. V tolerant) B9 JATG_TDO O JTAG Test Data Out; Open drain; Require pull up on the platform; Pull up voltage must be selected based on the IO voltage selected for other JTAG signals B JTAG_TMS I JTAG Test Mode Select.8 V(. V tolerant) B JTAG_TCK I JTAG Clock.8 V(. V tolerant) E8 JTAG_TRST# I JTAG Reset; Active Low.8 V(. V tolerant) System Management Bus (SMBus) B SMBCLK I/O SMBus Clock Input / Open Drain Clock Output.8 V(. V tolerant) B8 SMBDAT I/O SMBus Data Input / Open Drain Output.8 V(. V tolerant) F4 SMB_ADDR_0 I SMBus Address Bit0.8 V(. V tolerant) B SMB_ADDR_ I SMBus Address Bit.8 V(. V tolerant) B5 SMB_ADDR_/ VD_8() I SMBus Address Bit or Vendor Defined.8 V(. V tolerant) PCIe* 4.0 Retimer Supplemental Features and Standard 7

18 Table -. x6 Retimer Signal Descriptions (Sheet 6 of 6) Pin# Signal Name Signal Direction Signal Description Voltage Level EEPROM Configuration Interface FJ EE_DAT/VD_7() I/O EEPROM Interface Clock or Vendor Defined.8 V(. V tolerant) FF5 EE_CLK/VD_8() I/O EEPROM Interface Data or Vendor Defined.8 V(. V tolerant) Miscellaneous Power FJ VD_() TBD Vendor Defined Signal FF4 VD_() TBD Vendor Defined Signal FJ6 VD_() TBD Vendor Defined Signal FF8 VD_4() TBD Vendor Defined Signal FJ9 VD_5() TBD Vendor Defined Signal FF VD_6() TBD Vendor Defined Signal FJ5 VD_9() TBD Vendor Defined Signal FF7 VD_0() TBD Vendor Defined Signal FJ8 VD_() TBD Vendor Defined Signal FF0 VD_() TBD Vendor Defined Signal FJ VD_() TBD Vendor Defined Signal FF VD_4() TBD Vendor Defined Signal G VD_5() TBD Vendor Defined Signal B6 REFCLK_Out+ () O 00MHz. This pin is used for driving REFCLK_out+ E8 REFCLK_Out () O 00MHz. This pin is used for driving REFCLK_out - E RX_DET_BYP I Receiver Detection Bypass 6 pins PWR_ Power Rail.8V or.v 4 pins PWR_ Power Rail.V or.0v or 0.9V or 0.8V 5pins 0V Notes:. It is safe to route high speed Vendor Defined (VD) signals at these locations. Care must be taken to provide enough isolation. Retimer vendors are recommended to do a thorough signal integrity analysis when using any of the VD pins.. REFCLK Out, when supported, is compliant with REFCLK definition in the PCIe Base Specification... Signal Descriptions... SMBus Interface SMBCLK, SMBDAT and three address pins (SMB_ADDR_0, SMB_ADDR_, SMB_ADDR_) are assigned in the ballmap. Three address bits are required to address retimers on the SMBus in a platform configuration. Retimer vendors are allowed to take care of SMBus address needs on the platform by using only two address pins, if they can take care of additional addresses needed by the platform in a proprietary way. The retimer vendors can use the third address bit for Vendor Defined purposes in that case. Address pin SMB_ADDR_ can be used for Vendor Defined signal.. 8 PCIe* 4.0 Retimer Supplemental Features and Standard

19 ... EEPROM Interface EECLK and EEDAT signals are defined to load initial configuration from an external EEPROM. No specific interface is mentioned, giving retimer vendors freedom to use the interface of their choice. An example of the interface that can be used is IC. When this dedicated interface is not used for EEPROM load, and some other means are used to load EEPROM configuration, these pin can be used as Vendor Defined.... Miscellaneous Signals... RX_DET_BYP (PCIe_BYPASS_MODE) This signal is asserted to bypass the Receiver detection process to expedite the link training. In this mode, the retimer does not do any active determination of its Receiver impedance. It rather assumes that the receiver is present on the other end of the link. This feature can be used for soldered-down devices. The same signal when asserted, also serves to bypass the PCIe mode.... REFCLK_Out+/REFCLK_Out-... PERST#...4 CLKREQ# This is the 00 MHz reference clock as defined by the PCIe Base Specification. Some retimer devices may provide this clock output to ease clock routing complexities on the platform. Retimer devices that do not support REFCLK_Out feature are allowed to use these pins for Vendor Defined purposes. Fundamental Reset signal as defined by the PCIe Base Specification. This signal is used to support LPM Substates. Refer to the PCIe Base Specification for more details on LPM Substate support for retimers. PCIe* 4.0 Retimer Supplemental Features and Standard 9

20 EE_D AT /VD_7 EE_CLK/ VD_5 SM B _A DDR_0 RX_DET REFCLK + PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ P WR_ PWR_ REFCLK- REFCLK _Out+/V D_6 REFCLK _Out- /VD_7 SM B_A DDR_/ VD_8. x6 Retimer Ballmap (Package Side) The following figure shows the ball arrangement from the retimer package side. Note that this figure is for reference only, for actual pin number and spacing details, refer to Figure -5, x6 Retimer, Platform Side Land Pattern with Spacing Details (Top View) on page. Figure -. x6 Retimer, Package Side Pin Arrangement (Top View) CP CN CM CL CK CJ CH CG CF CE CD CC CB CA BY BW BV BU BT BR BP BN BM BL BK BJ BH BG BF BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A NC p5 p4 p p p A _PER p0 p9 p8 p7 p6 p5 p4 A _PER p p p p0 NC NC NC NC n5 n4 n n n n0 n9 n8 n7 n6 A _PER n5 n4 n n n n0 PERST# NC JTAG_T CK 4 VD_8 4 5 VD_ JTAG_T DI 5 6 VD_4 JTAG_T RST# 6 7 VD_ JTAG_T DO 7 8 VD_6 _B YP 8 9 JTAG_T MS PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ P WR_ PWR_ 4 4 SM B_A 5 VD_ DDR_ 5 6 VD_ 6 7 VD_ VD_0 8 9 VD_ SMBDAT 9 0 VD_ 0 VD_ SMBCLK VD_4 NC NC NC CLKREQ NC # NC NC 4 CP CN CM CL CK CJ CH CG CF CE CD CC CB CA BY BW BV BU BT BR BP BN BM BL BK BJ BH BG BF BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 4 Note: Refer to Figure -5, x6 Retimer, Platform Side Land Pattern with Spacing Details (Top View) on page for pitch and spacing details. Legend PWR_ PWR_ Control and VD Signals Differential TX Differential RX No Balls NC 0 PCIe* 4.0 Retimer Supplemental Features and Standard

21 EE_DAT /VD_7 EE_CLK/ VD_8 VD_5 SM B_A DDR_0 RX_DET _B YP REFCLK + PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ REFCLK- REFCL _Out+/V D_6 REFCLK _Out- /VD_7 DDR_ SM B _A DDR_ VD_8. x6 Retimer, Platform side Pin Arrangement The following figure shows the platform side pin arrangement with PCB vias. The TX and RX balls here have been swapped when compared to package side ballmap (Figure -). That is, TX lane x in package side ballmap gets mapped to RX lane x in the land pattern. Note that this figure is for reference only; for actual pin number and spacing details, refer to Figure -5, x6 Retimer, Platform Side Land Pattern with Spacing Details (Top View) on page. Figure -. x6 Retimer, Platform side Pin Arrangement (Top View) CP CN CM CL CK CJ CH CG CF CE CD CC CB CA BY BW BV BU BT BR BP BN BM BL BK BJ BH BG BF BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A NC 5 4 A _PETp A _PETp NC NC NC NC A _PETn 4 0 PERST# NC JTAG_ CK 4 5 VD_ JTAG_ DI 6 VD_4 JTAG_T RST# 7 VD_ JTAG_ DO 8 VD_6 9 JTAG_ MS 0 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ 4 5 VD_ SM B _A 6 VD_ 7 VD_9 p 5 p 4 p p p p 0 p 9 p 8 p 7 p 6 p 5 p 4 p p p p 0 8 VD_0 9 VD_ n 5 n 4 n n n n 0 n 9 n 8 n 7 n 6 n 5 n 4 n n n n 0 SMBDA 0 VD_ VD_ SMBCL VD_4 NC NC NC CLKREQ 4 NC # NC NC CP CN CM CL CK CJ CH CG CF CE CD CC CB CA BY BW BV BU BT BR BP BN BM BL BK BJ BH BG BF BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A Legend RX Via PWR_ Via PWR_ Via Via Control Signal Via PCIe* 4.0 Retimer Supplemental Features and Standard

22 .4 x6 Retimer Package-side Ball Arrangement The following figure shows the top view of x6 retimer package-side ball arrangement with pin numbers. Figure -4. x6 Retimer, Physical Ballmap on Package (Top View) PCIe* 4.0 Retimer Supplemental Features and Standard

23 .5 x6 Retimer Platform-side Land Pattern The following figure shows top view of the platform side mechanical outline drawing for x6 retimer. Dimension tolerances for ball diameter are ±0.05 mm. Figure -5. x6 Retimer, Platform Side Land Pattern with Spacing Details (Top View) Note: All dimensions are in mm and all distances are center to center..6 x8 Retimer Interface Signals Table -. x8 Retimer Signal Descriptions (Sheet of 4) Pin# Signal Name Signal Direction Signal Description Voltage Level High Speed Differential I/Os B9 0 O A0 0 O C6 O D7 O B O A4 O E O D O AB 4 O AA 4 O Transmitter differential pair, A Channels, Lane 0 Transmitter differential pair, A Channels, Lane Transmitter differential pair, A Channels, Lane Transmitter differential pair, A Channels, Lane Transmitter differential pair, A Channels, Lane 4 PCIe* 4.0 Retimer Supplemental Features and Standard

24 Table -. x8 Retimer Signal Descriptions (Sheet of 4) Pin# Signal Name Signal Direction Signal Description Voltage Level AE4 5 O AD 5 O AH 6 O AG 6 O AL4 7 O AK 7 O B5 p0 I A4 n0 I C8 p I D7 n I B p I A0 n I E p I D n I AB p4 I AA n4 I AE0 p5 I AD n5 I AH p6 I AG n6 I AL0 p7 I AK n7 I H 0 O G0 0 O L O K O P O N0 O U O T O AP 4 O AN 4 O AU0 5 O AT 5 O AP7 6 O AR8 6 O AU4 7 O AT5 7 O H 0 I G4 0 I Transmitter differential pair, A Channels, Lane 5 Transmitter differential pair, A Channels, Lane 6 Transmitter differential pair, A Channels, Lane 7 Receiver differential pair, A Channels, Lane 0 Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane 4 Receiver differential pair, A Channels, Lane 5 Receiver differential pair, A Channels, Lane 6 Receiver differential pair, A Channels, Lane 7 Transmitter differential pair, B Channels, Lane 0 Transmitter differential pair, B Channels, Lane Transmitter differential pair, B Channels, Lane Transmitter differential pair, B Channels, Lane Transmitter differential pair, B Channels, Lane 4 Transmitter differential pair B Channels, Lane 5 Transmitter differential pair, B Channels, Lane 6 Transmitter differential pair, B Channels, Lane 7 Receiver differential pair, B Channels, Lane 0 4 PCIe* 4.0 Retimer Supplemental Features and Standard

25 Table -. x8 Retimer Signal Descriptions (Sheet of 4) Pin# Signal Name Signal Direction Signal Description Voltage Level L I K I P I N4 I U I T I AP 4 I AN 4 I AU4 5 I AT 5 I AP7 6 I AR6 6 I AU0 7 I AT9 7 I Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane 4 Receiver differential pair, B Channels, Lane 5 Receiver differential pair, B Channels, Lane 6 Receiver differential pair, B Channels, Lane 7 Reference Clock Y5 REFCLK+ I 00 MHz. Reference Clock (Differential Pair) to be used in Common Clock configuration, as V5 REFCLK- I defined by the PCIe Base Specification PCI Express Auxiliary Signals JTAG Y PERST# I Fundamental Reset; Active Low.8 V (. V tolerant) B CLKREQ# I Used by LPM Substates; Active Low.8 V (. V tolerant) AC8 JTAG_TDI I JTAG Test Data In.8 V (. V tolerant) L8 JATG_TDO O JTAG Test Data Out; Open drain; Require pull up on the platform; Pull up voltage must be selected based on the IO voltage selected for other JTAG signals E6 JTAG_TMS I JTAG Test Mode Select.8 V (. V tolerant) AG8 JTAG_TCK I JTAG Clock.8 V (. V tolerant) R8 JTAG_TRST# I JTAG Reset; Active Low.8 V (. V tolerant) System Management Bus (SMBus) AC6 SMBCLK I/O SMBus Clock Input / Open Drain Clock Output.8 V (. V tolerant) AG6 SMBDAT I/O SMBus Data Input / Open Drain Output.8 V (. V tolerant) R6 SMB_ADDR_0 I SMBus Address Bit 0.8 V (. V tolerant) L6 SMB_ADDR_ I SMBus Address Bit.8 V (. V tolerant) V SMB_ADDR_/ VD_5 I SMBus Address Bit or Vendor Defined.8 V (. V tolerant) EEPROM Configuration Interface AP EE_DAT/VD_5() I/O EEPROM Interface Clock or Vendor Defined.8 V (. V tolerant) AP EE_CLK/VD_6() I/O EEPROM Interface Data or Vendor Defined.8 V (. V tolerant) Miscellaneous AT VD_ TBD Vendor Defined Signal PCIe* 4.0 Retimer Supplemental Features and Standard 5

26 Table -. x8 Retimer Signal Descriptions (Sheet 4 of 4) Pin# Signal Name Signal Direction Signal Description Voltage Level Power W VD_ TBD Vendor Defined Signal B VD_ TBD Vendor Defined Signal AU VD_4 TBD Vendor Defined Signal D VD_7() TBD Vendor Defined Signal D VD_8() TBD Vendor Defined Signal A VD_9 TBD Vendor Defined Signal W VD_0 TBD Vendor Defined Signal AT VD_ TBD Vendor Defined Signal V VD_ TBD Vendor Defined Signal B VD_ TBD Vendor Defined Signal AT REFCLK_Out+ () O 00MHz. This pin is used for driving REFCLK_out+ Y9 REFCLK_Out () O 00MHz. This pin is used for driving REFCLK_out - V9 RX_DET_BYP I Receiver Detection Bypass 6 pins PWR_ Power Rail.8V or.v 48 pins PWR_ Power Rail.V or.0v or 0.9V or 0.8V 75pins 0V Notes:. It is safe to route high speed Vendor Defined signals at these locations. Rest VD pins are recommended to be used for static/ quasi static (low slew rate) signals. Routing high frequency signals on these may impose crosstalk on high-speed signals. Retimer vendors are recommended to do a thorough signal integrity analysis when using any of the VD pins.. REFCLK Out, when supported is compliant with REFCLK definition in the PCIe Base Specification..6. Signal Descriptions.6.. SMBus Interface Refer to Section..., SMBus Interface on page EEPROM Interface Refer to Section..., EEPROM Interface on page Miscellaneous Signals Refer to Section..., Miscellaneous Signals on page 9. 6 PCIe* 4.0 Retimer Supplemental Features and Standard

27 .7 x8 Retimer Ballmap Figure -6. x8 Retimer, Package-side Pin Arrangement (Top View) AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A VD_ VD_ PERST# A _PETn 6 A _PETn 4 VD_ REFCL K+ REFCL K SMBDA T SMBCL K SMB_A DDR_0 SMB_A DDR_ A _PETp PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ 0 0 EE_CLK /VD_5 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ VD_7 CLKRE Q# VD_4 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ VD_9 RX_DET _BYP EE_DA T/VD_6 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ VD_8 4 7 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ n PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ p0 5 6 JTAG_ TMS PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ n JTAG_ TCK JTAG_ TDI JTAG_ TRST# JTAG_ TDO p 8 9 REFCLK_ OUT+/VD _0 REFCLK_ OUT- /VD_ p7 p5 0 n 0 5 n7 n5 0 p 4 n6 n4 VD_ A _PER p VD_ 4 A _PER p6 p4 SM B_AD DR_/VD _4 n VD_5 AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A Legend PWR_ PWR_ Control Signals Differential TX Differential RX No Balls PCIe* 4.0 Retimer Supplemental Features and Standard 7

28 .8 X8 Retimer, Platform-side Land Pattern The following figure shows the platform side land pattern. The TX and RX balls have been swapped when compared to package side ballmap. i.e. TX lane x in package side ballmap gets mapped to RX lane x in the land pattern. Figure -7. x8 Retimer, Platform-side Pin Arrangement (Top View) AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A A _PER VD_ VD_ PERST# 4 p6 p4 n 4 n6 n4 VD_ A _PER p 5 n7 n5 0 p 4 5 p7 p5 0 n 4 5 REFCL K+ REFCL K SMBDA T SMBCL K SMB_A DDR_0 SMB_A DDR_ p PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ n PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ p PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ n0 0 EE_CLK /VD_5 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ VD_7 CLKRE Q# VD_4 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ VD_9 RX_DET _BYP EE_DA T/VD_6 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ VD_8 4 7 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ JTAG_ TMS PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ 7 JTAG_ JTAG_ 8 6 TCK TDI REFCL REFCL K_OUT K_OUT- +/VD /VD JTAG_ TRST# JTAG_ TDO A _PETp A _PETn 6 A _PETn 4 VD_ VD_ SMB_A DDR_/ VD 4 VD_5 AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A Legend PWR_ Via PWR_ Via Via Control Signal Via 8 PCIe* 4.0 Retimer Supplemental Features and Standard

29 .9 x8 Retimer Package-side Ballmap Figure -8. x8 Retimer, Physical Ballmap on Package (Top View) Note: All dimensions are in mm and all distances are center to center. PCIe* 4.0 Retimer Supplemental Features and Standard 9

30 .0 x8 Retimer Platform-side Land Pattern Figure -9. x8 Retimer, Platform-side Land Pattern with Spacing Details (Top View) Note: All dimensions are in mm and all distances are center to center.. x4 Retimer Interface Signals Table -. x4 Retimer Signal Descriptions (Sheet of ) Pin# Signal Name Signal Direction Signal Description Voltage Level High Speed Differential I/Os A 0 O A4 0 O C O B O F O E O Transmitter differential pair, A Channels, Lane 0 Transmitter differential pair, A Channels, Lane Transmitter differential pair, A Channels, Lane 0 PCIe* 4.0 Retimer Supplemental Features and Standard

31 Table -. x4 Retimer Signal Descriptions (Sheet of ) Pin# Signal Name Signal Direction Signal Description Voltage Level J O H O A8 p0 I A7 n0 I C0 p I B0 n I F0 p I E0 n I J0 p I H0 n I M0 0 O l0 0 O R0 O P0 O V0 O U0 O W7 O W8 O M 0 I L 0 I R I P I V I U I W4 I W I Transmitter differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane 0 Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane Receiver differential pair, A Channels, Lane Transmitter differential pair, B Channels, Lane 0 Transmitter differential pair, B Channels, Lane Transmitter differential pair, B Channels, Lane Transmitter differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane 0 Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane Receiver differential pair, B Channels, Lane Reference Clock C5 REFCLK+ I 00MHz. Reference Clock (Differential Pair) to be used in Common Clock configuration, as C6 REFCLK- I defined by the PCIe Base Specification PCI Express Auxiliary Signals JTAG A PERST# I Fundamental Reset; Active Low.8 V (. V tolerant) A9 CLKREQ# I Used by LPM Substates; Active Low.8 V (. V tolerant) U JTAG_TDI I JTAG Test Data In.8 V (. V tolerant) C JATG_TDO O JTAG Test Data Out; Open drain; Require pull up on the platform; Pull up voltage must be selected based on the IO voltage selected for other JTAG signals N JTAG_TMS I JTAG Test Mode Select.8 V (. V tolerant) K JTAG_TCK I JTAG Clock.8 V (. V tolerant) J JTAG_TRST# I JTAG Reset; Active Low.8 V (. V tolerant) PCIe* 4.0 Retimer Supplemental Features and Standard

32 Table -. x4 Retimer Signal Descriptions (Sheet of ) Pin# Signal Name Signal Direction Signal Description Voltage Level System Management Bus (SMBus) G8 SMBCLK I/O SMBus Clock Input / Open Drain Clock Output.8 V (. V tolerant) K8 SMBDAT I/O SMBus Data Input / Open Drain Output.8 V (. V tolerant) W5 SMB_ADDR_0 I SMBus Address Bit 0.8 V (. V tolerant) W6 SMB_ADDR_ I SMBus Address Bit.8 V (. V tolerant) W9 SMB_ADDR_/ VD_ I SMBus Address Bit or Vendor Defined.8 V (. V tolerant) EEPROM Configuration Interface U8 EE_DAT/VD_9 () I/O EEPROM Interface Clock or Vendor Defined.8 V(. V tolerant) N8 EE_CLK/VD_0 () I/O EEPROM Interface Data or Vendor Defined.8 V(. V tolerant) Miscellaneous Power W VD_ TBD Vendor Defined Signal W VD_ TBD Vendor Defined Signal W0 VD_ TBD Vendor Defined Signal A VD_4 TBD Vendor Defined Signal U5 U6 VD_5 () / REFCLK_Out+ () VD_6 () / REFCLK_Out- () TBD/O TBD/O If the retimer supports driving REFCLK out, this pin is used for REFCLK_out+; else the pin can be used as Vendor Defined Signal If the retimer supports driving REFCLK out, this pin is used for REFCLK_Out-; else the pin can be used as Vendor Defined Signal A5 VD_5 TBD Vendor Defined Signal A0 VD_6 TBD Vendor Defined Signal C8 VD_9 TBD Vendor Defined Signal A6 RX_DET_BYP I Receiver Detection Bypass 5 pins PWR_ Power Rail. V or.8 V 9 pins PWR_ Power Rail. V or.0 V or 0.9 V or 0.8 V 54 pins 0 V Notes:. It is safe to route high speed Vendor Defined signals at these locations. Rest VD pins are recommended to be used for static/ quasi static (low slew rate) signals. Routing high frequency signals on these may impose crosstalk on high-speed signals. Retimer vendors are recommended to do a thorough signal integrity analysis when using any of the VD pins.. REFCLK Out, when supported is compliant with REFCLK definition in the PCIe Base Specification... Signal Descriptions... SMBus Interface Refer to Section..., SMBus Interface on page EEPROM Interface Refer to Section..., EEPROM Interface on page 9 PCIe* 4.0 Retimer Supplemental Features and Standard

33 ... Miscellaneous Signals Refer to Section..., Miscellaneous Signals on page 9.. x4 Retimer Ballmap Figure -0. x4 Retimer, Package-side Pin Arrangement (Top View) W V U T R P N M L K J H G F E D C B A VD_ 0 0 VD_4 VD_ PERST# JTAG_T DI PWR_ PWR_ PWR_ JTAG_T MS PWR_ PWR_ JTAG_T CK PWR_ PWR_ JTAG_T RST# PWR_ PWR_ PWR_ JTAG_T DO 0 4 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ SM B_A DDR_0 SM B_A DDR_ REFCLK _OUT+/V D_5 REFCLK _OUT- /VD_6 REFCLK + REFCLK- VD_7 5 RX_DET _BYP 6 7 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ n EE_DAT /VD_9 PWR_ PWR_ PWR_ EE_CLK/ VD_0 PWR_ PWR_ SM BDA T PWR_ PWR_ SM BCL K PWR_ PWR_ PWR_ VD_ p SM B_A DDR_/ VD_ CLKREQ # 9 0 VD_ 0 0 p n p n p n VD_8 0 W V U T R P N M L K J H G F E D C B A Legend PWR_ PWR_ Control Signals Differential TX Differential RX No Balls PCIe* 4.0 Retimer Supplemental Features and Standard

34 . x4 Retimer, Platform side Land Pattern The following figure shows the platform side land pattern. The TX and RX balls have been swapped when compared to package side ballmap. i.e. "TX lane x" in package side ballmap gets mapped to RX lane x in the land pattern. Figure -. x4 Retimer, Platform-side Land Pattern (Top View) W V U T R P N M L K J H G F E D C B A VD_ 0 0 p n p n p n VD_4 VD_ PERST# JTAG_T DI PWR_ PWR_ PWR_ JTAG_T MS PWR_ PWR_ JTAG_T CK PWR_ PWR_ JTAG_T RST# PWR_ PWR_ PWR_ JTAG_T DO p 0 4 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ n SM B_A DDR_0 SM B_A DDR_ REFCLK _OUT+/V D_5 REFCLK _OUT- /VD_6 REFCLK + REFCLK- VD_7 5 RX_DET _BYP 6 7 PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ EE_DAT /VD_9 PWR_ PWR_ PWR_ EE_CLK/ VD_0 PWR_ PWR_ SM BDA T PWR_ PWR_ SM BCL K PWR_ PWR_ PWR_ VD_ SM B_A DDR_/ VD_ CLKREQ # 9 0 VD_ 0 0 VD_8 0 W V U T R P N M L K J H G F E D C B A Legend PWR_ Via PWR_ Via Via Control Signal Via 4 PCIe* 4.0 Retimer Supplemental Features and Standard

35 .4 x4 Retimer, Physical Ballmap (Package Side) Figure -. x4 Retimer, Physical Ballmap on Package (Top View) Note: All dimensions are in mm and all distances are center to center. PCIe* 4.0 Retimer Supplemental Features and Standard 5

36 .5 X4 Retimer Platform-side Land Pattern Figure -. x4 Retimer, Platform-side Land Pattern with Spacing Details (Top View) 6 PCIe* 4.0 Retimer Supplemental Features and Standard

37 4 Electrical Characteristics Two power supplies are supported, PWR_ and PWR_. PWR_ supports. V or.8 V. PWR_ supports one of (0.8 V, 0.9 V,.0 V,. V). Actual voltage is to be decided between retimer vendor and the system vendor. PWR_ rail is intended for control signals and sideband signals, whereas PWR_ is intended for high-speed signaling. Table 4- lists power distribution for the two rails (PWR_ and PWR_) for x4, x8 and x6 configurations. 4. Absolute Maximum Ratings The following table lists the absolute maximum supply voltage ratings Table 4-. Absolute Maximum Voltage Ratings Symbol Parameter Min Max Units Notes. V. V Supply Voltage.8.6 V.8 V.8 V Supply Voltage.7.9 V. V. V Supply Voltage.06.7 V.0 V.0 V Supply Voltage V 0.9 V 0.9 V Supply Voltage V 0.8 V 0.8 V Supply Voltage V Note:. No specific Power-On and Power-Off sequence is required for various supply voltage rails 4. Power Consumption The following table lists power consumption values under maximum operating conditions. Maximum power is consumed while all the lanes are operating at 6 GT/s with full swing on Transmitter. Table 4-. Recommended Absolute Maximum Power Ratings Power_ Power_ Unit x W x W x W PCIe* 4.0 Retimer Supplemental Features and Standard 7

38 4. Power Supply Decoupling Due to the low level signaling of the PCI Express interface, it is strongly recommended that sufficient decoupling of all power supplies be provided. This is recommended to ensure that power supply noise does not interfere with the recovery of data from a remote upstream PCI Express device. Some basic guidelines to help ensure a quiet power supply are provided below. Note: The following are guidelines only. It is the responsibility of the retimer designer and the platform designer to properly test the design to ensure that retimer circuitry does not create excessive noise on power supply or ground signals at the retimer package balls. For PWR_ rail, a bulk decoupling capacitor of value x470uf (Aluminum) and xuf (0805) is recommended near VR on the platform. For PWR_ rail, x0 uf (060) capacitor is recommended at top cavity on the platform. For PWR_ rail, x0 uf (060) capacitor is recommended at bottom cavity on the platform. For PWR_ rail, a bulk decoupling capacitor of value x470 uf (Aluminum) and x uf (0805) is recommended near VR on the platform. For PWR_ rail, x0 uf (060) capacitors and x0 uf (0805) capacitor is recommended at the top cavity on the platform. For PWR_ rail, x uf (0805) capacitor is recommended at the bottom cavity on the platform. It is recommended that the retimer vendor incorporate the decoupling caps in the package or in the die as needed to minimize noise at the package balls. 4.4 Retimer Latency Maximum Latency (Refer to Base Specification) specification for PCIe Gen-4 retimers is 64 ns to 9 ns depending on clocking architecture and maximum payload size. Some applications may need significantly lower latency (less than 0 ns). OEMs are recommended to work with retimer vendors for this low latency use case. 4.5 Package Thermal Considerations Parameter Description Value Units T J(max) Junction temperature 5 C T A(max) Ambient temperature 85 C 8 PCIe* 4.0 Retimer Supplemental Features and Standard

39 5 SMBus and EEPROM It is assumed that each retimer has a dedicated EEPROM behind it from where the retimer loads its configuration data upon power-up. Dedicated EEPROM interface allows retimer to use fixed address to access the EEPROM. It is recommended that the retimer load most of the configuration through EEPROM. Once the EEPROM configuration is loaded, any additional configurations needed from the platform side is done using SMBus interface. Retimer pinout supports SMBus address pins allowing up to 8 addressable devices on the bus. If more than 8 devices (and hence addresses) are needed, some kind of SMBus multiplexing is used on the platform side. Minimizing the configurations through SMBus in applications where boot time is minimized is recommended. PCIe* 4.0 Retimer Supplemental Features and Standard 9

40 40 PCIe* 4.0 Retimer Supplemental Features and Standard

41 6 Register Configuration 6. Global Parameter Register Bit Location Register Description Attributes :0 6:4 7 Max Data Rate 000: Rsvd 00:.5 G (Def) 00: 5.0 G 0: 8.0 G 00: 6 G 0: Rsvd 0: Rsvd SRIS Enable 0: Common Clock (Def) : SRIS SRIS Link Payload Size (valid when Bit=) 000: 8 00: 56 00: 5 0: 04 00: 048 0: 4096 (Def) 0: Rsvd : Rsvd Port Orientation Method 0:Static :Dynamic (Def) RW RW RW RW PCIe* 4.0 Retimer Supplemental Features and Standard 4

42 6. Global Parameter Register Bit Location Register Description Attributes 4:0 Port Link Subdivision (Bifurcation) 00000: x6 (Def) 0000: x8 0000: x4 000: x8 x8 0000: x4 x4 000: x x 000: x4 x4 x4 x4 00: x x x x x x x x 0000: x8 x4 x4 000: x4 x x 000: x8 x4 x x 00: x x x4 000: x4 x4 x8 00: x x4 x 00: x xx4 x8 0-: Reserved RW 7:5 Reserved R0 4 PCIe* 4.0 Retimer Supplemental Features and Standard

43 6. Physical Pseudo Port Parameter Register Bit Location Register Description Attributes 0 : 4 5 Port Orientation (valid when Port Orientation Method in Global Parameter Register = 0) 0:Upstream : Downstream (Def) Selectable De-emphasis Port (valid when Port Orientation = and Max Data Rate = 5G in Global Parameter Register) 0:-.5 db (Def) :-6.0 db RX Impedance Control Port 00: Static- On 0: Static- Off 0: Dynamic (Def) : Rsvd Port TX Compliance Disable : Disable 0: Enable (Def) Pseudo Port Slave Loopback : Enable 0: Disable (Def) R0 R0 RW RW RW 7:6 Reserved R0 PCIe* 4.0 Retimer Supplemental Features and Standard 4

44 6.4 Physical Pseudo Port Parameter Register Bit Location Register Description Attributes :0 7:4 Downstream Pseudo Port, 8 GT/s TX Preset 0000: P0 000: P 000: P 00: P 000: P4 00: P5 00: P6 0: P7 (Def) 000: P8 00: P9 00: P0 0 to : Rsvd Downstream Pseudo Port 8 GT Requested TX Preset 0000: P0 000: P 000: P 00: P 000: P4 00: P5 00: P6 0: P7 (Def) 000: P8 00: P9 00: P0 0 to : Rsvd RW RW 44 PCIe* 4.0 Retimer Supplemental Features and Standard

45 6.5 Physical Pseudo Port Parameter Register Bit Location Register Description Attributes :0 7:4 Downstream Pseudo Port, 6 GT/s TX Preset: 0000: P0 000: P 000: P 00: P 000: P4 00: P5 00: P6 0: P7 (Def) 000: P8 00: P9 00: P0 0 to : Rsvd Downstream Pseudo Port 6 GT Requested TX Preset: 0000: P0 000: P 000: P 00: P 000: P4 00: P5 00: P6 0: P7 (Def) 000: P8 00: P9 00: P0 0 to : Rsvd RW RW PCIe* 4.0 Retimer Supplemental Features and Standard 45

46 6.6 Physical Pseudo Port Parameter Register 4 Bit Location Register Description Attributes 5:0 8G Cursor Coefficient Pseudo Port Coefficient to Coefficient 64 RW 7:6 Reserved RO 6.7 Physical Pseudo Port Parameter Register 5 Bit Location Register Description Attributes 5:0 8G Pre-cursor Coefficient Pseudo Port Coefficient to Coefficient 64 RW 7:6 Reserved RO 46 PCIe* 4.0 Retimer Supplemental Features and Standard

47 6.8 Physical Pseudo Port Parameter Register 6 Bit Location Register Description Attributes 5:0 8G Post-cursor Coefficient Pseudo Port Coefficient to Coefficient 64 RW 7:6 Reserved RO 6.9 Physical Pseudo Port Parameter Register 7 Bit Location Register Description Attributes 5:0 6G Cursor Coefficient Pseudo Port Coefficient to Coefficient 64 RW 7:6 Reserved RO 6.0 Physical Pseudo Port Parameter Register 8 Bit Location Register Description Attributes 5:0 6G Pre-cursor Coefficient Pseudo Port Coefficient to Coefficient 64 RW 7:6 Reserved RO PCIe* 4.0 Retimer Supplemental Features and Standard 47

48 6. Physical Pseudo Port Parameter Register 9 Bit Location Register Description Attributes 5:0 6G Post-cursor Coefficient Pseudo Port Coefficient to Coefficient 64 RW 7:6 Reserved RO 6. Physical Pseudo Port Parameter Register Bit Location Register Description Attributes 0 : 4 5 Port Orientation (valid when Port Orientation Method in Global Parameter Register = 0) 0:Upstream (Def) :Downstream Selectable De-emphasis Port 0:-.5 db (Def) :-6.0 db RX Impedance Control Port 00: Static- On 0: Static- Off 0: Dynamic (Def) : Rsvd Port TX Compliance Disable : Disable 0: Enable (Def) Pseudo Port Slave Loopback : Enable 0: Disable (Def) R0 R0 RW RW RW 7:6 Reserved R0 48 PCIe* 4.0 Retimer Supplemental Features and Standard

49 6. Physical Pseudo Port Parameter Register Bit Location Register Description Attributes :0 7:4 Downstream Pseudo Port, 8 GT/s TX Preset 0000: P0 000: P 000: P 00: P 000: P4 00: P5 00: P6 0: P7 (Def) 000: P8 00: P9 00: P0 0 to : Rsvd Downstream Pseudo Port 8GT Requested TX Preset 0000: P0 000: P 000: P 00: P 000: P4 00: P5 00: P6 0: P7 (Def) 000: P8 00: P9 00: P0 0 to : Rsvd RW RW PCIe* 4.0 Retimer Supplemental Features and Standard 49

50 6.4 Physical Pseudo Port Parameter Register Bit Location Register Description Attributes :0 7:4 Downstream Pseudo Port 6 GT/s TX Preset 0000: P0 000: P 000: P 00: P 000: P4 00: P5 00: P6 0: P7 (Def) 000: P8 00: P9 00: P0 0 to : Rsvd Downstream Pseudo Port 6 GT Requested TX Preset 0000: P0 000: P 000: P 00: P 000: P4 00: P5 00: P6 0: P7 (Def) 000: P8 00: P9 00: P0 0 to : Rsvd RW RW 50 PCIe* 4.0 Retimer Supplemental Features and Standard

51 6.5 Physical Pseudo Port Parameter Register 4 Bit Location Register Description Attributes 5:0 8G Cursor Coefficient Pseudo Port Coefficient to Coefficient 64 RW 7:6 Reserved RO 6.6 Physical Pseudo Port Parameter Register 5 Bit Location Register Description Attributes 5:0 8G Pre-cursor Coefficient Pseudo Port Coefficient to Coefficient 64 RW 7:6 Reserved RO PCIe* 4.0 Retimer Supplemental Features and Standard 5

52 6.7 Physical Pseudo Port Parameter Register 6 Bit Location Register Description Attributes 5:0 8G Post-cursor Coefficient Pseudo Port Coefficient to Coefficient 64 RW 7:6 Reserved RO 6.8 Physical Pseudo Port Parameter Register 7 Bit Location Register Description Attributes 5:0 6G Cursor Coefficient Pseudo Port Coefficient to Coefficient 64 RW 7:6 Reserved RO 5 PCIe* 4.0 Retimer Supplemental Features and Standard