Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. Ajay K. Verma and Paolo Ienne. csda

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1 Improvig XOR-Domited Circuits y Exploitig Depedecies etwee Operds Ajy K. Verm d Polo Iee csd Processor Architecture Lortory LAP & Cetre for Advced Digitl Systems CSDA Ecole Polytechique Fédérle de Luse EPFL

2 Logic Sythesis: Limited Depedecy Exploittio Logic sythesis tools re extremely good t optimizig the Boole expressios cotiig AND, OR d NOT gtes. c c c I cse of XOR gte either expd the XOR gte i terms of AND d OR gte, or replce the XOR expressio y ew vrile. Expdig XOR gtes might icrese the expressio size expoetilly, d the expsio cot e restored due to shortcomigs of lgeric fctorig. Oly depedecies mog the operds of AND d OR gtes re utilized.

3 Multiplier: XOR Gtes with Correlted Operds c

4 4 Multiplier: XOR Gtes with Correlted Operds Both its cot e true Simulteously.

5 5 Outlie Relted work. Prolem formultio. Bsic Ide. Expdig XOR gtes selectively. Alysis d improvemet of sic ide. Brodeig of selectio criteri. Results. Coclusios.

6 6 Relted Work Optimiztio of geerl XOR-domited circuits. Optimiztio of Reed-Muller form [Mishcheko, ] -SPP form optimiztio [Berscoi6] BDD-sed logic optimiztio [Sso9, Yg, ] Optimiztio of colum compressors. Crry-sve dditio [Wllce64] Optimiztio usig vrious size couters [Sog9] Proper schedulig of couters TGA [Oklodzij96, Stellig98, ]

7 7 Why Not Expd All XOR s Why Not Expd All XOR s Q P R Q P 4 4 Before expsio :.7 s 8. μm After expsio :.6 s 46.9 μm Before expsio :. s 58.8 μm After expsio :.7 s. μm Selective Expsio of XOR s is the key. Q P R Q P Q P PQ

8 8 Prolem Sttemet Give circuit cosistig of AND, OR, NOT, d XOR gtes, fid list of XOR gtes which should e expded to chieve smllest criticl pth dely fter logic sythesis. Correltio fctor: XOR gtes with sufficiet correltio etwee its operds must e expded i order to reduce dely.

9 9 Selective Expsio AB A B A B Extremely correlted A B A B AB Smll expressio: A expressio tht c e computed quickly. XOR expsio: A B AB A B operds Reltive sizes of AB d AB re good mesure of correltio etwee A d B.

10 Selective Expsio Cotd. Selective Expsio Cotd. PQ Q P R Q P Q P R Q P 4 4 Before expsio :.7 s 8. μm After expsio :.6 s 46.9 μm Before expsio :. s 58.8 μm After expsio :.7 s. μm 4 4 i i j j j j i i PQ Q P Quickly computle compred to P d Q Slow computtio compred to P d Q Expd Do ot expd

11 Criteri for XOR Expsio isexpsiouseful operd A, operd B { mi D AB, DA B ε ; // correltio fctor. mx D, D AR D AR D A D D B AB A B Δ ; // re pelty. A B // correltio etwee the operds must e sigifict s well s // expsio should ot hve huge re overhed. if ε < ε threshold or Δ > Δ threshold retur flse; // re pelty per uit correltio must e smll. if Δ / ε > κ retur flse; } retur true;

12 Correltio etwee XOR-Operds Operds d Rest of the Fuctio C Be Useful Locl correltio: correltio etwee the operds of XOR. A B A B AB Glol correltio: correltio etwee the rest of the expressio d the operds of XOR. A B C AB C A B C A B C A B C AB C

13 Glol Correltio Exmple Glol Correltio Exmple... > > > > B A... > > > > B A... > B A... > B A Comprtor fuctio crry A B crry A - B Glol correltio coverts user friedly implemettio ito sythesis friedly implemettio.

14 4 Overll Algorithm The expressio tree is optimized itertively y expdig XOR gtes sed o locl d glol correltio criteri. If there re more th XOR gtes which stisfy the expsio criteri, proper orderig of expsio is decided usig greedy heuristic. I order to mesure locl d glol correltio, estimtor fuctio is used to estimte the dely d re vlues.

15 5 Experimetl Setup Iput Circuit e.g., Prtil Product Arry Commercil Optimiztios BOA Stte of the Art Three Greedy Approch Selective Expsio Algorithmiclly Logic sythesis Artis Stdrd Cells UMC CMOS Techology.µm

16 6 Results ADPCM Decoder Commercil Optimiztios BOA Selective Expsio 6556 μm.6 s 694 μm.9 s 8 x 8-it Multiplier DesigWre 4488 μm.6 s Three Greedy Approch TGA 5996 μm.8 s Selective Expsio 76 μm. s Costt Multiplictio A x 7 A x μm.85 s A A 4A 55 μm.7 s 8A - A 94 μm.56 s Selective Expsio A A 4A s iput 8 μm.5 s Selective Expsio 8A A s iput 8 μm.5 s 5-it Comprtor Commercil Optimiztios Selective Expsio 55 μm.4 s 466 μm. s

17 7 Results Cotd. 8x8-it Multiplier: Dely Compriso times lrge compred to Selective Expsio

18 Approprite choice of Prmeters.,., ε threshold, Δ threshold, κ.,.,.5,.,.,.4,.,.4,.5,.,.,.,.5,.4,.5,.4, Most pproprite choice of prmeters 8 Dely d hrdwre re vlues for differet implemettios of 8 x 8-it multiplier geerted y Selective Expsio for differet vlues of ε threshold, Δ threshold, κ.

19 9 Results Cotd. Results Cotd. p p p p p p p p p

20 Results Cotd. Optimiztios sed o simple depedecy Locl correltio Glol correltio Optimum implemettio

21 Coclusio We hve show tht logic sythesis escpes certi kid of optimiztios o XOR-domited circuits. We preset lgorithm which works s frot ed to logic sythesis tool d trsforms give circuit ito sythesis friedly circuit. Selective Expsio improves the speed of some rithmetic circuits such s 8 x 8-it multiplier y % over stte of rt techiques.

Similar idea to multiplication in N, C. Divide and conquer approach provides unexpected improvements. Naïve matrix multiplication

Similar idea to multiplication in N, C. Divide and conquer approach provides unexpected improvements. Naïve matrix multiplication Next. Covered bsics of simple desig techique (Divided-coquer) Ch. of the text.. Next, Strsse s lgorithm. Lter: more desig d coquer lgorithms: MergeSort. Solvig recurreces d the Mster Theorem. Similr ide