A study on scheduling algorithm s for high2speed switching networks ba sed on input2queu ing
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1 3 3 Vol CAA I Transactions on Intelligent System s Jun. 2008,,,, (, ) :,.,. VOQ,,,,,.,,. : ; ;; : TP18 : A: (2008) A study on scheduling algorithm s for high2speed switching networks ba sed on input2queu ing ZHAG Chong2yang, SHE J in2yuan, L IU Run2jie, ZHAG W en2ying, MU W ei2xin ( Institute of Information Engineering, Zhengzhou University, Zhengzhou , China) Abstract: Most high2speed sw itching networks adop t a sw itching fabric w ith fixed2length cells, and their perform2 ance depends heavily upon queuing strategies and the cell scheduling algorithm. Only when the input2queuing strat2 egy is combined with a p roper switching algorithm can throughput and time delay for the switching fabric be op ti2 m ized. This paper mainly discusses virtual output queuing (VOQ ) 2based algorithm s, among them the m aximum num ber matching algorithm, the m axim um weight matching algorithm, the stable combination m atching algorithm, and the Hopfield neural network ( H ) scheduling algorithm. The m echanism s, perform ance and imp lementation2 al comp lexity of these algorithm s are compared and analyzed. The working modes of distributed and centralized scheduling algorithm s are analyzed. Finally, from the findings in our research, it is concluded that the H algo2 rithm can realize other algorithm s by defining a p riority function. Keywords: input2queuing; virtual output queuing; bipartite graph matching; scheduling algorithm, ( head of line, HOL),,.,( input2queued, IQ ) ( output2queued, OQ ) ( combined input/output2queued, C IOQ ).,. F IFO ( ),, : :( ),. :. E2mail: jyshen@ zzu. edu. cn [ 1 ]. ( virtual of queuing, VOQ),,100% [ 223 ]., Crossbar +VOQ, Tiny2Tera [ 4 ] Cisco GSR 12000IP [ 5 ]. 1,,,., 100%.
2 266 3 ( bipartite graph matching). 1 GM Fig. 1B ipartite graph G and its matching graphm 1, G = [V, E ], V, 2 :, ; E,,W ij. :P IM isl IPW ij = 01, Q ij ; ilqfiocf, W ij Q ij. G M E, M 2.,,. (maximum size matching, MSM ) [ 627 ], (maximum weight matching,mwm ) [ 8211 ], [ 12 ],. : [ 10 ] MSM 1,, 1,0. [ 9 ], 100%,,.,MSM, P IM ( parallel iterative matching) [ 2, 6 ], isl IP ( iterative round robin matching with SL IP) [ 627 ]. P IM,. 3: 1) (Request) : ; 2) ( Grant) :, ; 3) (Accep t) :,., ( ). P IM 63%,100%. P IM, 16 16,P IM, isl IP 3., 2,, Grant,,3, Grant1 ( ) ; 3,,, Accep t 1. P IM,,,. isl IP2 :,,. isl IPP IM. 1. 2,,, 1.,,100%. MWM : ( iterative long queue first, ilqf) ( iterative old cell first, iocf) [ 9211 ] ( iterative long port first, ilpf) [ 3, 6, ]. ilqflqf, 3, W ij ( n ) L ij ( n).,2b, b L max,2bl max. ilqf. iocf OCF, W ij ( n)t ij ( n). iocf,, T ij ( n)
3 3,: 267. iocfilqf. ilpflpf, W ij ( n) = R i ( n) + C j ( n), L ij ( n) > 0, 0, J ij ( n) = 0. : L ij ( n) n Q ij. R ij ( n) = L ij ( n), i n ; C ij ( n) = L ij ( n), j, ilpf. ilpf2: 1 ; 2,,., 2,. 1MSM MWM Table1 The com prehen sive com par ison of M SM and MWM a lgor ithm s % MSM /1 O ( 2. 5 ) - P IM /1 O ( 3 log ) - isl IP /1 O ( i3 3 log ) - MWM 100 W ij O ( 33 log ) + ilqf 100 L ij O ( i3 b3 log ) + iocf 100 T ij O ( i3 b3 log ) + ilpf 100 R i + C j O ( 2 ) + MWM 2,2,. MWM isl IP [ 12 ] ( stable marriage matching) Gale Shap ley, GSA ( Gale2Shap ley algorithm), GSA.,,. MUCFA (most urgent cell first algorithm) [ 13 ] GSA. j Q ij ( urgent value)i. F IFO2OQ,. i. JPM ( joined p referred matching) [ 14 ] CCF ( critical cell first) [ 15 ],. MUCFA, JPMCCF. LOOFA ( lowest output occupancy first algo2 rithm ) [ 16 ] CCF,, LOOFA. 2 Table2The com prehen sive com par ison of GSA s MUCFA 4 O ( 2 ) JPM 2 O ( 2 ) CCF 2 O ( 2 ) LOOFA 2 O ( 2 ) 2.,,, : 1),, ; 2),, ; 3), ; 4), [ 17 ]. 1. 4, H ( hopfield neural network),h [ ]. H, VOQ,. H,( i, j)1,,,0,.
4 268 3 V = [1 + exp ( - gu ) ] - 1. : U, V, g., H : 1) ; 2); 3) ; 4 ). H: E = A 2 ( l ij - B 2 C q =1 p =1, pi q =1 P (Q ij ) V ij V iq ) 2 + H ij, pq V ij V pq - + D V ij (1 - V ij ). : A B CD ; V ij ( i, j) ; I ij ( i, j), ( i, j),1,0; H ij, pq 2 ( i, j)( p, q),2, 1,0; P (Q ij ). de / dt0,,. [ 20 ],,. CMOS VLSI H 100 ns [ 21 ],. 2 MSM MWM,,,. P IM,.,,,. 1 2.,,,,.,. CMOS VL2 SI,., ( ) ; 13,,,, ;2, ;. P (Q ij ), L ij ilqf ;, iocf ;.,. 3, Crossbar,,. H,,.,[ ] ( frame) ( envelope).,,.,,,. : [ 1 ] KAROL M, HLUCHYJ M, MORGA S. Input versus out2 put queuing on a space2division packet switch [ J ]. Trans on Communications, 987, 12 ( 35) : IEEE [ 2 ]ADERSO T, OW ICKI S, SAXES J, THACKER C. H igh speed switches scheduling for local area network [ J ]. ACM Transactions on Computer System s, 1993, 11 ( 4) : [ 3 ]MEKKITTIKU I A, MCKEOW. A p ractical scheduling algorithm to achieve 100% throughout in input2queued swit2 ches[ C ] / / IEEE IFOCOM 98. San Francisco, CA, 1998: [ 4 ]MCKEOW, IZZARD M, MEKKITTIKUL A, et al. The tiny2tera: a packet switches core [ J ]. IEEE M icro M aga2 zine, 1997, 17 (1) : [ 5 ] Cisco Inc. Cisco series2internet Router. Product O2 verview [ EB /OL ]. [ ]. http: / /www. Cisco.
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