MC74LVX50. Hex Buffer

Transcription

1 Hex Buffer The MC74LX50 is an advanced high speed CMOS buffer fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0, allowing the interface of 5.0 systems to systems. Features High Speed: t PD = 4. ns (Typ) at CC = 3.3 Low Power Dissipation: I CC = 2 () at T = 25 C High Noise Immunity: NIH = NIL = 28% CC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for to 3.6 Operating Range Low Noise: OLP = 0.5 () These Devices are Pb Free and are RoHS Compliant SOIC 4 NB D SUFFIX CSE 75 PIN SSIGNMENT TSSOP 4 DT SUFFIX CSE 948G CC 6 Y6 5 Y5 4 Y Y Y 2 Y2 3 Y3 GND Y2 Y3 Y = Y4 Y Y Y2 Y3 Y4 Y5 MRKING DIGRMS 4 4 Lead (Top iew) LX50G WLYWW SOIC 4 NB Y6 Figure. Logic Diagram 6 Figure 2. Logic Symbol Y6 4 LX 50 LYW FUNCTION TBLE TSSOP 4 Input L H Y Output L H LX50 = Specific Device Code = ssembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Semiconductor Components Industries, LLC, 204 ugust, 204 Rev. 5 Publication Order Number: MC74LX50/D

2 MXIMUM RTINGS Symbol Parameter alue Unit CC DC Supply oltage 0.5 to 7.0 IN DC Input oltage 0.5 to 7.0 OUT DC Output oltage 0.5 to CC 0.5 I IK DC Input Diode Current I < GND 20 m I OK DC Output Diode Current O < GND ±20 m I OUT DC Output Sink Current ±25 m I CC DC Supply Current per Supply Pin ±50 m T STG Storage Temperature Range 65 to 50 C T L Lead Temperature, mm from Case for 0 Seconds 260 C T J Junction Temperature under Bias 50 C J Thermal Resistance (Note ) SOIC TSSOP MSL Moisture Sensitivity Level F R Flammability Rating Oxygen Index: 30% 35% UL in C/W ESD ESD Withstand oltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) > 2000 > I Latchup Latchup Performance bove CC and Below GND at 85 C (Note 5) ±300 m Stresses exceeding those listed in the imum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Measured with minimum pad spacing on an FR4 board, using 0 mm by inch, 2 ounce copper trace with no air flow. 2. Tested to EI/JESD Tested to EI/JESD Tested to JESD22 C0. 5. Tested to EI/JESD78. RECOMMENDED OPERTING CONDITIONS Symbol Parameter Min Unit CC Supply oltage 3.6 I Input oltage (Note 6) O Output oltage (HIGH or LOW State) 0 CC T Operating Free ir Temperature C t/ Input Transition Rise or Fall Rate CC = ± ns/ Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 6. Unused inputs may not be left open. ll inputs must be tied to a high or low logic input voltage level. NOTE: The J of the package is equal to /Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below. 2

3 DC ELECTRICL CHRCTERISTICS Symbol Parameter Test Conditions CC () IH High Level Input oltage 3.6 IL Low Level Input oltage 3.6 OH OL High Level Output oltage ( IN = IH or IL ) Low Level Output oltage ( IN = IH or IL ) I OH = 50 I OH = 50 I OH = 4 m I OL = 50 I OL = 50 I OL = 4 m I IN Input Leakage Current IN = 5.5 or GND 0 to 3.6 T = 25 C T 85 C Min Typ Min Unit ±0. ±.0 I CC Quiescent Supply Current IN = CC or GND Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. C ELECTRICL CHRCTERISTICS Input t r = t f = ns T = 25 C T 85 C Symbol Parameter Test Conditions t PLH, Propagation Delay, CC = 2.7 C L = 5 pf t PHL Input to Y C L = 50 pf CC = 3.3 ± 0.3 C L = 5 pf C L = 50 pf Min Typ Min Unit ns t OSHL t OSLH Output to Output Skew (Note 7) CC = 2.7 C L = 50 pf.5.5 ns CC = 3.3 ±0.3 C L = 50 pf.5.5 C IN Input Capacitance pf C PD Power Dissipation Capacitance (Note 8) 25 C, CC = Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (t OSHL ) or LOW to HIGH (t OSLH ); parameter guaranteed by design. 8. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. verage operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC. C PD is used to determine the no load dynamic power consumption; P D = C PD CC 2 f in + I CC CC. NOISE CHRCTERISTICS Input t r = t f = ns, C L = 50pF, CC = 3.3 Symbol Characteristic 5 T = 25 C OLP Quiet Output imum Dynamic OL OL Quiet Output Minimum Dynamic OL IHD Minimum High Level Dynamic Input oltage ILD imum Low Level Dynamic Input oltage 0.8 Typ pf Unit 3

4 TEST POINT 50% t PLH t PHL CC GND DEICE UNDER TEST OUTPUT C L * Y 50% CC Figure 3. Switching Waveforms *Includes all probe and jig capacitance Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit EMBOSSED CRRIER DIMENSIONS (See Notes 9 and 0) Tape Size B D D E F K P P 0 P 2 R T W 8 mm 4.35 mm (0.79 ) 2 mm 8.2 mm (0.323 ).5 mm ( ).0 mm Min (0.79 ).5 mm Min (0.060).75 mm ±0. ( mm ±0.5 (.38 ±0.002 ) 5.5 mm ±0.5 (0.27 ±0.002 ) 2.4 mm (0.094 ) 6.4 mm (0.252 ) 4.0 mm ±0.0 ( mm ±0.0 ( mm ±0.0 ( mm ±0. (0.57 mm ±0. ( mm (0.98 ) 30 mm (.8 ) 0.6 mm (0.024) 8.3 mm (0.327) mm ±0.3 (0.470 ±0.02 ) 6 mm 2. mm (0.476 ) 7.5 mm ±0.0 ( mm (0.3 ) 4.0 mm ±0.0 ( mm ±0.0 (0.35 mm ±0.0 ( mm (0.642) 24 mm 20. mm (0.79 ).5 mm ±0.0 ( mm (0.468 ) 6.0 mm ±0.0 ( mm (0.957) 9. Metric Dimensions Govern English are in parentheses for reference only. 0. 0, B 0, and K 0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 0 within the determined cavity 4

5 K t TOP COER TPE D P 2 P 0 0 PITCHES CUMULTIE TOLERNCE ON TPE ±0.2 mm (±0.008 ) E B K 0 SEE NOTE FOR MCHINE REFERENCE ONLY INCLUDING DRFT ND RDII CONCENTRIC ROUND B B EMBOSSMENT USER DIRECTION OF FEED P SEE NOTE CENTER LINES OF CITY F W D FOR COMPONENTS mm.2 mm ND LRGER *TOP COER TPE THICKNESS (t ) 0.0 mm (0.004 ) MX. R MIN. BENDING RDIUS TPE ND COMPONENTS SHLL PSS ROUND RDIUS R WITHOUT DMGE EMBOSSED CRRIER EMBOSSMENT 0 MXIMUM COMPONENT ROTTION 00 mm (3.937 ) mm MX TYPICL COMPONENT CITY CENTER LINE TPE TYPICL COMPONENT CENTER LINE mm (0.039 ) MX 250 mm (9.843 ) CMBER (TOP IEW) LLOWBLE CMBER TO BE mm/00 mm NONCCUMULTIE OER 250 mm. 0, B 0, and K 0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 0 within the determined cavity Figure 6. Carrier Tape Specifications 5

6 t MX.5 mm MIN (0.06 ) mm ±0.2 mm (0.52 ±0.008 ) 20.2 mm MIN (0.795 ) 50 mm MIN (.969 ) FULL RDIUS G Figure 7. Reel Dimensions REEL DIMENSIONS Tape Size T&R Suffix G t 8 mm T, T2 78 mm (7 ) 8 mm T3, T4 330 mm (3 ) 2 mm R2 330 mm (3 ) 6 mm R2 360 mm (4.73 ) 24 mm R2 360 mm (4.73 ) 8.4 mm, +.5 mm, 0.0 ( , 0.00) 8.4 mm, +.5 mm, 0.0 ( , 0.00) 2.4 mm, + mm, 0.0 ( , 0.00) 6.4 mm, + mm, 0.0 ( , 0.00) 24.4 mm, + mm, 0.0 ( , 0.00) 4.4 mm (0.56 ) 4.4 mm (0.56 ) 8.4 mm (0.72 ) 22.4 mm (0.882 ) 30.4 mm (.97 ) DIRECTION OF FEED BRCODE LBEL POCKET HOLE Figure 8. Reel Winding Direction 6

7 CITY TPE TOP TPE TPE TRILER (Connected to Reel Hub) NO COMPONENTS 60 mm MIN COMPONENTS DIRECTION OF FEED TPE LEDER NO COMPONENTS 400 mm MIN Figure 9. Tape Ends for Finished Goods User Direction of Feed Figure 0. TSSOP and SOIC R2 Reel Configuration/Orientation TPE UTILIZTION BY PCKGE Tape Size SOIC TSSOP QFN SC88 / SOT 353 SC88/SOT mm 5, 6 Lead 2 mm 8 Lead 8, 4, 6 Lead 8, 4, 6 Lead 6 mm 4, 6 Lead 20, 24 Lead 20, 24 Lead 24 mm 8, 20, 24, 28 Lead 48, 56 Lead 48, 56 Lead ORDERING INFORMTION Device Package Shipping MC74LX50DG SOIC 4 NB (Pb Free) 55 Units / Rail MC74LX50DR2G MC74LX50DTG SOIC 4 NB (Pb Free) TSSOP 4 (Pb Free) 2500 Tape & Reel 96 Units / Rail MC74LX50DTR2G TSSOP 4 (Pb Free) 2500 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 7

8 PCKGE DIMENSIONS TSSOP 4 CSE 948G ISSUE B 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SETING PLNE U U S 2X L/2 PIN IDENT. S D C 4 4X K REF 0.0 (0.004) M T U S S N (0.00) M B U 7 G H N J J F DETIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N DETIL E W NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION DOES NOT INCLUDE MOLD FLSH, PROTRUSIONS OR GTE BURRS. MOLD FLSH OR GTE BURRS SHLL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLED FLSH OR PROTRUSION. INTERLED FLSH OR PROTRUSION SHLL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DMBR PROTRUSION. LLOWBLE DMBR PROTRUSION SHLL BE 0.08 (0.003) TOTL IN EXCESS OF THE K DIMENSION T MXIMUM MTERIL CONDITION. 6. TERMINL NUMBERS RE SHOWN FOR REFERENCE ONLY. 7. DIMENSION ND B RE TO BE DETERMINED T DTUM PLNE W. MILLIMETERS INCHES DIM MIN MX MIN MX B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDERING FOOTPRINT* PITCH 4X X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8

9 PCKGE DIMENSIONS H M B M e D 7 3X b B E 0.25 M C S B S C SETING PLNE SOIC 4 NB CSE ISSUE K DETIL h X 45 M L 3 DETIL NOTES:. DIMENSIONING ND TOLERNCING PER SME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DMBR PROTRUSION. LLOWBLE PROTRUSION SHLL BE 0.3 TOTL IN EXCESS OF T MXIMUM MTERIL CONDITION. 4. DIMENSIONS D ND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MXIMUM MOLD PROTRUSION 0.5 PER SIDE. MILLIMETERS INCHES DIM MIN MX MIN MX b D E e.27 BSC BSC H h L M SOLDERING FOOTPRINT* X.8.27 PITCH 4X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74LX50/D