4.1 INTRODUCTION 4. CONTROL FOR VOLTAGE BALANCING 80

Transcription

1 4. ONTRO FOR VOTAGE BAANING 4.1 INTRODUTION An actie power ilter i propoed in thi tudy. The actie ilter conit o the otwitching multileel inerter with lying capacitor a tated in chapter. With regard to the control ytem, mathematical model or the actie power ilter hae been deeloped uing intantaneou power theory. Howeer, the analytical approach i mainly ocued on oltage balancing iue, in conjunction with the oerall power compenation controller. In thi ection, the ariou controller related to oltage balancing in the actie ilter are modeled and analyzed. To identiy each unction o the controller, characteritic o the control algorithm baed on the intantaneou power theory are preented. Fig. 4.1 how the ytem coniguration o the propoed actie power in thi tudy. The main circuit conit o a lying-capacitor three-leel inerter connected in parallel with the nonlinear load. The circuit i connected to the ac line ide. For harmonic-adaptie control, it i required to detect the harmonic content o the three-phae load current and the main ource oltage. Such an approach make it poible to compenate all harmonic exiting in the nonlinear load by injecting the negatie compenating harmonic. There are two main control part to the oerall controller and the oltage controller. The oerall controller goern to control the working on the actie ilter that can eliminate harmonic current on the non-linear load. The control loop i deigned with intantaneou reactie power (IRP) theory. The oltage controller act a oltage tabilizer to maintain the oltage balance between the capacitor. 4. ONTRO FOR VOTAGE BAANING 80

2 i i Nonlinear oad a b c V dc A Source i S 1a S 1b S 1c V S a S b S c a b c dc dc i IRP ontrol Actie Filter TMS303 DSP board i i _ S a _ S 1a urrent ontrol _ S b _ S 1b Switching Pattern _ S c _ S 1c ± α p 0 ( ) PVc IVc ( ) PVdc IV dc c - - V dc V Fig Propoed three-leel actie power ilter with lying capacitor. 4. INSTANTANEOUS REATIVE POWER (IRP) ONTRO Variou approache hae been ued to calculate the uitable compenating current reerence [B1], [B4], [B6], [B10], [B1], and [B19]. Among them, intantaneou reactie power (IRP) control that i well known a p-q algorithm preented by Akagi i widely ued in actie power application [B1]. In thi tudy the IRP control algorithm i conidered. Thi algorithm i uitable or balanced ource oltage and nonlinear load, and directly control the ource current to compenate the current harmonic and the power actor at the ame time. To deine an IRP theory, a three-phae power circuit i modeled below: 4. ONTRO FOR VOTAGE BAANING 81

3 a b and c ia i ib (4-1) ic where, a, b, and c are the intantaneou ource oltage and i a, i b, and i c are the intantaneou load current. To calculate the intantaneou power, the three-phae ource oltage and the three-phae load current are tranormed into the α-β orthogonal coordinate. The α-β tranormation i applied to the ource oltage and the load current, repectiely. Accordingly, the pace ector are deined by: α β [ ] a b c i i α and i [ ] β i i i a b c (4-) where, [ ] / 3 / 1/ 3 / The intantaneou actie power and imaginary power are calculated rom the α-β orthogonal coordinate. Thee intantaneou power are iltered to eparate ac and dc component. Here, the dc component are related to the actie and reactie power due to undamental oltage and current. Aume that the intantaneou real power, p, and intantaneou imaginary power, q, on the non-linear load are gien by p q α β β i α i α β (4-3) 4. ONTRO FOR VOTAGE BAANING 8

4 In (4-3), α i α and β i β obiouly mean intantaneou real power becaue they are deined by the product o the intantaneou oltage in one axi and the intantaneou current in the ame axi. Thereore, p i the real power in a three-phae circuit a deined in Fig. 4.. β Sβ S i β i 0 Sα i α α Fig. 4.. Deinition o actie and reactie power with α-β coordinate. Howeer, α i β and β i α are not intantaneou power, becaue they are deined by the product o the intantaneou oltage and current under dierent axe in the perpendicular axi. Thu, q can not be dealt with a a conentional electrical quantity o that their dimenion i completely dierent rom that o the conentional reactie power. From (4-3), the intantaneou power can be decompoed into two intantaneou real and imaginary power, repectiely. p p ~ p q q q~ (4-4) where, p and q are the dc component correponding to the undamental o the load current, p~ and q ~ are the ac component to the harmonic current. Fig. 4.3 how the block diagram o an implementing p-q algorithm to extract the current reerence rom the intantaneou power theory, which i baed on the high pa ilter (HPF). 4. ONTRO FOR VOTAGE BAANING 83

5 p q ~ p q ~ i p p ~ p q q q ~ p q p ~ p q q ~ HPF p q (a) Block diagram o control logic i a i b i c i α i β Sα α i α S β i α Σ p HPF p a b c Sα Sβ Sα i β -1 Σ q S β i α HPF q (b) Implementation o control logic Fig p-q algorithm or the current reerence extraction. In the actie power ilter or a harmonic compenation, p and q are gien by p 0 and q q~ (4-5) Uing (4-1) and (4-), the compenation reerence current are deried a: i i i a b c [ ] T α β 1 β α 0 q (4-6) when the dc capacitor could not maintain a contant, the aerage charge through the dc capacitor could be not zero. Thi i becaue the inerter ha a witching deice lo and a capacitor lo. 4. ONTRO FOR VOTAGE BAANING 84

6 To meet the charge balance, ome real power i deliered to the dc capacitor by controlling a dc oltage loop o the inerter. Thu, an additional intantaneou real power, p, hould be compenated a i i i a b c [ ] T α β 1 β α p q (4-7) where, p i the intantaneou real power neceary to compenate the oltage acro the dc capacitor to the reerence alue. 4.3 URRENT ONTRO The ue o a current control loop ha eeral beneit or an actie ilter. Firt, i the actie ilter i ued to inject the current harmonic into the power network, the current command i applied to the current loop to achiee the deired compenating current. Second, a current loop proide an oercurrent protection, when the actie ilter current are ened and limited to a maximum alue. Third, or adance control, it i neceary to hae a current control loop, which ollow the nonlinear current command. Once the linearized model o an actie ilter i identiied with a plant, the current controller i deigned to generate harmonic reerence current or the three-phae ytem. Fig. 4.4 how a current controller or the actie ilter. A PI controller in thi tudy i elected or a current controller becaue o it implicity to implementation, and the integral portion o the controller preent the control ignal rom arying erratically between the aturation leel o the controller. Aume that the reitance o the interace inductor i zero. The current loop traner unction i hown in (4.8): 4. ONTRO FOR VOTAGE BAANING 85

7 G i ( ) H H a Pica PWM Pica PWM Iica ( ) (4-8) ia ( ) H Pica PWM H Pica PWM Iica where, Pica Iica PWM H : the proportional gain in a-phae current : the integral gain in a-phae current : the PWM gain o the actie ilter : the current enor gain in a-phae current : the interace inductance o the inductor i a - i a_ MD ( Pi a Ii ) a PI trl imiter PWM Inerter 1 Interace Inductor i a H urrent Tranducer Fig A current control loop or actie ilter. With thi control diagram in Fig. 4.4, the current loop become a econd order ytem in which econd order ytem deign technique are applied. In deigning the current controller gain, it i deirable to peciy a bandwidth or the current loop baed on the witching requency o the actie ilter. onidering the at bandwidth o the current loop, the characteritic equation o the approximated current loop i deried. Moreoer, ince it i a econd-order equation, the natural requency, ω n, and damping ratio, ξ, can be ued to obtain the current controller gain and 4. ONTRO FOR VOTAGE BAANING 86

8 time contant. Below, (4-9) and (4-10) peciy the damping ratio and the natural requency o the approximated ytem. n H ( ) ω ξω ω (4-9) n n where, ξω n Pi a H PWM ωn Ii a H PWM Pica ωc 3ωn (1 ξ ) (1 ξ ) 1 (4-10) From (4-9) and (4-10), the P and I gain can be deried or a gien natural requency and damping ratio. In order to ealuate the requency repone o the ytem, the bandwidth o the cloed-loop traner unction can be ounded. Once the gain o the current controller are ound, an unapproximated current loop i imulated by uing Bode plot. Baed on the load condition with an interace inductor, PI gain are calculated conidering the deired peciication with V dc 750V, 1 mh, and V re 5V. onidering the witching requency o 1 khz, the bandwidth o the controller i elected a 1. khz. The controller ha been deigned with the ollowing parameter: PWM V dc /V re 150 H i a /i a 0.05 ξ 1 Pica.01 Iica mF 4. ONTRO FOR VOTAGE BAANING 87

9 Thereore, the traner unction o the PI controller i.01( 3771) 7580 G PI ().01 (4-11) With (4-11) and the eedback path, the open-loop traner unction or the loop traner unction, GH (), can be deried a: GH ,075 56,850,000 (4-1) () (.01 ) PWM H where, GH() i the product term in the ytem traner unction o the orward path and the eedback path. To ind the magnitude and phae margin o the open-loop traner unction, the requency repone are plotted in Fig Fig. 4.5(a) how the Bode plot o a PI controller rom the traner unction o G PI (). The controller ha two input; the reerence ignal I a and the eedback ignal I a_md. The error ignal i ed the PI controller and the output can be et the integration time contant. The output o the controller arie between 0 and 1 and ha two limit, one correponding to the lowet duty cycle and the other or the highet duty cycle. The controller proide output current to change uddenly by the current command and the action o the integrator capacitor caue the controller output current to begin to rie at a teady rate. The Bode plot o the current loop traner are plotted in Fig. 4.5(b). The phae margin o the ytem i about 90 at the gain crooer point. 4. ONTRO FOR VOTAGE BAANING 88

10 10 3 Magnitude Phae (degree) Magnitude Frequency (radian) Frequency (radian) (a) Proportional-integral (PI) controller Phae (degree) Magnitude g Frequency (radian) Frequency (radian) (b) Open-loop ytem Fig Bode plot o an open-loop current control ytem with proportional-integral control. 4. ONTRO FOR VOTAGE BAANING 89

11 4.4 D BUS APAITOR VOTAGE ONTRO The mot commonly ued technique or dc bu capacitor oltage control are the PI controller and PWM. The dc bu oltage control allow the dc capacitor oltage to hae a contant alue. When the capacitor doe not maintain a contant, the aerage charge through the dc capacitor doe not equal zero. Thi i becaue the inerter ha witching a deice lo and a capacitor lo during operation. Furthermore, the ize o the dc bu capacitor depend on the magnitude o ripple oltage and capacitor current. For example, when the ilter current i poitie, the capacitor i charged. When the ilter current i negatie, the capacitor i dicharged. During charging and dicharging, the charging requency i twice the line requency. On the other hand, i the tranient load change in the actie ilter occur, the dc bu oltage arie. Thi ariation i conequently conidered when deigning the dc bu capacitor. Alo, in order to tabilize the dc bu oltage, a cloed loop control i required. Fig. 4.6 (a) how the propoed oerall oltage control block diagram or the dc capacitor with a PI controller. The controller i ue to compenate the dc capacitor ariation correponding to load ariation. In the teady tate, the ariation o the dc capacitor oltage depend on the alternating power o the load. Thu, the deign o the PI controller i related to the load real power. The deried p i the real power generated by the actie ilter and the real power i compenated by upplying or obering to tabilize the dc bu oltage within the deired oltage range. During the reactie power compenation, the oltage control loop can be impliied in Fig. 4.6(b). The controller perorm the oltage regulation to maintain a contant oltage on the dc link o the actie ilter. V dc i the error to the oltage reerence and actual command, V dc -V dc, by generating a oltage drop due to loe in the interacing inductor and witching deice. From the impliied block diagram, we can get the dc oltage control loop traner unction, which i related to a eedback loop with PI control. The error obtained i compenated by the gain parameter, which are determined rom an aigned traner unction. The deigned procedure are imilar to that o the current controller. 4. ONTRO FOR VOTAGE BAANING 90

12 i abc abc abc/ αβ abc/ αβ i α i β Sα Sβ P ( i,) q p p ~ p q q ~ HPF q p p p i α i ( p, -1 ) i β αβ/ abc i a G () i a dc - dc _ MD dc ( P I ) a p d H V dc (a) Oerall oltage control loop dc - dc _ MD dc P ( I ) a p G() i a G () i a d dc H V (b) Simpliied oltage control loop Fig Voltage control loop or dc bu capacitor. 4.5 FYING APAITOR VOTAGE ONTRO In the propoed actie ilter, the oltage unbalance o the lying capacitor in practical implementation wa obered due to unequal parameter o the inerter. Thu, a oltage 4. ONTRO FOR VOTAGE BAANING 91

13 controller i neceary to maintain a contant alue o the oltage ource acro the lying capacitor. With regard to the control cheme or oltage balancing, there are ariou compenating approache or the three-phae actie power ilter with PWM control a ollow: - Direct witching tate control, - Sliding mode control, - Hyteri control, - PI control with duty-cycle changing, etc. Furthermore, it i well known that the perormance o actie power ilter highly depend on the dynamic repone correponding load ariation. Thu, it i important to minimize the calculation proceing time to obtain the power compenating reerence. To reach thi end, a new PI controller with phae-hit i propoed and explored in thi ection. The controller i imilar to a conentional PI controller with duty-cycle changing. It can achiee a at dynamic repone o the ytem in conjunction with a digital controller Analyi o Voltage Variation The current lowing lying capacitor depend on the control index and output current o the inerter a below. i ( t) m I (4-13) c where, m c i the dierent duty cycle between witching deice and I i the output rm current. On the other hand, it depend on the capacitor oltage ariation. i d ( t) (4-14) dt 4. ONTRO FOR VOTAGE BAANING 9

14 where, i the lying capacitance o the lying capacitor. Subtituting (4-13) into (4-14), thu, lead to (4-15). d ( t) dt mci (4-15) Thi reult indicate that ariation o capacitor oltage are goerned by the nonlinear irt order dierential equation. From (4-15), the capacitor oltage ariation can be deried a below. m I c (4-16) w From (4-16), the oltage loop traner unction can be deried. By controlling the polarity o m c in Fig. 4.6, the lying capacitor oltage can be tabilized a hown in Fig. 4.7, where ± m c depend on the inerter parameter. V V S / d 1 > d d 1 < d : harging d 1 d : Dicharging ± m c : ontrollable oltage 0 t Fig Voltage control or balancing. Fig. 4.8 how the etimated oltage unbalance o the lying capacitor under dierent capacitance. During a 1 minute running a hown in Fig. 4.8(a), the lying capacitor with ONTRO FOR VOTAGE BAANING 93

15 µf wa decreaed to 85V or m c 0.05 and 97 V or m c 0.01, repectiely. Howeer, with 00 µf, the oltage wa alo decreaed to 5 V or m c 0.05 and 85 V or m c 0.01, repectiely. A a reult, thi indicate that a change in the dierence o duty cycle between two cell, m c ( d 1 - d ), create a large change in V, when i mall V m V m 0.01 Vc1( t ) Vc( t) m 0.05 Vc( t ) Vc3( t ) m µF 40 00µF t T (ec) t T (ec) 60 (a) 1000 µf (b) 00 µf Fig Etimated oltage unbalance o the clamping capacitor during inerter operation. Fig. 4.9 how the imulated oltage unbalancing and it compenation cheme o the actie ilter. Fig. 4.9(a) how an example o the dierged capacitor oltage in imulation. When the unbalanced oltage phenomena occur in the lying capacitor, the oltage dierge eentually reulting in a dangerou condition or the inerter. Thereore, in order to maintain the oltage balance at any cycle, a eedback control i required or a oltage balancing o the lying capacitor. Howeer, the controller doe not need a real time proce oer the indiidual capacitor oltage. For thi purpoe, Fig. 4.9(b) how an oerall control cheme or oltage balancing. The control cheme i to control the charging time or the lying capacitor by uing phae hiting. 4. ONTRO FOR VOTAGE BAANING 94

16 The baic idea i to conert rom m c to the phae hiting angle, α. Firt, each capacitor oltage V (i,j) i meaured with repect to the reerence dc oltage V dc. Then, the oltage error i ued or the light adjutment o phae hit o the witching pattern through the control window (± α (i,j)) o the i th and j th leel. The ign o the phae-hit adjutment depend on the charging oltage balance through the operating window ( α(i,j)) o that the V (i,j) i controlled to the deired oltage leel. Ater the oltage reache the equalized oltage, the witching pattern ha a normal operation unction. Thi approach reult in the ame eect to adjut the duty cycle on the controller. Howeer, thi approach i limited to the digital controller, which ue a conerion table a the look-up table. For implementation, a digital proportional-integral (PI) controller a hown in Fig. 4.9(c) can be ued to ole the oltage unbalance problem. Baically, wheneer the oltage unbalance happen, the witching pattern o the inerter hould be controlled with an immediate phae-hiting adjutment by triggering the control window. 4. ONTRO FOR VOTAGE BAANING 95

17 800 Balanced cae apacitor Voltage [V] Unbalanced cae (5%) Time [ mec] (a) apacitor oltage waeorm o the inerter S S 1 arrier 0 α π ωt S 1w S w 0 - φ π - α Dichr hrg (b) Feedback control cheme o the oltage tabilization 4. ONTRO FOR VOTAGE BAANING 96

18 V dc Sot-witching Multileel Actie Filter S1 Sn Switching Pattern Generator p V c S - ± α ( ) Vp S Vi i, j (c) Voltage tabilizer with a PI controller Fig A oltage controller or oltage tabilization Voltage Stabilizer Fig how the propoed oltage controller or the lying capacitor to tabilize the oltage balance between the witche. A like the current loop a tated in the preiou ection, the oltage controller i deigned with a PI controller. To elect the gain o the controller, the relation between the current loop and the lying capacitor i conidered. Fig. 4.10(a) how the oerall block diagram o the oltage controller that i linked to the current controller. For impliication, aume that the magnitude o the current command o the actie ilter i contant in teady tate. Thu or a mall ariation o the duty cycle, m c, the oltage i unbalance to the lying capacitor. Fig. 4.10(b) how the impliied oltage loop or oltage tabilization. Fig how the correponding tep repone o the cloed-loop ytem or a lying capacitor oltage loop. The time-domain repone indicate that an original ytem model i table or the oltage ariation. Thi tability i one o important conideration when deigning a control 4. ONTRO FOR VOTAGE BAANING 97

19 ytem. Since the ytem i table, then it relatie tability can be impliied to deign the controller to reduce the calculation time to ind the compenation parameter. On the other hand, a impliied block diagram a hown in Fig. 4.10(b) repreent the control ytem or implicity. The interpretation o the impliied model i that due to high orward gain in the witching ampliier, it repone i determined by the eedback. Simulation reult in Fig how that the modiied model i ery cloe to the original control ytem, een the ytem ha a mall oerhoot. The rie time o the modiied model i a little at and the time repone reache the inal teady tate. It conclude that the impliied mode i alid or oltage control. The impliied oltage loop traner unction i hown in (4.15): ( ) ( ) Iw H Iw H PVc PVc Iw H Iw H PVc IVc PVc IVc (4-17) where, PVc Ic Iw H : the proportional gain o the oltage loop, : the integral gain o the oltage loop, : the total gain o the lying capacitor loop, : the oltage enor gain o the oltage loop, and : the capacitance o lying capacitor. The reciprocal traner unction, G c () ( V c ()/V c ()), or the lying capacitor oltage ha the econd-order characteritic. The complete unction o the lying capacitor loop or oltage balancing wa deried in (4-17). It i realized in the oltage tabilizer with the PI controller G c (). The controller interact the connection between the oerall outer control loop and the inner oltage control loop. The controller gain are determined by the relationhip between a ytem tranient repone and it cloed-loop requency repone. Furthermore, ince the deried unction i a econd-order eed back control ytem, we can ue it cloed-loop 4. ONTRO FOR VOTAGE BAANING 98

20 unction a a tandard econd-order ytem. A earlier mentioned, the gain o the controller can be elected a: i a - i a_ MD H ( Pi a Ii ) a d PV ( IV ) m c - (m _ c d 1 -d ) MD PWM 1 i a H V (a) Voltage tabilizer or lying capacitor with a PI controller - _ MD ( PV IV ) m c Iw H V (b) Simpliied oltage control loop Fig ontrol block diagram or lying capacitor oltage balancing with PI control. 4. ONTRO FOR VOTAGE BAANING 99

21 800 V dc Voltage (V) Simpliied oltage loop Original oltage loop Time (ec) Fig Step repone o the cloed-loop ytem or a lying capacitor oltage loop. Pia ξω n H Iw ωn Ii a IwHV Pica ωc 3ω n (1 ξ ) (1 ξ ) 1 (4-18) From (4-18), the P and I gain can be deried or a gien natural requency and damping ratio. In order to ealuate the gain and phae margin uing Bode plot. The gain margin i ound by uing the phae plot to ind the requency. O coure, a relationhip exit between the peak alue o the cloed-loop magnitude repone and the damping ration. onidering a le oerhoot, the damping ratio (ζ 0.7) wa elected under khz. The controller ha been deigned with the ollowing parameter: Iw 7.5 ( PWM ) PWM 0.5 V dc /V re ONTRO FOR VOTAGE BAANING 100

22 0.1 H V V /V Pica 3.36 Iica 63 Thereore, the traner unction o the PI controller, G VcPI (), i G VcPI () bw 3.36( 63) (4-19) 0kHz onidering the plant model and eedback model o a ytem, the oltage loop traner unction, GH Vc (), can be calculated. GH Vc 3.36( 1) 1,50 159,000 (4-0) () ( ) PWM H where, GH Vc () i the open-loop traner unction or the oltage loop. Fig. 4.1 how the Bode plot o the open-loop oltage controller. From the traner unction o G VcPI () and GH Vc (), the Bode plot were obtained. The phae margin o the current controller wa about 90 at khz. For more table operation, a dc bypa circuit i added to the PI controller. In addition, to proide a mooth and ot tarting o the actie ilter, the oltage ramp circuit i actiated ater the controller receie the oltage command. From the ramp circuit diagram it i note that the time contant R control the rate o change o the power compenating ignal. 4. ONTRO FOR VOTAGE BAANING 101

23 10 3 Phae (degree) ( g ) Magnitude Magnitude Frequency (radian) Frequency (radian) (a) Proportional-integral (PI) controller. Phae ((degree) g ) Magnitude Frequency (radian) Frequency (radian) (b) Open-loop ytem Fig Bode plot o a oltage loop traner unction with proportional-integral control. 4. ONTRO FOR VOTAGE BAANING 10

24 4.6 ONUSION The new ot-witching multileel actie power ilter and it control cheme hae been propoed and dicued in thi chapter. To tabilize dc bu oltage and lying capacitor, the propoed cheme with eedback control loop including main current control and oltagebalancing control were analyzed and explained. The dc bu oltage control loop wa modeled with a PI controller, which indicate the dc bu oltage regulator. The controller wa conidered to the real power low through the main, the non-linear load and power conerter to reach a new a balance tate. In addition, the controller compenate the oltage drop due to witching deice lo and capacitor lo during operation. For the lying capacitor oltage balancing, a new PI controller with phae-hit ha propoed and analyzed. The controller act a the oltage tabilizer to maintain the oltage balance between lying capacitor and the witching witche. For alidation, ariou numerical imulation were conducted. In addition, conidering a tranient load changing, the time repone o the lying capacitor oltage loop wa imulated baed on the aplace tranorm o the tep repone o the ytem. The controller wa table or the tep repone. On the other hand, rom the traner unction o the oerall oltage control ytem, the Bode plot were deried. The gain and phae margin were deried rom the phyical block diagram. The alidation wa dicued with the gain and the phae magnitude o the ytem through imulation reult. To realize the propoed control algorithm, the real time digital controller hould be implemented with the oltage detection. It reult in high perormance o the ilter by compenating an adaptie gain to the controller. The eectiene o the propoed controller will be conirmed with imulation and experiment in hapter 5. Furthermore, ariou dynamic behaior o the controller or oltage balancing will be characterized by the interaction between the control eaibility and inluence o the propoed ot-witching multileel actie ilter. 4. ONTRO FOR VOTAGE BAANING 103