Characteristic Equation-Based Computation of Thévenin and Norton Equivalent Circuits

Transcription

1 IEEJ TANSACTIONS ON EECTICA AND EECTONIC ENGINEEING IEEJ Trns 0; 6: Pulished online in Wiley Online irry (wileyonlinelirry.com). DOI:0.00/tee.0689 Chrcteristic Eqution-Bsed Computtion of Thévenin nd Norton Equivlent Circuits Pper Ersoy Keleekler, Non-memer Ali Bekir Yildiz, Non-memer In this pper, new method is proposed for determining the prmeters of Thévenin nd Norton equivlent circuits. The method is unified nd employs only one topology tht depends on the test lod impednce,, connected to the output of the circuit. It does not require setting ll independent sources to zero for determining Thévenin nd Norton impednce. All equivlent circuit prmeters re derived simultneously nd systemticlly from the chrcteristic eqution relting to the output of the circuit. 0 Institute of Electricl Engineers of Jpn. Pulished y John Wiley & Sons, Inc. Keywords: Thévenin equivlent, Norton equivlent, chrcteristic eqution eceived August 00; evised 4 Novemer 00. Introduction The Thévenin nd Norton theorems re of high importnce in electricl nd electronics circuit nlysis. Any liner circuit, no mtter how complex, my e represented y Thévenin or Norton equivlent circuits ( 4). The prmeters of these equivlent circuits (i.e., U th, Z th Z nor nd J nor ) re determined y vrious pproches in circuit nlysis. The Thévenin voltge, U th,isthe open circuit voltge t the desired terminl pir of given circuit. The Norton current, J nor, is the short circuit current t the desired terminl pir of given circuit. The Thévenin/Norton impednce, Z th Z nor, whose computtion is extremely time-consuming, is the equivlent impednce t the desired terminl pir y setting ll independent sources to zero. If there re dependent sources in the circuit, test current or test voltge source is pplied to the circuit ll independent sources re set to zero. Herey, the Thévenin/Norton impednce is found y using the voltge nd current of these test sources. There re some studies out Thévenin nd Norton theorems in the literture. The systemtic structure of Thévenin theorem for liner n port networks ws given in ef. (5). Some computtionl methods for Thévenin nd Norton equivlents of the circuits were investigted in efs. (6 9). Mod presented the concepts of the Thévenin nd Norton theorems nd surveyed some textooks presenting these theorems nd gve methods of finding equivlent circuits for two ports nd multiterminl networks (0). Hley gve proof of the Thévenin theorem for liner circuits using current voltge (I V ) chrcteristic of the output of the circuits (). This method needs no network equtions or specil circuits, ut it is convenient only for experimentl pplictions. Jin nd Chn presented unified method in which two prmeters of Thévenin nd Norton equivlent circuits cn e otined simultneously nd systemticlly without requiring setting ll dependent sources to zero (). But, their method requires using the current source s test source to otin the Thévenin equivlent circuit nd the voltge source s test source to otin the Norton equivlent circuit. In Correspondence to: Ali Bekir Yildiz. E-mil: yildiz@koceli.edu.tr * Technicl Eduction Fculty, Deprtment of Electronics nd Computer Eduction, University of Koceli, 4380 Koceli, Turkey ** Engineering Fculty, Deprtment of Electricl Engineering, University of Koceli, 4380 Koceli, Turkey ddition to this restriction, the experimentl ppliction of method is limited ecuse there is no physicl current source for experimentl pplictions. Bogrd introduced n experimentl pproch to find the output resistnce, similr to the equivlent resistnce, of the mplifier circuits (3). The pplictions of Thévenin nd Norton s theorems when deling with specil cses of electric circuits re demonstrted in ef. (4). A novel nlyticl pproximtion method of frequency dependent Thévenin impednce is given in ef. (5). A lortory exercise is presented tht fcilittes the teching of Thévenin s equivlent circuit nd mximum power trnsfer through the use of lck ox equipped with two externl terminls in ef. (6). A novel Thévenin equivlent clcultion sed on vrying system condition is nlyzed in ef. (7). ecursive lest squre estimtion technique is pplied to estimte online Thévenin equivlent nd trck system voltge stility. Different engineering pplictions relting to Thévenin equivlent circuits re given in efs. (8 ). In circuit nlysis, different topologies re used to derive the prmeters of Thévenin nd Norton equivlent circuits. In order to find U th, the open circuit voltge t the desired terminls is clculted. Similrly, to find J nor, the desired terminls re short circuited nd the current through this short circuit is clculted. In determining of Thévenin nd Norton impednces, Z th Z nor, the equivlent impednce t the desired terminls is clculted y setting ll independent sources to zero. The use of different topologies in otining the prmeters of equivlent circuits is extremely time-consuming. This pper proposes novel unified, efficient, nd esy understndle pproch for computtion of equivlent circuit prmeters. The method employs only one topology tht depends on the test lod impednce,, connected to the output of the circuit. It does not require setting ll independent sources to zero for determining Thévenin nd Norton impednce. The prmeters of the Thévenin nd Norton equivlent circuits re derived simultneously nd systemticlly from the chrcteristic eqution relting to the output terminls of the circuit, which minly depends on test lod impednce. The proposed method is more powerful nd systemtic thn the conventionl methods ecuse it uses one topology to otin ll equivlent circuit prmeters. Another importnt power of the method is convenient for relizing experimentlly. The following two sections explin the sic form nd the generlized stte of the proposed method, respectively. Section 4 0 Institute of Electricl Engineers of Jpn. Pulished y John Wiley & Sons, Inc.

2 E. KEEBEKE AND A. BEKI YIDIZ N Fig.. Bsic circuit illustrtes its four ppliction exmples, followed y finl remrks in the lst section.. Fundmentls of the Proposed Method et N e liner time-invrint circuit, which my include dependent nd independent sources, mgnetic coupling. N my e either resistive or dynmic. Suppose port is creted in N, s shown in Fig., nd let us otin the Thévenin or Norton equivlent circuits for this port. The port terminls re denoted s nodes nd. Thévenin nd Norton equivlent circuits of the sic circuit re given in Fig. () nd (), respectively. The prmeters of Thévenin nd Norton equivlent circuits relting to ny circuit cn e found y determining the opencircuit voltge (U oc ) nd the short-circuit current (I sc ) otined for desired port of sic circuit ( nd in Fig. ). Thévenin voltge: Norton current: Thévenin/Norton impednce: U th U oc () J nor I sc () Z th Z nor U oc I sc U th J nor (3) In this pper, we introduce new pproch employing test lod impednce,, to determine the prmeters of Thévenin nd Norton equivlent circuits. This section detils how these prmeters cn e expressed in terms of. The port voltge (U ) nd the port current (I ) ccording to Fig. () nd () re otined s follows: The port voltge: or () () U th U U Z th U th Z nor Z nor J nor Z th U I I J nor Z nor U Zx Fig.. () Thévenin circuit () Norton circuit (4) (4) The port current: I (5) Z th or I Z nor J nor (5) Z nor Norton current: In (5) nd (5), the limit of the I s pproches zero is equl to the short-circuit current (U 0). In this cse, the Norton current is expressed s elow: U th J nor I sc lim Zx 0 I (6) Thévenin voltge: In (4) nd (4), the limit of the U s pproches infinite is equl to the open-circuit voltge (I 0). In this cse, the Thévenin voltge is expressed s elow. For indefiniteness / in (7), hospitl rule is used: U th U oc lim U (7) Zx Thévenin/Norton impednce: Suppose tht the prmeters of equivlent oth circuits re fixed nd the test lod impednce ( ) is djustle in Fig. () nd (). For determining the Thévenin (or Norton) impednce, we extrct the expression of the test lod impednce from (4) s elow: U Z th (8) U th U In Fig. (), when the port voltge (U ) drops from open-circuit voltge to one-hlf of it (U U th /), the test lod impednce is equl to the Thévenin impednce y the voltge divider rule. If this condition is sustituted into (8), it is seen tht the Thévenin impednce is equl to the test lod impednce s in (9). This pproch is used to determine experimentlly the output resistnce of the mplifier circuits in electronic experiments (0): U th / U th U th / Z th Z th (9) Similrly, this impednce cn lso e expressed ccording to the Norton equivlent circuit. First, the expression of the test lod impednce,, is extrcted from (5) s elow: Z nor J nor Z nor (0) I In Fig. (), when the port current (I ) drops from short-circuit current to one-hlf of it (I J nor /), the test lod impednce is equl to the Norton impednce y the current divider rule. If this condition is sustituted into (0), the Norton impednce is otined s: Z nor J nor / J nor Z nor Z nor () Consequently, ech one of the elow equtions gives the Thévenin (or Norton) impednce: Z th lim or Z nor lim () U U th / I Jnor/ 3. Generlized Stte of the Proposed Method We now explin the generlized stte of the proposed pproch for given equivlent circuits in Fig. () nd (). The method used for determintion of the Thévenin or Norton equivlent circuits of generl circuit in Fig. 3 is stted s elow. The test lod impednce is connected into the port. The port voltge (U ) nd the port current (I ), including the test lod impednce, re generted y using ny formultion method such 50 IEEJ Trns 6: (0)

3 CHAACTEISTIC EQUATION-BASED COMPUTATION OF THÉVENIN AND NOTON EQUIVAENT CICUITS N U Fig. 3. Bsic circuit including test lod impednce s stte vrile nlysis, mesh nlysis, or nodl nlysis ( 3). The system equtions nd the output equtions in s domin re s in (3) nd (4). Our method is independent from the formultion: The system equtions: AX (s) BU (s) (3) The output equtions: Y (s) CX (s) DU (s) (4) A, B, C, D re coefficient mtrices, U (s) is the source vector, X (s) is the unknown vector, Y (s) is the output vector. Mtrix A is lso clled the chrcteristic mtrix in the circuit nlysis. Solutions of the system equtions nd the output equtions re given in (5) nd (6), respectively: ( ) X (s) A BU (s) det(a) Adj(A) BU (s) (5) Y (s) CA BU (s) DU (s) [CA B D]U (s) [ ( ) ] C det(a) Adj(A) B D U (s) (6) It is ovious tht solutions of (5) nd (6) re frctionl. The determinnt of the chrcteristic mtrix, A, hs lso frctionl nd polynomil form s in (7): det(a) (7) (s) nd (s) show the numertor nd the denomintor of the determinnt, respectively. The determinnt expression in (7) is sustituted into (5) nd (6): ( ) X (s) (s) Adj(A) Adj(A) B (s) M (s) Adj(A) B (s) [ Y (s) C (s) BU (s) I U (s) M (s) U (s) (8) ] Adj(A) B D U (s) N (s) U (s) (9) N (s) C Adj(A) B (s) D C M (s) D The trnsfer functions of the system re otined from (9): H (s) Y (s) U (s) N (s) C M (s) D (0) The numertor of determinnt of the coefficient mtrix (A) in (7) nd the denomintor of the trnsfer functions in (0) re equl. Therefore, polynomil is lso clled the chrcteristic eqution in circuit nlysis. The port voltge or the port current relting to the generl circuit is expressed in terms of vriles of the utilized method. The equivlent circuit prmeters relting to the generl circuit hve frctionl nd polynomil form s shown in (): U th (s) P (s) () Q (s) Z th (s) Z nor (s) P (s) Q (s) J nor (s) P 3(s) Q 3 (s) or J nor (s) U th(s) Z th (s) P (s)q (s) P (s)q (s) () (c) For the generl circuit, the port voltge in (4) nd the port current in (5) cn e presented s elow in terms of the expressions in (). The port current: The port voltge: U (s) I (s) U th(s) Z th (s) P (s) Q (s) P (s) Q (s) (s) Z th (s) U th (s) (s) P (s) P (s) Q (s) Q (s) P (s)q (s), (s) P (s)q (s), Q (s)q (s) () (3) According to system theory, ll circuit vriles nd trnsfer functions relting to ny circuit hve the sme denomintor in s domin ( 4). Therefore, the denomintors of the trnsfer function in (0) nd the port vriles in () nd (3) re equl to the chrcteristic eqution () of the system. in the expressions of the output vriles (the port voltge or the port current) is equl to N (s)u (s) ccording to (9). is the coefficients of nd (s) consists of terms independent of. The denomintors (), chrcteristic equtions, of () nd (3) re identicl, ut their numertors re different. Moreover, the components (, x ) of chrcteristic equtions re identicl. The chrcteristic eqution,, cn e lwys prtitioned in terms of, x, s in () nd (3). In order to determine the prmeters of Thévenin nd Norton equivlent circuits, our proposed pproch depends on otining the components (, x ) of the chrcteristic eqution nd polynomil. Here, the most importnt point is tht these components give directly the prmeters of the equivlent circuits, which re indicted clerly elow. After expressing the port voltge (U ) or the port current (I ) in the generl circuit, the prmeters of equivlent circuits re determined s follows. Here, they re otined y using concepts of the open-circuit voltge (U oc ) nd short-circuit current (I sc ), s explined in Section. In short-circuit stte, is zero. In open-circuit stte, is infinite. Norton current: In (), the limit of the I s pproches zero is equl to the short-circuit current (I sc ) nd this current is the Norton current: J nor (s) I sc (s) lim I (s) (4) Zx 0 (s) According to (3), lim U (s) 0. Zx 0 5 IEEJ Trns 6: (0)

4 E. KEEBEKE AND A. BEKI YIDIZ Thévenin voltge: In (3), the limit of the U s pproches infinite is equl to the open-circuit voltge (U oc ) nd this voltge is the Thévenin voltge. I U th (s) U oc (s) lim U (s) (5) Zx For indefiniteness in (5), if hospitl rule is used, the expression is otined s: U th (s) U oc (s) lim U (s) (6) Zx According to (), lim I (s) 0. Zx Thévenin/Norton impednce: The expression of the test lod impednce is extrcted from () s elow: (s) I (s) (s) (7) When the port current of the generl circuit is equl to onehlf of its short-circuit current, the Thévenin/Norton impednce nd test lod impednce re equl. Hence, the limit of the test lod impednce s I pproches one-hlf of I sc descries the Thévenin/Norton impednce: Z th (s) Z nor (s) lim (s) I Isc/ Isc(s) (s) (8) If the expression of I sc in (4) is sustituted into (8), Z th (Z nor ) is otined s elow: Z th (s) Z nor (s) (s) (s) (s) (9) Eqution (3) cn e lso used to express Thévenin/Norton impednce. The expression of the test lod impednce is extrcted from (3) s elow: U (s) (s) (s) (30) U (s) When the port voltge of the generl circuit is equl to onehlf of its open-circuit voltge, the Thévenin/Norton impednce nd test lod impednce re equl. Hence, the limit of the test lod impednce s U pproches one-hlf of U oc descries the Thévenin/Norton impednce: Uoc(s) Z th (s) Z nor (s) lim Z (s) x (s) U Uoc/ Uoc(s) (3) If the expression of U oc in (6) is sustituted into (3), Z th (Z nor ) is otined s elow: Z th (s) Z nor (s) x (s) (s) x (s) (s) (3) The Thévenin/Norton impednce cn e lso otined directly from (4) nd (6): Z th (s) Z nor (s) U th(s) J nor (s) (s) (33) Moreover, it cn e lso relized tht (4), (6), nd (33) re equl to the expressions in (), respectively: U th (s) P (s)q (s) Q (s)q (s) P (s) (34) Q (s) J nor (s) (s) P (s)q (s) P (s)q (s) Z th (s) Z nor (s) (s) P (s)q (s) Q (s)q (s) P (s) Q (s) (34) (34c) U Fig. 4. A simple resistive circuit After connecting the test lod impednce ( ) into the generl circuit nd expressing the port voltge or the port current ccording to this element, the chrcteristic eqution nd the required components (, x, P) re esily determined. All equivlent circuit prmeters re simultneously derived in terms of, x, P from only one topology. Therefore, the proposed method is unified nd systemtic, which hs een pplied to ll kind of possile complicted circuit exmples. 4. Applictions In this section, four ppliction exmples re presented. First exmple, simple resistive circuit in Fig. 4, is tken to show systemticl nd experimentl power of the method. Besides, the method is compred with the conventionl methods from the point of theoreticl nd experimentl. Exmple. The proposed method requires to e connected test lod resistnce, potentiometer, to designted terminl pir nd to e otined port voltge or port current. First, let us write the port current: I ( ) x P x x, the numertor, the coefficient of x nd independent terms of x in denomintor correspond to P, x nd in (), respectively. The Norton current is equl to limit of I s x pproches zero: J nor lim I x 0 This result cn e directly otined from (4), P/. Now, let us write the port voltge, x U x ( ) x P x U x i ( ) x x x x, the coefficient of x in numertor, the coefficient of x nd independent terms of x in denomintor correspond to P, x nd in (3), respectively. As seen from the expressions of port current nd port voltge, the components (P,, x ) of the method re the sme. The Thévenin voltge is equl to limit of U s x pproches infinite: U th lim U x This result cn e directly otined from (6), P/ x. The Thévenin/Norton resistnce cn e otined from the expressions of port current or voltge. The Thévenin/Norton resistnce is equl to vlue of the test lod resistnce which drops the port voltge/current to hlf. If we extrct the test lod resistnce from the port current expression, x I I ( ) so, th nor x lim x I Jnor 5 IEEJ Trns 6: (0)

5 CHAACTEISTIC EQUATION-BASED COMPUTATION OF THÉVENIN AND NOTON EQUIVAENT CICUITS I A x C U I () () U x V Fig. 5. Experimentl connection structure to otin Thévenin/ Norton equivlent circuit prmeters or if the test lod resistnce is extrcted from the port voltge expression, U x U ( ) so, th lim x U U th Thévenin/Norton resistnce cn e directly otined from (9) or (33), / x. The proposed method is systemticl nd unified. All prmeters of the equivlent circuits re otined simultneously y using one topology. The conventionl methods require different topologies to derive ll prmeters. For the Thévenin voltge nd the Norton current, the open-circuit voltge nd shortcircuit current re clculted, respectively. Next, the equivlent resistnce is clculted y setting ll independent sources to zero ( 4). Using test voltge source or test current source is nother method to otin the prmeters of Thévenin/Norton equivlent circuits (). Tht method does not require to e set ll independent sources to zero. But it gives directly the Norton equivlent when the voltge source is used s the test source nd the Thévenin equivlent when the current source is used s the test source. Therefore, it uses two topologies. The proposed method in this pper is convenient for relizing experimentlly. The Thévenin/Norton prmeters re experimentlly otined y connecting potentiometer to the port terminls nd. The mmeter in Fig. 5() gives the Norton current when the potentiometer is equl to zero. The voltmeter in Fig. 5() gives the Thévenin voltge when the potentiometer is equl to infinite (or not connect to the port). The Thévenin/Norton resistnce cn e otined from the structures in Fig. 5() or (). The equivlent resistnce is equl to the potentiometer resistnce which drops the port current from Norton current to one-hlf of it in Fig. 5() or the port voltge from Thévenin voltge to one-hlf of it in Fig. 5(). In order to otin experimentlly the prmeters of Thévenin/ Norton equivlent circuits y using the conventionl methods, the short-circuit current s Norton current nd the open-circuit voltge s Thévenin voltge re mesured. The port resistnce gives the Thévenin/Norton resistnce when ll independent sources re set to zero. Consequently the conventionl methods use more thn one topology nd tke long time. The method descried in ef. () uses test voltge source for Norton equivlent or test current source for Thévenin equivlent without requiring setting ll independent sources to zero. But, experimentl ppliction of the method is restricted ecuse of nonexistence physicl current Fig. 6. Circuit for Exmple source. The methods presented in efs. (,6) re only experimentl methods nd do not include ny eqution. Next three exmples re presented to verify nd evlute the proposed method. In order to otin the system equtions, stte vrile nlysis in the second exmple, mesh nlysis in the third exmple nd modified nodl nlysis in the fourth exmple hve een utilized. After connecting the test lod impednce,, into the output port of the circuit nd expressing the port voltge or port current, the equivlent circuit prmeters re otined simultneously. Exmple. Consider the circuit shown in Fig. 6 the test lod impednce,, is connected to the port terminls, nd. The stte equtions of the circuit in s-domin re: s [ ] UC (s) I (s) 0 C ( ) ZX Z X [ ] UC (s) I (s) [ ] 0 (s), cpcitor voltge (U C (s)) nd inductor current (I (s)) re the vriles of the method. et us rerrnge the system equtions s in the form of (3): s C ( ) ZX Z X s }{{} A [ ] UC (s) I (s) } {{ } X The determinnt of the coefficient mtrix is: [ 0 ] }{{} B (s) det(a) (s) s C s CZ X scz X Z X C ( ) The chrcteristic eqution,, is grouped ccording to s: (s) Z X X (s) [s C ] [s C sc ] From the expression of in () nd (3), the components, nd x, re determined s: (s) s C, s C sc After solving the system equtions, the port voltge nd the port current relting to the circuit re expressed s follows: I (s) I (s) Z X sc s C s (s) CZ X scz X Z X U (s) Z X I (s) Z X scz X s C s (s) CZ X scz X Z X It cn e esily understood tht the denomintors of the output vriles re equl to the chrcteristic eqution. et s rerrnge the expressions of the port current nd the port voltge 53 IEEJ Trns 6: (0)

6 E. KEEBEKE AND A. BEKI YIDIZ ccording to () nd (3): I (s) sc [s C ] Z X [s C sc ] (s) U (s) sc [s C ] Z X [s C sc ] (s) sc (s) The equivlent circuit prmeters re determined in terms of nd the components of the chrcteristic eqution. Actully, it mens tht the limit of the port voltge s pproches to infinite is equl to the Thévenin voltge: U th (s) lim U (s) Zx X (s) sc s C sc (s) At the sme time, the Thévenin voltge cn e directly otined from the generlized expression of the Thévenin voltge given in (6). The limit of the port current s the test lod pproches to zero gives the Norton current: J nor (s) lim I (s) Zx 0 (s) sc s C (s) The Norton current cn e directly otined from the generlized expression of the Norton current given in (4). Extrcting the test lod expression from the expressions of U or I, the elow equtions re otined in terms of U nd I, respectively: s C (s) [sc ] (s) U (s)[s C sc ] U (s) (s) sc (s) I (s)[s C ] I (s)[s C sc ] The Thévenin/Norton impednce is equl to the limit of the test lod s expression s the output voltge, U, pproches to one-hlf of its open circuit vlue (U oc ) or the output current, I, pproches to one-hlf of its short circuit vlue (I sc ). It mens tht the output voltge/current drops to hlf when the test lod impednce is equl to the Thévenin/Norton impednce: Z th (s) Z nor (s) lim lim U U th I Jnor (s) X (s) s C s C sc The result cn e lso otined directly from (33), the generlized expression of the Thévenin/Norton impednce. Exmple 3: Consider the mgnetic coupling circuit, shown in Fig. 7 the test lod impednce,, is connected to the port terminls, nd. Mesh equtions re: AX (s) BU (s), s s s sm sm s sm s s 3 sm s 3 sm A sc sc sm s 3 sm s 3, I (s) X (s) I (s), B 0, I (s) 0 sc U (s) [ (s)] Z X sc M 3 I I I C Fig. 7. Circuit for Exmple 3 The determinnt of the coefficient mtrix is: det(a) (s) (s) (s) The chrcteristic eqution,, is grouped ccording to s: (s) s 3 C [ ( 3 M ) M 3 ] s C ( 3 ) s( ) (s) s 4 C (M 3 ) s 3 3 C s s, (s) sc After solving the system equtions, the port current or port voltge relting to the circuit is expressed. In this exmple, the port current is used since the vriles of mesh nlysis re currents: I (s) s3 C (M 3 ) s 3 C s (s) (s) [s 3 C (M 3 ) s 3 C s ] (s) The prmeters of the equivlent circuits re otined y either pplying of the limit pproch step y step s in Exmple or using the generlized expressions given in Section 3. In this exmple nd next exmple, the generlized expressions re used in order to emphsis the systemtic of the method. The Thévenin voltge from (6) is s elow: U th (s) [s3 C (M 3 ) s 3 C s ] (s) x (s) x (s) x (s) s 3 C [ ( 3 M ) M 3 ] x (s) s C ( 3 ) s( ) The Norton current is equl to (4): J nor (s) (s) [s3 C (M 3 ) s 3 C s ] (s) s 4 C (M 3 ) s 3 3 C s s 54 IEEJ Trns 6: (0)

7 CHAACTEISTIC EQUATION-BASED COMPUTATION OF THÉVENIN AND NOTON EQUIVAENT CICUITS c C J C ki d Ji Fig. 8. Circuit for Exmple 4 The Thévenin/Norton impednce is equl to (33): Z th (s) Z nor (s) (s) s4 C (M 3 ) s 3 3 C s s x (s) x (s) Exmple 4: Consider the circuit shown in Fig. 8 the test lod impednce,, is connected to the port terminls, nd. Modified nodl equtions re: AX (s) BU (s) G sc / / sc G 0 / G / A sc kg sc 0, G kg 0 s G U (s) 0 0 U (s) 0 X (s) U c (s), B 0 0, U (s) U d (s) 0 I u (s) 0 [ ] Ji (s) (s) The determinnt of the coefficient mtrix is: det(a) (s) (s) (s) The chrcteristic eqution,, is grouped ccording to s: (s) s G G C sg C G G, (s) s G C s(kg G G G C ) G G, (s) sz X After solving the system equtions, the port current or port voltge relting to the circuit is expressed. In this exmple, the port voltge is used since the vriles of nodl nlysis re voltges. U (s) U (s) U (s) (s) [s G C s(kg G G G C ) G ]J i (s) [sg C ( sg )] (s) The Thévenin voltge from (6) is s elow: U th (s) s G C s(kg G G G C ) G s J i (s) G G C sg C G G sg C ( sg ) s (s) G G C sg C G G The Norton current is equl to (4): J nor (s) (s) s G C s(kg G G G C ) G s G C s(kg G G G C ) G G J i (s) sg C ( sg ) s (s) G C s(kg G G G C ) G G The Thévenin/Norton impednce is equl to (33): Z th (s) Z nor (s) (s) s G C s(kg G G G C ) G G s G G C sg C G G 5. Conclusions A new efficient nd systemtic pproch for determining prmeters of the Thévenin nd Norton equivlent circuits nd its exmple pplictions hve een presented in this pper. It llows ll equivlent circuit prmeters to otin simultneously from only one circuit topology. It is sufficient to connect test lod impednce to the output of circuit nd to express the port voltge or the port current y using ny formultion method. As result, the generlized expressions re formulted for otining systemticlly ll prmeters. The proposed pproch is independent from the nlysis method nd cn e pplied to ll possile ctive nd pssive circuit structures s lredy presented in the four exmple pplictions verifying the efficiency of the method explicitly. For future works, computer progrm out computtion of the prmeters cn e written y employing the proposed method. eferences () Thoms E, os AJ. The Anlysis nd Design of iner Circuits. 5th ed. John Wiley & Sons: New Jersey; 006. () Nhvi M, Edminister JA. Theory nd Prolems of Electric Circuits. 4th ed. McGrw-Hill: Ohio; 003. (3) Nilsson JW, iedel SA. Electric Circuits. Prentice Hll: New Jersey; 005. (4) Yildiz AB. Electric Circuits, Theory nd Outline Prolems, Prt II. Koceli University Press: Turkey; 006. (5) Corzz GC, Somed CG. Generlized Thévenin s theorem for liner n-port networks. IEEE Trnsction on Circuit Theory 969; 6(4): (6) Director SW, Wyne DA. Computtionl efficiency in the determintion of the Thévenin nd Norton equivlents. IEEE Trnsction on Circuit Theory 97; 9(): (7) Hjj IN. Computtion of the Thévenin nd Norton Equivlents. Electronics etters 976; (): (8) Sommriv AM. Thévenin s theorem: new formultion. IEEE 6th Interntionl Conference on Electronics, Circuits nd Systems (ICECS) ; : Cyprus, 999. (9) Boccletti CD, Sntini EG. Extended Thévenin equivlent circuits. Interntionl Symposium on Power Electronics, Electricl Drives, Automtion nd Motion (SPEEDAM), Itly, 008. (0) Mod MF. On Thévenin s nd Norton s equivlent circuits IEEE Trnsction on Eduction 98; E-5(3): IEEJ Trns 6: (0)

8 E. KEEBEKE AND A. BEKI YIDIZ () Hley SB. The Thévenin circuit theorem nd its generliztion to liner lgeric systems IEEE Trnsction on Eduction 983; E- 6(): () Jin M, Chn SP. A unified nd efficient pproch for determining Thévenin (Norton) equivlent circuits. IEEE Trnsction on Eduction 989; 3(3): (3) Bogrd TF, Brown JW. Experiments in Electronic Devices nd Circuits. Prentice Hll: New Jersey; 997. (4) Chtzrkis GE, Tortoreli MD, Tziols AD. Thevenin nd Norton s theorems: powerful pedgogicl tools for treting specil cses of electric circuits. Interntionl Journl of Electricl Engineering Eduction 003; 40(4): (5) Kiss P, Dn A. Novel nlyticl pproximtion method of frequency dependent Thévenin ımpednce. IEEE Proceedings, PowerTech, omni, 009. (6) Holder ME. Thevenin s Theorem nd lck ox. IEEE Trnsction on Eduction 009; 5(4): (7) Tsi SJ, Wong KH. On-line estimtion of Thévenin equivlent with vrying system sttes. IEEE Power nd Energy Society Generl Meeting Conversion nd Delivery of Electricl Energy in the st Century, Pittsurgh, PA, 008. (8) Gil B. Appliction of the generlized Thévenin theorem for solving symmetricl series fults. IEEE Proceedings of the First Interntionl Crcs Conference on Devices, Circuits nd Systems, Venezuel, 995. (9) Psini G, Montgn M, Grnelli GP. Inverse mtrix modifiction lemm nd Thévenin theorem for compensted network solutions. IEE Proceedings-Genertion, Trnsmission nd Distriution 999; 46(5): (0) Hoop D, ger AT, Tomssetti IE. The pulsed-field multiport ntenn system reciprocity reltion nd its pplictions time-domin pproch. IEEE Trnsction on Antenns nd Propgtion 009; 57(3): () Witherspoon SA, Chom J. The nlysis of lnced, liner differentil circuits. IEEE Trnsction on Eduction 995; 38(): Ersoy Keleekler (Non-memer) ws orn in Burs, Turkey in 980. He received the B.S. nd M.S. degrees in deprtment of electronics nd computer eduction from Koceli University, in 00 nd 006, respectively. He joined the Technicl Eduction Fculty of Koceli University s eserch Assistnt, in 004. He is currently working on his Ph.D. thesis t the deprtment of electronics nd computer eduction of Koceli University. His reserch study hs focused on wve propgtion in nisotropic, nonhomogenous, closed wveguides, nd computer-ided nlysis of electronic circuits. He is lso interested in teching electronics. Ali Bekir Yildiz (Non-memer) ws orn in Skry, Turkey in 970. He received the B.S. nd M.S. degrees in electricl engineering from Yildiz Technicl University, Istnul, in 99 nd 993, respectively, nd the Ph.D. degree in electricl engineering from Koceli University, Koceli in 998. Since 999, he hs een on Engineering fculty, electricl engineering deprtment t Koceli University, Turkey, he is currently Asc. Prof. Dr. He pulished two ooks relting to electric circuits. His reserch interests re in computer-ided nlysis nd modeling of ctive nd pssive circuits, modeling of semiconductor switches, nlysis of power electronic circuits, modeling nd nlysis of DC mchines. 56 IEEJ Trns 6: (0)