MAS Output LDO Voltage Regulator IC

Size: px

Start display at page:

Download "MAS Output LDO Voltage Regulator IC"

Gwenda Bates
5 years ago
Views:

DA9122.4 MAS9122 3-Output LDO Voltage Regulator IC DESCRIPTION MAS9122 is a three-output voltage regulator.

1 DA MAS Output LDO Voltage Regulator IC DESCRIPTION MAS9122 is a three-output voltage regulator. It is designed for three different output voltages, which can be modified through a mask option. Regulators operating mode is controlled by two enable/disable pins. The circuit consists of a bandgap voltage reference, an error amplifier, a current limit circuit and a thermal protection circuit. Three Low Dropout Voltage Regulators Very Low Noise: 25 µvrms High Ripple Rejection: 63 db Very Low Crosstalk Low Ground Pin Current Regulator Enable/Disable Control MAS9122 features very low ground pin current: typically less than 1.5 µa sleep mode current and typical 125 µa for one regulator in active mode. Excellent noise and PSRR performance enables the use of MAS9122 in high precision portable devices. Low crosstalk between regulators provides an area efficient solution compared to single regulators. FEATURES APPLICATIONS Three Regulators at 135 ma, 7 ma and 5 ma Output Options 2.7, 2.85 and 3. V, see Ordering Information p. 12 Low Noise: 2 µvrms Typical and 3 µvrms Maximum for All Regulators over Frequency Range 1 Hz 1 khz Fast Dynamic Response Output Voltage Accuracy < ±2. % MSOP-8 Package Systems Requiring Stabilized Power in Separate Blocks Cordless Phones Mobile Phones Portable Systems Battery Powered Systems BLOCK DIAGRAM VIN ENA & LDO_A 135 ma OUT A ENBC & LDO_B 7 ma OUT B & LDO_C 5 ma OUT C ORgate Temperature Protection & Bandgap Reference VREF GND 1 (12)

2 9122 AXWW DA PIN CONFIGURATION OUTA 1 8 OUTB Top View OUTC 2 7 VIN ENBC 3 6 GND ENA 4 5 VRF Top Marking Information: AX = voltage version, see p.12 Ordering information WW = week PIN DESCRIPTION Pin Name Pin Type Function OUTA 1 O 135 ma Regulator Output OUTC 2 O 5 ma Regulator Output ENBC 3 I Enable for Regulators B and C ENA 4 I Enable for Regulator A VREF 5 O Reference Voltage: Pin for Bypass Capacitor GND 6 P Ground VIN 7 P Positive Supply Voltage OUTB 8 O 7 ma Regulator Output G = Ground, I = Input, O = Output, P = Power ABSOLUTE MAXIMUM RATINGS All Voltages with Respect to Ground Parameter Symbol Conditions Min Max Unit Supply Voltage V IN.3 6 V Voltage Range for All Pins.3 V IN +.3 V ESD Rating HBM 2 kv Junction Temperature T Jmax 175 (limited) Storage Temperature T S Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but will not be destroyed. RECOMMENDED OPERATING CONDITIONS o C o C Parameter Symbol Conditions Min Max Unit Supply Voltage V IN V OUT(NOM) V Operating Junction T J C Temperature Operating Ambient Temperature T A C 2 (12)

3 DA ELECTRICAL CHARACTERISTICS Thermal Protection T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. Threshold High T H Threshold Low T L The hysteresis of 1 o C prevents the device from turning on too soon after thermal shut-down. o C o C Control Pin Parameters T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. Input Voltage ENA, ENBC.3 V IN +.3 V ON-state OFF-state 2. Note 1.3 If CTRL-pin is not connected, the particular regulator(s) is/are in OFF state (9 kω pull-down resistor to ground). Note 1: Contact MAS Oy for a version with enable voltage of 1.15 V ON-state,.6 V OFF-state. Current Parameters T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. LDO_A Continuous Output Current I OUTA 135 ma LDO_B Continuous Output Current I OUTB 7 ma LDO_C Continuous Output Current I OUTC 5 ma Short Circuit Current for LDO_A I SHORTA 35 ma Short Circuit Current for LDO_B I SHORTB 265 ma Short Circuit Current for LDO_C I SHORTC 23 ma Ground Pin Current I GND(OFF) I OUT = A, V ENA,ENBC <.3 V, 2 4 µa V IN = 3.6 Ground Pin Current I GND(ONA) I OUT = A, V ENA > 2 V, 125 µa V ENBC <.3 V, V IN = 3.6 Ground Pin Current I GND(ONBC) I OUT = A, V ENA <.3 V, 17 µa V ENBC > 2 V, V IN = 3.6 Ground Pin Current I GND(ONABC) I OUT = A, V ENA, ENBC > 2 V V IN = µa 3 (12)

4 DA Voltage Parameters T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. Output Voltage: Mask option for 2.85 V V OUTA Max I OUT = 135 ma % % V V OUTA,B,C Max I OUTA = 1 ma, Max I OUTB = % % V 7 ma, Max I OUTC = 5 ma LDO_A Dropout V DROPA I OUTA = 135 ma 22 mv Voltage I OUTA = 1 ma 18 LDO_B Dropout V DROPB I OUTB = 7 ma 165 mv Voltage LDO_C Dropout Volt. V DROPC I OUTC = 5 ma 15 mv External Capacitors T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. Output Capacitors for µf all Regulators C OUTA,B,C.8 1 Effective Series Resistance ESR Ω Bypass Capacitor C BYPASS 1 nf Power Dissipation T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. Junction to Case Thermal R JC 39 C/W Resistance Junction to Ambient Thermal Resistance R JA typical PC board mounting, still air 26 C/W TJ(MAX) TA Maximum Power Dissipation P d any ambient temperature PdMAX = mw R JA Note 2 Note 2: T J(MAX) denotes maximum operating junction temperature (+125 C), T A ambient temperature, and R JA junction-to-ambient thermal resistance (+26 C/W). Load Regulation T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. Load Regulation LDO_A ma < I OUT < 135 ma 22 5 mv ma < I OUT < 1 ma 22 3 Load Regulation LDO_B ma < I OUT < 7 ma mv Load Regulation LDO_C ma < I OUT < 5 ma mv Line Regulation T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. Line Regulation for all LDOs I OUT = I MAX,V IN from mv V OUT(NOM) +.35 V to 5.3 V 4 (12)

5 DA PSRR T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. PSRR for all LDOs I OUT = Max I OUT V IN = 3.6 V f = 1 khz f = 1 khz db Noise and Crosstalk T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. Noise Voltage for all LDOs V NO 1 Hz < f < 1 khz 25 3 µvrms Dynamic Parameters T A = -4 C to +85 C, typical values at T A = +27 C, V IN = 4.5 V, I OUT = 1. ma, C IN = 1. µf, C L = 1. µf, C BYPASS = 1 nf, V CTRL = 2. V, unless otherwise specified. Start-up Delay (from enabling V ENA from <.3 V to > 2. V, 25 µs LDO_A to 9% * V OUT(NOM), other LDOs at ON state) (Note 3) V ENBC > 2. V, I OUT = Max I OUT, C OUTA = 1 µf Overshoot V ENA from <.3 V to > 2. V, V ENBC > 2. V, I OUT = Max I OUT, 1 % Settling Time (from 9% * V OUT(NOM)A to max ±.1% fluctuation) C OUTA = 1 µf V ENA from <.3 V to > 2. V, V ENBC > 2. V, I OUT = Max I OUT, C OUTA = 1 µf, w/o C BYPASS 2 µs Note 3: When all regulators are disabled the start-up delay is a function of a bypass capacitor. Typically.5 ms for 1 nf capacitor. CTRL 5% Figure 1. Definitions of start-up delay, overshoot and settling time. overshoot 9% VOUT start-up delay settling time 5 (12)

6 DA APPLICATION INFORMATION VIN = V OUT(NOM) +.25 V V 1 uf OUTA VIN OUTB 1 uf MAS9122 OUTC 1 uf ENA VREF 1 uf ENBC GND 1 nf See also table External Capacitors on p. 4. FUNCTIONS Reference voltage The device is supplied with V OUT(NOM) +.25 V to 5.3 V battery under normal conditions. An internal bandgap voltage reference is routed via 2 kohm resistor to an external pin, where a filter capacitor can be connected in order to reduce noise level of all regulators. The startup time of the reference voltage is then determined by the value of the bypass capacitor at pin VREF. Enable pins Each regulator can be enabled/disabled by two enable pins ENA and ENBC. Pin ENA controls regulator LDO_A and pin ENBC controls both regulator LDO_B and LDO_C. If both enable pins are forced low, the whole circuit goes into power saving sleep-mode. In the table below all functional modes are presented. Regulators The device contains three low dropout CMOS regulators, with maximum output currents of 135 ma, 7 ma and 5 ma. Three different output voltage options are available by mask option: 2.7 V, 2.85 V and 3. V. Logic Table for Enable Inputs ENA ENBC LDO_A LDO_B LDO_C VREF 1 1 ON ON ON ON 1 ON OFF OFF ON 1 OFF ON ON ON OFF OFF OFF OFF 6 (12)

7 DA TYPICAL PERFORMANCE CHARACTERISTICS 4 MAS9122 Line transient response MAS9122 Ouput noise density VOUT (mv) VIN (V) Noise spectral density (nv/hz Hz) ½ ) Time (5 µs/div) Vout Vin Frequency (khz) Figure 2. LDO_C line transient for a supply voltage change of 1 V, V OUT = 2.8 V. Figure 3. Regulator output noise density MAS9122 V OUT temperature dependency 2 MAS9122 LDO_A load transient response VOUT (V) 2.85 VOUT (mv) IOUT (ma) Temperature ( C) -5 Time (5 µs/div) Vout Iout Figure 4. Regulator output voltage temperature dependency. Figure 5. LDO_A load transient response to maximum output current with 1 µs steps (I OUT(MAX) = 1 ma). NOTE: With 135 ma of current the overshoot values and lengths will grow by 3% compared to 1 ma of current. 2 MAS9122 LDO_B load transient response 35 2 MAS9122 LDO_C load transient response VOUT (mv) IOUT (ma) VOUT (mv) IOUT (ma) Time (5 µs/div) Time (5 µs/div) Vout Iout Vout Iout Figure 6. LDO_B load transient response to maximum output current with 1 µs steps. Figure 7. LDO_C load transient response to maximum output current with 1 µs steps. 7 (12)

8 DA TYPICAL PERFORMANCE CHARACTERISTICS LDO_A Output voltage (V) MAS9122 LDO_A start-up, overshoot and crosscoupling to LDO_B (V OUTB = 2.85 V) Time (5 µs/div) VoutA VoutB LDO_B Output LDO_B voltage Output change volt (mv) Dropout voltage (mv) MAS9122 Dropout voltage temperature dependency with max I OUT Temperature ( C) LDO_A LDO_B LDO_C Figure 8. LDO_A start-up, overshoot and cross-coupling to LDO_B. Figure 9. Dropout voltage temperature dependency with maximum output current. Ground pin current (µa) MAS9122 Ground pin current vs. temperature Temperature ( C) max load min load Load regulation (mv) MAS9122 Load regulation vs. temperature Temperature ( C) LDO_A LDO_B LDO_C Figure 1. Total ground pin current vs. temperature. Figure 11. Load regulation vs. temperature. 4 MAS9122 Short circuit current variation vs. supply voltage MAS9122 LDO_A Ground pin current vs. output current 12 Short circuit current (µa) Supply voltage (V) LDO_A LDO_B LDO_C Ground pin current (µa) Output current (ma) Figure 12. Short circuit current variation vs. supply voltage. Figure 13. LDO_A ground pin current vs. output current. 8 (12)

9 DA PACKAGE (MSOP-8) OUTLINE E1 E F Land Pattern Recommendation P Q L Gage plane R1 R A A N A1 b D e A2 A G M c b1 (b) Section A - A c1 Symbol Min Nom Max Unit A 1.1 mm A1.15 mm A mm b mm b mm c.8.23 mm c mm D 3. BSC mm E 4.9 BSC mm E1 3. BSC mm e.65 BSC mm F 4.8 mm G.65 mm L (Terminal length for mm soldering) M.41 mm N 1.2 mm P 8 Q.25 BSC mm R.7 mm R1.7 mm Dimensions do not include mold or interlead flash, protrusions or gate burrs. All measurement according to JEDEC standard MO (12)

10 DA SOLDERING INFORMATION Resistance to Soldering Heat According to RSH test IEC /2 2*22 C Maximum Reflow Temperature 235 C Maximum Number of Reflow Cycles 2 Seating Plane Co-planarity max.8 mm Lead Finish Solder plate µm, material Sn 85% Pb 15% EMBOSSED TAPE SPECIFICATIONS P1 P2 PO DO T E W F BO A AO User Direction of Feed D1 Section A-A KO Pin 1 Designator Dimension Min/Max Unit Ao 5. ±.1 mm Bo 3.2 ±.1 mm Do /-. mm D1 1.5 min mm E 1.75 mm F 5.5 ±.5 mm Ko 1.45 ±.1 mm Po 4. mm P1 8. ±.1 mm P2 2. ±.5 mm T.3 ±.5 mm W /-.1 mm 1 (12)

11 DA REEL SPECIFICATIONS W 2 A D Tape Slot for Tape Start C N B W 1 Carrier Tape Cover Tape End Start Trailer Components Leader Dimension Min Max Unit A 33 mm B 1.5 mm C mm D 2.2 mm N 5 mm W 1 (measured at hub) mm W 2 (measured at hub) 18.4 mm Trailer 16 mm Leader 39, mm of which minimum 16 mm of empty carrier tape sealed with cover tape Weight 15 g 11 (12)

12 DA ORDERING INFORMATION Product Code Product Top Marking (ax) Package Comments MAS9122ASM2-T 3 x 2.7 V LDO Voltage Regulator IC A2 MSOP-8 T&R/4k/reel MAS9122ASM3-T 3 x 2.85 V LDO Voltage Regulator IC A3 MSOP-8 T&R/4k/reel MAS9122ASM4-T 3 x 3. V LDO Voltage Regulator IC A4 MSOP-8 T&R/4k/reel For more voltage options contact Micro Analog Systems Oy. LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O.Box 51 FIN-2771 Espoo, FINLAND Tel. (9) Tel. Int Telefax info@mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 12 (12)

13 Pour plus d'information, merci de contacter le distributeur en France : ISC COMPOSANTS 1 Avenue du Président Pompidou BP Rueil Malmaison Cedex Tel : Fax : contact@isc-composants.com

MAS Output LDO Voltage Regulator IC

MAS Output LDO Voltage Regulator IC DA.8 MAS 2-Output LDO Voltage Regulator IC Dual Regulator: 2 15 ma Very Low Crosstalk Low Dropout: 7 mv High Ripple Rejection: 62 db Low Noise: 3 µvrms Stable with Low-ESR Output Capacitors Separate Enable/Disable