2017 IEEE 67th Electronic Components and Technology Conference

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1 2017 IEEE 67th Electronic Components and Technology Conference A Unique Temporary Bond Solution Based on a Polymeric Material Tacky at Room Temperature and Highly Thermally Resistant Application Extension from 3D-SIC to FO-WLP Alain Phommahaxay, Goedele Potoms, Julien Bertheau, Pieter Bex, Fabrice Duval, Arnita Podpod, Teng Wang, Greet Verbinnen, Gerald Beyer, Erik Sleeckx, Eric Beyne imec Kapeldreef 75 Leuven, Belgium phomma@imec.be Atsushi Nakamura Fujifilm Electronic Materials Europe N.V. Zwijndrecht, Belgium Yoshitaka Kamochi Fujifilm Corporation Shizuoka, Japan Abstract Among the technological developments pushed by the adoption of Through Silicon Vias and 3D Stacked IC technologies, wafer thinning on a temporary carrier has become a critical element in device processing over the past years. First generation of adhesive materials enabled the integration of the first devices at the expense of capping the thermal budget. Hence new generation materials are being explored to overcome this limitation and further bring the process complexity down. Keywords: Wafer bonding, Wafer thinning, strength, Temporary bond adhesive, Thin wafer handling, Wafer molding, Die attachment I. INTRODUCTION Thin wafer handling has become one of the cornerstones of 3D Stacked IC manufacturing over the past years. Bonding a device wafer to a temporary process carrier with adhesive is one of the process steps that has been studied extensively. First generation materials, including thermoplastics, laser-degradable or chemically dissolvable glues, are readily available on the market and already enable early 3D demonstrator processing. Yet, when it comes to building additional structures on the wafer backside after thinning, most of the usual process steps involving high temperature have to be adapted. This is even more critical for processes performed in deep vacuum environment (ex: PVD, CVD). This combination of heat and vacuum environment pose a great challenge for temporary bond materials. Up to now backside processing temperatures have been tailored and lowered to match the properties of the various temporary bond adhesives [1-2]. Hence processes are usually kept below 250 C in air or even below 200 C when dealing with deposition in vacuum. Imec and Fujifilm have collaborated over the past few years in the development of a novel multifunctional polymeric material that incorporate an adhesive and release function combined, thus enabling process complexity reduction. First demonstration of a via-middle integration flow including high topography Cu pillar has been previously presented [3]. Since then, further work has been carried out in order to answer the need for higher temperature resistant materials but also integrate the temporary material with microbumps. The present contribution will therefore deal with the thermal performance of such temporary bond solution and the process impact on scaled down microbumps. In a second part, some unique features such as the adhesion at room temperature will be also discussed. One can envision the reuse the material to Fan Out-WLP application. II. THINNING PROCESS FOR 3D-SIC Among the different possible 3D integration schemes, this study will focus on the via-middle approach followed at imec where Cu TSVs are formed during the BEOL process as illustrated in Fig. 1 [4]. After formation of the TSVs, and completion of the front side process as shown on a), the wafer is edge trimmed (situation b)) to avoid wafer edge chipping during subsequent grinding. The device wafer is then bonded to a carrier wafer with temporary adhesive as shown in step c). The TSVs are subsequently revealed from the wafer backside after thinning by grinding (step d)). Backside layers, including passivation, are then built on top of the thinned device substrate. Upon completion of the process, the bonded stack is then attached to a dicing tape for mechanical carrier debonding (steps e) and f)). Finally, the remaining adhesive is removed in step g) by solvent cleaning or mechanical detaping as previously demonstrated [3] /17 $ IEEE DOI /ECTC

2 a) Device wafer after frontside processing b) Wafer edge trimming The device wafers have been then bonded to the silicon carrier wafers using the Suss CB300 bond chamber with temperature ranging from 200 C to 260 C and force in the 20kN range. The bond quality has been subsequently assessed using a Scanning Acoustic Microscope, AutoWafer300 from PVA Tepla Analytical Systems. The results depicted in Fig. 2. indicate that void-free bonding has been achieved. The bond uniformity and Total Thickness Variation, TTV of the adhesive layer, has then be measured by IR-Time of Flight using a Semdex 302 from Sentronics Metrology. The radial plot of adhesive thickness can be found in Fig. 3. A TTV value of about 2μm has been achieved. c) Temporary wafer bonding d) Wafer thinning and backside processing e) Transfer to dicing tape Figure 2. Scanning Acoustic Microscope inspection after bonding f) debonding g) removal Figure 1. Schematic process flow from wafer thinning to debonding In this study, we are focusing on processing wafers with low topography (i.e. microbumps with height below 10μm) contrary to the previous contribution with 50μm tall Cu pillars [3], hence a thinner adhesive layer with target thickness of 30μm has been used. This layer is first spun on top of a silicon carrier substrate using the Suss SC300 coat module of an XBS300 bond cluster. Thickness (um) Figure 3. Total Thickness Variation of the adhesive layer after wafer bonding 1830

3 a) After 5min at 260 C in vacuum (10-4 mbar) Figure 4. Total Thickness Variation of the device wafer after thinning to 50μm The device wafers have been subsequently thinned to 50μm by mechanical grinding. TTV of the substrate has been measured again by IR-TOF method. The measurement across a 300mm wafer is shown in Fig. 4. TTV value of about 2μm has been reached. III. THERMAL SURVIVAVILITY VERIFICATION b) After 5min at 300 C in vacuum (10-4 mbar) Pressure (mbar) Temperature ( C) In order to assess the thermal survivability and performance of the temporary bond material, full thickness bonded wafers have been submitted to a heat cycle in vacuum using the Suss CB300 bond chamber. Following the previous contribution [3], where the materials have shown no defect at 200 C in mild vacuum conditions (in mbar range) and 250 C at atmospheric pressure, the current study is pushing it further. Indeed, the wafers have been submitted to deeper vacuum levels in the 10-4 mbar range and to temperature ranging from 260 C to 350 C as shown in Fig. 5. For all cases, the SAM inspection in Fig. 6 does not reveal any degradation of the temporary bond adhesive. c) After 5min at 350 C in vacuum (10-4 mbar) Figure 6. Scanning Acoustic Microscope inspection after various thermal treatment in vacuum Figure 5. Temperature and pressure profile used to assess the thermal and vacuum stability of the material 1831

4 IV. DEBONDING IMPACT ON MICROBUMPS In order to further characterize the material and process impact on frontside microbumps, selected wafers have been pre-inspected, bonded with adhesive and then debonded. Then adhesive has been subsequently detaped from the device wafer. The microbumps have been finally reinspected by Scanning Electron Microscope. The photographs presented in Table I, for two different type of microbumps: with and without tin solder, do not demonstrate significant process impact on the microbumps morphology. Die Die Die Figure 7. Schematic of die placement on temporary silicon carrier TABLE I. MICROBUMPS BEFORE AND AFTER BONDING & DEBONDING Bump type Before temporary bonding After debond & adhesive removal by detaping Cu 8.6μm diameter 20μm pitch Figure 8. Photograph carrier populated with dies on a temporary adhesive Cu/Ni/Sn 8.6μm diameter 20μm pitch V. MATERIAL TECHNOLOGY EXTENSION TO FO-WLP In order to further characterize the material bonding properties, various experiments have been conducted by Die to Wafer (D2W) attachment on top of the temporary adhesive as depicted in Fig. 7. Force and temperature have been varied during the placement of 5mm x 5mm dies on wafer using a Besi Datacon 8800 flip chip bonder. The die attachment conditions have been summarized in Table II. A typical picture of attached die on wafer is shown in Fig. 8. The adhesion for each attachment condition has been further assessed by shearing the dies off from the carrier substrate. The results have been summarized in Fig. 9 and show the impact of the temperature and force parameters on the die strength. TABLE II. DIE ATTACHEMENT CONDITIONS Parameter Condition Time 1s Force 10 to 30N Temperature 20 to 200 C One can notice a remarkable phenomenon in Fig. 9 a). Indeed, all temperature conditions have led to dies being attached to the adhesive substrate with shear strength above 20N. Room temperature attachment is a pretty unique feature considering that the material is rated to withstand process temperature above 200 C. Tacking dies onto common adhesive material would usually require partial remelt of the material and therefore a high temperature process, typically above 100 C. The adhesion strength of the Fujifilm temporary adhesive is also surprisingly independent of the attachment force as shown in Fig. 9 b). More analysis will be carried out in the future in order to further characterize this phenomenon. 1832

5 Shear force (N) Shear force in function of placement temperature for placement force of 20N Temperature ( C) a) Influence of the placement temperature Mold a) Molding on temporary silicon carrier Mold b) Transfer to dicing tape Mold c) Temporary carrier debonding and adhesive removal Figure 10. Schematic process flow of application extension to wafer overmolding Shear Force (N) b) Influence of the placement force Figure 9. Shear strength of dies placed with various conditions on Fujifilm Temporary Being able to attach dies at low temperature or even room temperature enables new field of application for this type of temporary adhesive. Indeed, the schematic shown in Fig. 7. is directly comparable to the chip first approach for wafer reconstruction by molding [5-6]. Hence imec and Fujifilm have explored the alternative use of the adhesive developed for temporary bonding into the field of wafer overmolding. This present quite some challenge due to the higher level of wafer stress handling by the adhesive material. In order to assess the feasibility of such process, we have therefore submitted substrates coated with adhesive to the process steps described in Fig. 10. The temporary bond material has been overmolded with a 200μm thick mold cap. No delamination has been noticed after molding nor after post mold cure for few set of mold materials. Figure 11. Photograph of a 200μm thin mold wafer after debonding and adhesive removal The temporary bond material can therefore withstand the stress of a full surface overmolding, a worst case scenario. Further experiment included the separation of the mold substrate from the carrier wafer using a direct mechanical debond approach similar to the one used in classical temporary wafer debonding as depicted in Fig

6 VI. CONCLUSIONS The properties of a single material temporary bond solution from Fujifilm have been further explored. This unique polymeric material does not only offer an adhesive and release function combined, allowing thin wafer mechanical debond, it also features interesting properties such as tackiness to silicon dies at room temperature. This polymeric material being in addition resistant to harsh vacuum and heat conditions, up to 350 C, it provides interesting options for its applications to FO-WLP processing, including wafer reconstruction by overmolding. ACKNOWLEDGMENT The authors would like to thanks Walter Spiess, Hans Mathee, Stefan Lutter from Suss Microtec, Lan Peng, Fumihiro Inoue, Philip Nolmans, Bram De Loore, Dieter Cuypers, Ingrid Demonie, Wim Elen from imec for their support during the experiments. REFERENCES [1] A. Jourdain, T. Buisson, A. Phommahaxay, M. Privett, D. Wallace, S. Sood, P. Bisson, E. Beyne, Y. Travaly, B. Swinnen, 300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications, 2010 IEEE International 3D Systems Integration Conference (3DIC), Munich, 2010, pp [2] J. Lee; J. Seetoh; H. Yu Li; V. Lee; Y. Chen Yeo, G. Kian Lau, K. Hwa Teo, S. Gao, Compatibility of Dielectric Passivation and Temporary Bonding Materials for Thin Wafer Handling in 3-D TSV Integration, in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 12, pp , Dec [3] A. Phommahaxay, A. Nakamura, A. Jourdain, G. Verbinnen, Y. Kamochi, I. Koyama, Y. Iwai, M. Sawano, S. Tan, A. Miller, G. Beyer, E. Sleeckx, E. Beyne, Demonstration of a novel low cost single material temporary bond solution for high topography substrates based on a mechanical wafer debonding and innovative adhesive removal, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, 2015, pp [4] A. Jourdain, T. Buisson, A. Phommahaxay, A. Redolfi, S. Thangaraju, Y. Travaly, E. Beyne, B. Swinnen, Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, 2011, pp [5] M. Brunnbauer, E. Fürgut, G. Beer and T. Meyer, Embedded wafer level ball grid array (ewlb), th Electronics Packaging Technology Conference, Singapore, 2006, pp [6] H. S. Ling, B. Lin, C. S. Choong, S. D. Velez, C. T. Chong and X. Zhang, Comprehensive Study on the Interactions of Multiple Die Shift Mechanisms During Wafer Level Molding of Multichip- Embedded Wafer Level Packages, in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 4, no. 6, pp , June