IEEE ASIC/SOC Conference, September 2000, Washington, D.C.

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1 DESIGN AND SYNTHESIS OF BUILTIN SELFTESTABLE TWODIMENSIONAL DISCRETE COSINE TRANSFORM CIRCUITS Hn Bin Kim Sun Microsystms, Inc. 90 Sn Antonio Ro Plo Alto, CA 940 Emil: Don Sm H Virini Tch VLSI for Tlcommunictions (VTVT) Brly Dpt. of Elctricl n Computr En. Virini Tch, Blcksbur VA 406 Emil: h@vt.u Wb: ABSTRACT W prsnt sin of twoimnsionl (D) iscrt cosin trnsform (DCT) circuit with builtin slftst (BIST) cpbility. Aftr moifyin n xistin fst D DCT lorithm to mk it mor flxibl, w synthsiz th t pth n th controllr usin our hihlvl BIST synthsis tool n incorport scn sin to othr mouls. Our sin chivs hih fult covr t smll cost of r ovrh n systm prformnc rtion. I. INTRODUCTION Builtin slftst (BIST) mbs tst pttrn nrtor () n sintur ristr (SR). BIST hs bcom populr for loic circuit tstin s wll s mb mmory tstin. A hihlvl BIST synthsis tool nrts t pth n controllr in th ristrtrnsfr (RT) lvl with BIST cpbility by rconfiurin xistin ristrs. A hihlvl BIST synthsis is ffctiv for tstin t intnsiv circuits, spcilly DSP (Diitl Sinl Procssin) circuits. In this ppr, w prsnt sin of twoimnsionl ( D) iscrt cosin trnsform (DCT) circuit with builtin slftst (BIST) cpbility. Th DCT lorithm is wily us to comprss ims. It is, for xmpl, mploy in JPEC n MPEC. Our sin procur is s follows: W moifi n xistin onimnsionl (D) DCT lorithm first n thn ppli our hihlvl BIST synthsis tool [] to nrt t pth n controllr with BIST. W sin othr mouls (such s I/O intrfc mouls n mmory trnsposition moul) mnully to implmnt D DCT circuit n thn incorport scn sin to th mouls. II. BACKGROUND A. OnDimnsionl DCT Alorithm Sinc DCT is sprbl trnsformtion procss, th D DCT cn b prform by two sprt D DCT procsss: D DCT in th row irction follow by D DCT in th column irction. Svrl implmnttions opt this pproch u to its simpl structur n low hrwr complxity [],[]. Howvr, th pproch rquirs trnsposition mmory to stor n to rrrn th squnc of t for th scon D DCT; this rs of th prformnc in sp. A iffrnt D DCT implmnttion, prsnt in [4], limints th n for trnsposition mmory. It improvs th prformnc t th cost of hihr circuit complxity. W us th formr pproch to implmnt th D DCT, which prforms in thr stps: D DCT, n thn mmory trnsposition follow by nothr D DCT. Th formul for th D DCT is ivn blow: N X (0) = x( n) () N n=0 N (n ) kπ X ( k) = x( n) cos, k=,, 7 () N n= 0 N whr x(n) rprsnts pixl vlu, X(k) rprsnts th trnsform vlu, n N is 8 for th 8 8 block siz. B. Fst DCT Alorithm Chn t l. propos mtho to improv th oriinl DCT formul scrib bov [5]. Th improv on hs fwr oprtions to incrs th sp n to ruc th circuit complxity. Chn t l s mtho is known to b on of th fstst DCT lorithms n is prtly mploy in our implmnttion. W scrib Chn's lorithm brifly blow. An Npoint D DCT lorithm involvs N N mtrix clcultions. Th N N mtrix clcultions in qutions () n () cn b compos into th two sts of qutions shown in () n (4) for N=8 by inspction [],[5]. Th first st contins vn inx trms n th scon st th o inx trms. Th composition rucs th numbr of multiplictions from N to N /, which rucs 64 multiplictions to multiplictions for N=8. It is importnt to not tht th composition proucs th sm rsult s th oriinl formul fin in [] n []. i

2 X = ( ( (0 4) ) X ) c X X (6) f X = ( ( ( 5) ) b X ) X X (7) f c b f c b x(0) x(7) c x() x(6) x() x(5) f x() x(4) x(0) x(7) x() x(6) x() x(5) b x() x(4) If th twolvl multiply structur is convrt to multipllvl on by rrrnin oprtions, th numbr of multiplictions is furthr ruc to. Rfr to [5] for tils of th mtho. III. DESIGN OF D DCT A. Optimiztion of D DCT Alorithm Th fst DCT lorithm scrib in th prvious sction rquirs mtch invrs DCT (IDCT) lorithm. Tht is, if t r comprss usin th nrl D DCT lorithm fin in qutions () n (), th fst IDCT lorithms cnnot b us for comprssion. To voi th incomptibility problm, w moifi th lorithm in our sin, which incrss th numbr of oprtions slihtly. Th t flow rph shown in Fi. is th moifi DCT lorithm mploy in our implmnttion. It hs th sm structur s Chn s lorithm only for vninx trms, which rquir iht multiplictions. Th numbr of multiplictions rquir for oinx trms rmins th sm (which is ) s spcifi in qution () n (4). Th totl numbr of multiplictions ncssry for our implmnttion is 4, whrs it is for Chn s lorithm. x X b b b f c c f b () (4) W ppli our hihlvl BIST synthsis tool cll ADVBIST_h to th t flow rph in Fi. n nrt RTlvl t pth n controllr []. B. Structur n Oprtion of D DCT Circuit Fi. shows th block irm of D DCT circuit. Ech row of n 8 8 im block is lo srilly throuh DIN port of sriltoprlll (srpr) convrsion moul, n D DCT oprtion is prform for th row. Th rsult is stor in th trnsposition mmory. Upon compltly procssin th iht rows, D DCT oprtions r prform column by column in th trnsposition mmory. Th rsult of ch column D DCT oprtion is outputt srilly throuh DOUT port of prllltosril (prsr) convrsion moul. SEN DIN Controllr SEN PEN ISEL SEL REN srpr 8x ISEL Trns. Mmory D DCT SEL REN PEN 8x prsr Fiur : Block irm of our D DCT circuit DOUT Fi. shows th rchitctur for our D DCT t pth n th controllr. Th multiplxrbs rchitctur is mploy for th t pth, n finit stt mchin (FSM) is us for th controllr. Th systm is clock by sinl systm clock. CLK TEST BIST ctlm rn Controllr (FSM) in[0:5] out[0:5] R R BIST Moul Moul Dt Pth Fiur : Architctur for our D DCT circuit B[0:] S[0:] SIN SOUT Fiur : Dt flow rph of D DCT lorithm ii

3 IN0 IN IN7 0,0 0, 0,7,0,,7 7,0 7, 7,7 Fiur 4: Schmtic of th trnsposition mmory OUT0 OUT OUT7 Th structur of trnsposition mmory is shown in Fi. 4. A trnsposition mmory consists of n 8 8 ristr rry in which ch ristr is bit lon. Dt r fill into th rry in rowwis from top, n r mpti in columnwis in th riht si. Two control sinls, n, trmin th irction of th t movmnt. IV. DESIGNFORTEST TECHNIQUES APPLIED A. s n SRs W implmnt s shown in Fi. 5 by moifyin builtin loic block obsrvr (BILBO) [6]. Our hs thr mninful functions such tht norml oprtion, scn, n tst pttrn nrtion s shown in Tbl. Th mjor iffrnc btwn our n th oriinl BILBO is tht th inputs Z 5 Z 0 r block for our in tst pttrn nrtion mo; this is ncssry for psuornom pttrn nrtion. W us th oriinl BILBO for sintur nlysis. B B 0 S i 0 MUX Z 5 Z 4 Z Z Z Z 0 Q 5 Q 4 Q Q Q Q 0 S o B. Tstin of th Dt Pth W fr scription on tstin of t pth mouls to Sction V, which lso covrs xprimntl rsults msur from th lyout. C. Tstin of th Trnsposition Mmory W im to tst stuckt fults of th ristrs in th trnsposition mmory. Our pproch is to mrch throuh ll0pttrns to tct stuckt fults n thn ll pttrns to tct stuckt 0 fults. Aftr tst pttrns r scnn into th ristrs in th rihtmost column, ristr (i, j) copis from its lft nihbor ristr (i, j) on vry clock in th mmory tstin mo; th ristrs in th rihtmost column r copi into scn ristrs in th t pth moul. Th oprtion of th tstin procss is s follows. First, ll0pttrns r scnn into th ristrs in th trnsposition mmory moul, whos ristrs r sh in Fi. 4. Nxt, iht clocks r ppli to th moul in th mmory tstin mo. Th pttrns mrch throuh th rry n r cptur in th output ristrs. Aftr switchin to th scn mo, th contnts of th output ristrs r scnn out for xmintion. Th schm chivs 00 % stuckt fult covr. D. Tstin of th Controllr Th controllr circuit consists of 9bit countr n n ssocit combintionl loic. Th combintionl loic rcivs th contnt of th countr n nrts 66 control sinls. Th countr srvs s in our BIST mo. Tst rsponss on th control sinls r compct in spc to outputs n thn comprss in tim usin two xistin SRs in th t pth. Fi. 6 shows th structur of th controllr ftr incorportion of BIST. Th XOR ts in th lft MISR (Multipl Input Sintur Ristr) compcts tst rsponss in spc. Th fult covr rchs 97.0 % for 50 pttrns n rmins th sm ftr th 50 pttrns. Hnc, w pply 50 tst pttrns (nrt by th countr) to tst th controllr. CLB REN Fiur 5: Schmtic of moifi bit Tbl : Oprtin mos of our bit B0 B Mos Norml function 0 0 Shift ristr 0 Tst pttrn nrtion CLK RST Countr MISR MISR Fiur 6: Schmtic of th controllr E. Tstin of th I/O Convrsion Mouls. W pply n ll0tst pttrn to primry inputs INS(0:5), which r inputs of th sriltoprlll convrtr. Thn w pply iht clocks to mrch th ll0 iii

4 pttrn throuh th iht bit ristrs in th convrtr. Th rsult is ltch into scn ristr in th t pth moul n scnn out for xmintion. W rpt th sm procss for th lltst pttrn. Tstin of th prllltosril moul is similr. W scn in tst pttrn into scn ristr in th moul n pply 7 clocks. Th tst rspons is xmin on primry outputs DOUT(0:5). Th schm chivs 00 % stuckt fult covr. F. Ovrll Tst Schul Th six ict control sinls, TEST, B[0:], n S[0:], r us to control tn iffrnt mos of oprtions. (Rfr to Fi..) Four BIST sssions r lloct. to tst six rithmtic mouls (two rs, two subtrctors, n two multiplirs) in th t pth. Four othr tst sssions inclu controllr tst mo, th trnsposition mmory tst mo, sriltoprlll convrtr tst mo, n prllltosril convrtr tst mo. Th rminin two mos r norml mo n th scn mo. V. EXPERIMENTAL RESULTS A. Appliction of HihLvl BIST Synthsis 5 control stps wr schul for th compltion of th D DCT oprtion, n 6 rithmtic mouls wr ssin for th oprtions. Our hihlvl BIST synthsis tool ADVBIST_h ws ppli in which th numbr of tst sssions ws st to 4 []. Th t pth nrt by ADVBIST_h ws builtin slftstbl with four s n two SRs. B. Tstin of Dt Pth Fi. 7 shows BIST confiurtions for tstin of th t pth. (Only rsourcs tht r rlt to BIST r shown in th fiur.) All th BIST ristrs r connct throuh sinl scn chin to initiliz s n to scn out sinturs of th tst rsponss cptur in SRs. Four BIST tst sssions r us for tstin six rithmtic mouls s scrib rlir, n th mouls n BIST ristrs r shown in Tbl. For ch tst sssion, initil tst pttrns r scnn in, th trt mouls r tst, n tst rsponss r scnn out. All rlt control sinls r nrt from th controllr. Th fult covr of rs n th subtrctors rchs 00 % with 40 n 50 tst pttrns, rspctivly. Th fult covr of th multiplirs rchs 99.0 % for 50 tst pttrns n incrss to % for 00 tst pttrns. W us 50 tst pttrns for th multiplirs; This chivs 99.6 % of fult covr. SCAN_IN R 0 R R R 4 S M M 4 S 5 A 6 A 7 SCAN_OUT SR R SR R Fiur 7: BIST confiurtions for th tstin of DCT t pths Tbl : Tst schul Sssion Moul SR 0 S5 R R4 R S R0 R R M R0 R R M4 R R0 R A6 R R R A7 R R0 R C. Loic & Lyout Dsin Th rsultnt BIST t pth n th control unit wr scrib in VHDL n wr synthsiz to obtin t lvl circuit. Th circuit ws plc n rout usin n HP 0.5 µm CMOS stnr cll librry with tripl mtl lyrs. W lso implmnt circuit without BIST in similr mnnr to msur th ovrh of th BIST sin. Th chrctristics of th two circuits r summriz in Tbl. Fi. 8 shows finl lyout of D DCT circuit with BIST. Tbl : Chrctristics of two chips Dscription w/o BIST w/ BIST Ar of th cor loic 0.84 mm.9 mm Mx. oprbl clock rt.4 MHz 0.8 MHz Ar ovrh 9.95 % Clock sp rtion 5. % Equiv. NAND t counts of th t pth of th control unit 7 55 of th mmory unit 0,00 45 Totl,6 7,0 iv

5 Fiur 8: Lyout of D DCT circuit with BIST VI. CONCLUSION In this ppr, w scrib sin of D DCT circuit. Our hihlvl BIST synthsis tool ws ppli to implmnt th t pth n th controllr. Scn sin ws ppli to othr mouls. Th r ovrh of th DFT incluin BIST is 9.95%, which is tolrbl in inustry. REFERENCES [] H.B. Kim n D.S. H, A HihLvl BIST Synthsis Mtho Bs on Rionwis Huristic for n Intr Linr Prormmin, IEEE Intrntionl Tst Confrnc, pp. 909, Spt [] A. Mistti n A.N. Wilson, Jr., "A 00 MHz D 8x8 DCT/IDCT Procssor For HDTV Applictions, " IEEE Trns. Circuits n Systms for Vio Tchnoloy, vol. 5, pp 585, Apr [] T. Xnthopoulos n A.P. Chnrksn, A Low Powr IDCT Mcrocll for MPEG MP@ML Exploitin Dt Distribution Proprtis for Miniml Activity, IEEE Journl of SoliStt Circuits, vol. 4, no. 5, pp. 6970, My 999. [4] V. Srinivsn n K.J.R. Liu, "VLSI Dsin of Hih Sp TimRcursiv D DCT/IDCT Procssor for Vio Appliction", IEEE Trns. on Circuits n Systms for Vio Tchnoloy, vol. 6, no, pp.8796, Fb. 996 [5] W.H. Chn, C.H. Smith, n S.C. Frlick, A Fst Computtionl Alorithm for th Discrt Cosin Trnsform, IEEE Trns. Commun., vol. COM5, pp , Spt [6] M. Abrmovici, M.A. Brur n A.D. Frimn, Diitl Systms Tstin n Tstbl Dsin, IEEE, Jn v