Overview. Usages of Fault Simulators. Problem and Motivation. Alternatives and Their Limitations. VLSI Design Verification and Testing

Transcription

1 VLSI Dsin Vriiction n Tstin Fult Simultion Mohmm Thrnipoor Elctricl n Computr Eninrin Univrsity o Conncticut Ovrviw Prolm n motivtion Fult simultion lorithms Sril Prlll Ductiv Concurrnt Othr lorithms Rnom Fult Smplin Summry Prolm n Motivtion Fult simultion Prolm: Givn A circuit A squnc o tst vctors A ult mol Dtrmin Fult covr - rction (or prcnt) o mol ults tct y tst vctors St o untct ults Motivtion Dtrmin tst qulity n in turn prouct qulity Fin untct ult trts to improv tsts Uss o Fult Simultors Tst rin s xplin or Tst Gnrtion Fult inosis Dsin or tst (DFT) intiiction o points tht my hlp improv tst qulity known s Tst Point Insrtion Fult-tolrnc intiiction o m ult cn cus Altrntivs n Thir Limittions Fult Simultor in VLSI Dsin Procss Prototypin with ult injction cpilitis Costly Limit ult injction cpility Dsin chns hr to implmnt Lon l tim Hrwr multors Costly Rquir spcil hrwr Mol ult list Fult Low covr? Aqut Stop Vrii sin ntlist Fult simultor Rmov tst ults Tst nrtor Tst Dlt compctor vctors A vctors Vriiction input stimuli Tst vctors 6

2 Exmpl Exmpl Hl-Ar HA c C A B C A B FA FA S S Full-Ar A B C HA D E HA F Crry Sum C A B C A B FA FA S S C 7 8 Fult Simultion Rsults Fult Simultion Scnrio -it FA: 6 loic ts, 9 PIs, POs, 86 sinl stuck-t ults. Vctor Numr Uncollps Fults Dtct Covr % 6% 67% 77% 87% % % % Collps Fults Dtct Covr % 7% 68% 78% 89% % % % Circuit mol: mix-lvl Mostly loic with som switch-lvl or hih-impnc (Z) n iirctionl sinls Hih-lvl mols (mmory, tc.) with pin ults Sinl stts: loic Two (, ) or thr (,, X) stts or purly Booln loic circuits Four stts (,, X, Z) or squntil MOS circuits Timin: Zro-ly or comintionl n synchronous circuits Mostly unit-ly or circuits with ck 9 Fult Simultion Scnrio (cont.) Fult Simultion Alorithms Fults: Mostly sinl stuck-t ults Somtims stuck-opn, trnsition, n pth-ly ults; nlo circuit ult simultors r not yt in common us Equivlnc ult collpsin o sinl stuck-t ults Fult-roppin -- ult onc tct is ropp rom consirtion s mor vctors r simult; ultroppin my supprss or inosis Fult smplin -- rnom smpl o ults is simult whn th circuit is lr Sril Prlll Ductiv Concurrnt Othrs Dirntil Prlll pttrn tc.

3 Sril Alorithm Fult Injction Alorithm: Simult ult-r circuit n sv rsponss. Rpt ollowin stps or ch ult in th ult list: Moiy ntlist y injctin on ult Simult moii ntlist, vctor y vctor, comprin rsponss with sv rsponss I rspons irs, rport ult tction n suspn simultion o rminin vctors Avnts: Esy to implmnt; ns only tru-vlu simultor, lss mmory Most ults, incluin nlo ults, cn simult Moiyin ntlist or vry run cn xpnsiv Altrntiv Chck i nt is ulty or ult-r I ulty chn its vlu to th stuck-vlu Els lv it to th comput vlu Mux s ult insrtion Us itionl vrils n comput th vlu s on th sinl vlu n th vlu in th itionl vril Sril Alorithm (Cont.) Prlll Fult Simultion Disvnt: Much rpt computtion; CPU tim prohiitiv or VLSI circuits Altrntiv: Simult mny ults tothr Tst vctors Fult-r circuit Circuit with ult Circuit with ult Comprtor Comprtor Comprtor tct? tct? n tct? Compil-co mtho; st with two-stts (,) Exploits inhrnt it-prlllism o loic oprtions on computr wors Stor: on wor pr lin or two-stt simultion Multi-pss simultion: Ech pss simults w- nw ults, whr w is th mchin wor lnth Sp up ovr sril mtho ~ w- Not suitl or circuits with timin-criticl n non- Booln loic Circuit with ult n 6 Prlll Fult Sim. Exmpl Ductiv Fult Simultion Bit : ult-r circuit Bit : circuit with c s-- Bit : circuit with s-- c s-- s-- Input = c s-- tct On-pss simultion, on ult-r circuit is simult. Ech lin k contins list L k o ults tctl on k Followin tru-vlu simultion o ch vctor, ult lists o ll t output lins r upt usin stthortic ruls, sinl vlus, n t input ult lists PO ult lists provi tction t Limittions: St-thortic ruls iicult to riv or non-booln ts Gt lys r iicult to us 7 8

4 Ductiv Fult Sim. Exmpl Nottion: L k is ult list or lin k k n is s--n ult on lin k { } {, c } { } c {, } L = L U L c U { } = {,, c, } {,, } L = (L L ) U { } = {, c,, } U Fults tct y th input vctor S Tl.6 in P (txt ook) or ult list proption ruls Concurrnt Fult Simultion Evnt-rivn simultion o ult-r circuit n only thos prts o th ulty circuit tht ir in sinl stts rom th ult-r circuit. A list pr t continin copis o th t rom ll ulty circuits in which this t irs. List lmnt contins ult ID, t input n output vlus n intrnl stts, i ny. All vnts o ult-r n ll ulty circuits r implicitly simult. Fults cn simult in ny molin styl or til support in tru-vlu simultion (ors most lxiility.) Fstr thn othr mthos, ut uss most mmory. 9 Conc. Fult Sim. Exmpl Othr Fult Simultion Alorithms c c c Prlll pttrn sinl ult simultion (PPSFP) Simult mny vctors in prlll Injct only on ult hnc on vnt Simult th circuit rom th ult sit Limittion wll suit or comintionl circuits only Fult Smplin Motivtion or Smplin A rnomly slct sust (smpl) o ults is simult. Msur covr in th smpl is us to stimt ult covr in th ntir circuit. Avnt: Svin in computin rsourcs (CPU tim n mmory.) Disvnt: Limit t on untct ults. Complxity o ult simultion pns on: Numr o ts Numr o ults Numr o vctors Complxity o ult simultion with ult smplin pns on: Numr o ts Numr o vctors

5 Rnom Smplin Mol All ults with ix ut unknown covr N p = totl numr o ults (popultion siz) Rnom pickin C = ult covr (unknown) Dtct ult Untct ult = smpl siz << N p c = smpl covr ( rnom vril) Proility Dnsity o Smpl Covr, c p (x ) (x--c ) σ p (x ) = Pro(x < c < x +x ) = σ ( ( π) / C ( - C) Vrinc,, σ = σ Mn = C σ Smplin rror C -σ C x C +σ. Smpl covr Gussin Proility nsity o smpl ult covr c x 6 Smplin Error Bouns C ( - C ) x - C = [ ] / Solvin th qurtic qution or C, w t th -sim (99.7% coninc) stimt:. C σ = x ± [ +. x ( - x )]/ Whr is smpl siz n x is th msur ult covr in th smpl. Exmpl: A circuit with 9,96 ults hs n ctul ult covr o 87.%. Th msur covr in rnom smpl o, ults is 88.7%. Th ov ormul ivs n stimt o 88.7% ± %. CPU tim or smpl simultion ws out % o tht or ll ults. 7