Multiplierless Modules for Forward and Backward Integer Wavelet Transform

Transcription

1 Multiplirl Mdul fr Frward and Backward Intgr Wavlt Tranfrm Vail Klv Abtract: Thi articl i abut nw architctur f a intgr DWT with rprgrammabl lgic. It i bad n cnd gnratin f wavlt with a rducd f numbr f pratin. A nw baic tructur fr paralll architctur and mdul t frward and backward intgr dicrt wavlt tranfrm i prpd. Ky wrd: lifting chm, rprgrammabl lgic, wavlt, filtr bank, intgr DWT. Intrductin Th wavlt analyi i uful fr th prblm in many ara f applicatin. Thi i a nw ytmatic way fr analyzing functin with a rich bai [1, 6]. In gnral thi man that th ar functin with a gd tim-frquncy ditributin and zr man. It i al pibl t mi a prttyp a i fr th cnd gnratin wavlt. Th dicrt wavlt tranfrm (DWT) i ud in imag and und prcing, ni rductin in ignal, tmgraphic, mdm digital hlgraphic tc. Oftn th prcr fr thi tranfrmatin i bad n rial input and lik data ar input rial frm th firt t th lat ampl. Th prcr ar ffctiv fr n-dimninal ignal, but it i al pibl t u thm fr tw-and thr-dimninal ignal. It i pibl t rprnt th tw dimninal pictur a a qunc f n-dimninal ignal with th pixl arrangd with a prdfind mannr. Th wavlt tranfrm with lifting chm (LS) wrking in plac i dcribd in [5, 8]. Thr i ralizatin with intgr arithmtic fr VLSI ptimiing tructur fr JPEG000 tandard [10]. Th gal f thi papr i t build mdul with nw baic tructur fr intgr dicrt wavlt tranfrm (intgr DWT) by LS fr ral tim prcing and hardwar paramtr tudying. Th algrithm vrviw Th baic principl f LS (fr analyi filtr - H (z) and ynti filtr - G (z) ) ar th plypha rprntatin: 1 H( z) = H ( z ) z H ( z ) (1) 1 G( z) = G ( z ) z G ( z ), whr th plypha cmpnnt H ( z ), G ) and H ( z ), G ( z ) ar Laurn plynmial frm cmmutativ ring. Th diviin with rdundancy hr i pibl but nt an uniqu lutin. Th plynmial rprnt th vn and dd filtr cfficint and frm plypha matrix []: H G P = () H G P (z) dcmpitin i a nw frm f rprntatin with triangl matrix, which dfind th pha f prdictin (P) and updating (U) (Fig.1) Analyi Lt th ignal S b a givn ignal f -lvl. Th rquirmnt fr dcrrlatin dfin th prblm fr ignal rprntatin with minimum cfficint numbr [4]. Spit Aftr uing lazy wavlt th input ampl ar paratd t vn and dd ara f cfficint [8](Fig.1). ( z

2 vn 1 1 Split P U dd 1 d 1 - fig.1 Lifting hm, frward tranfrm Th half f th ampl f riginal ignal frm ach n f th tw ara. ( vn 1, dd 1 ) : = Split( ) (3) Prdictin (P) Lt th ignal b trngly crrlatd. It i pibl t u an vn qunc fr prdictin f dd qunc. Th dtail part d 1 i th diffrnc btwn dd and prdictin valu: d dd P ( vn ) 1 (4) 1 = 1 It i pibl t u tripl ampl [ n], [n 1], [n ] t lin intrplatin with a prdictin pha (P) qual t avrag valu f vn ampl. Th diffrnc btwn dd and prdictd valu frm th wavlt. It i utilizd an pratr fr runding (flr functin x - i th gratt intgr l than r qual t x). It i fund th fllwing wavlt quatin: 1[n] 1[n ] d [ n] = 1[n 1] (5) If th dd valu cincid with prdictd valu, thn wavlt cfficint i zr. Updat (U) Th main gal f pha updating (U) i t find frm calculatd wavlt cfficint th calabl functin fr aving th currnt and avrag f th wavlt fr all lvl f dcmpitin. Th cfficint 0, 0 i avrag valu f ignal fr lat lvl. Th updating rprnt th caling functin fr th nxt lifting tp. vn U ( d ) 1 (6) 1 = 1 Frm th abv cnditin th caling cfficint can b rprntd by th xprin: d 1[ n] d 1[ n 1] [ n] = 1[n] (7) 4 Rcntructin Frm (6) th invrin can b fund f th tp f updating, which rult i an vn valu frm th rtrd qunc f a givn lvl: vn U ( d ) 1 (8) 1 = 1 Frm 1 and d 1 can ut b fund th invrin f prdictin tp (4), which rult i an dd valu frm rtrd qunc f givn lvl: dd d P ( vn ) 1 (9) Th rcntructin ignal 1 = 1 i dcribd a a mrg f vn and dd valu: Mrg ( vn, dd ) (10) = 1 1

3 Th nw baic tructur Th algrithm f ralizatin f LS rquir t tr in th am tim m valu. Th prpd in [5] baic architctur cnit frm tw addr, thr rgitr and n multiplayr. Such cnfiguratin rquir mr rurc and i incnvnint fr updating. In [10] i prp a ructur with n multiplayr, n addr, rgitr and multiplxr. Th diadvantag ar th rquirmnt f a big numbr f rgitr fr making multiplying, with which th tim f arithmtic pratin incra and th pibility th ampl b prcd nly in a rial way. Input R D n D m R R Output 1 Output Fig. Th nw prcing lmnt Th nw tructur (Fig.) i cnitd f tw prgrammabl dlay (D m и D n ), tr rgitr(r) and n addr. Thi tructur i in th bai f buildr intgr DWT. Mdul dcribing 1. Mdul analyi (Fig.3). Th input ignal i 8-bit. Th um f vn valu ( J-1 [n] and J-1 [n]) i trd in rgitr making diviin by tw a a hift n bit right. Th rult frm ( J-1 [n1]) i ubtractd with a pa vr t tw-cmplmnt cd. At th utput i btaind th wavlt valu d J-1 [n-1] and d J-1 [n] which ar ummatd. If th um i ngativ, th pratin diviin by fur i cmbind with n bit crrctin and th rult i addd with vn valu J-1 [n]. That giv th caling valu J-1 [n]. Th blck-dahd lin i ud in th nw baic tructur.. Mdul rcntructin (Fig.4) Thr ar wavlt d J-1 [n] and caling functin J-1 [n] ampl at th input. Th blck ncld with dahd lin i mad with nw ba tructur. If th um f valu d J-1 [n] and d J-1 [n-1] i ngativ, it i ncary t mak crrctin f th rult with n bit fr rrr liminating frm nxt pratin.th rgitr with th um i hiftd tw bit t th right fr diviin f fur. Nxt i th diffrnc btwn th rult f th hifting and J-1 [n], and that giv vn valu [n] trd in an additinal rgitr. Th tw valu ar ummarizd and it i mad a diviin by tw fr thi rult with a hifting f rgitr n bit t th right. Th utput f diviin i ummd with d J-1 [n] and that giv th dd valu [n]. By uing a multiplx it i pibl t hav rcntructin valu ( J 1). Th Hardwar implmntatin f th mdul Th rprgrammabl lgic chang ral tim th cmputr ytm with rcnfiguratin f ytm lvl and with chang f crrpnding data and intructin fr th individual prcing lmnt (PE). Thi lgic wrk with gratly frqunci than that fr th digital ignal prcr (DSP). Th diadvantag f thi lgic i th limit n numbr

4 f lgical pratin. It i pibl t u th advantag f hardwar dcriptin languag and t apply th mthd f dign frm dwn t tp lvl. It i availabl th rrr crrctin and th pibility t mak chang in whl chip tructur. Hr it i ud th high-lvl hardwar dcriptin languag VHDL fr dign dcriptin. Xilinx Fundatin i ud fr plac and ruting. Th imulatin ar mad with MdlSim5.6a f MntrGraphic. Th tt i with cnidratin f th applicatin f th mdul, which will wrk with intgr pitiv ampl. A ignal with 64 ampl (Fig.5) i gnratd wh valu hav with a nrmal ditributin. S J [n] J-1[n], J-1 [n1], J-1 [n] >>1 d J-1 [n] - d J-1 [n-1] >> crrctin J-1[n] Fig. 3 Architctur f frward intgr DWT d J-1 [n] J-1 [n] d J-1[n], d J-1[n-1]... d J-1[n-6] J-1[n], J-1 [n-1] J-1 [n-3] crrctin >> - vn rgitr >>1 dd Fig. 4 Architctur f backward intgr DWT MUX J 1 [n] Aftr th ptimizatin th dignd mdul hav th fllwing charactritic (Tabl 1). Th dignd with th prpd nw baic tructur mdul giv th pibility f dcraing th hardwar rquirmnt fr gnratin f th utput f frward ( J-1 [n], d J-1 [n]) and backward ( 1 ) intgr DWT (Tабл.).

5 Mdul Analyi Targt Dvic: Virtx Excv00-pq40-8 #Wrk frquncy (MHz) :100 # Rgitr : 30 8-bit rgitr : 30 # Addr/Subtractr : 5 8-bit ubtractr : 1 8-bit addr : 4 Tаbl 1 Mdul Rcntructin Targt Dvic: Spartan xc150-fg56-6 #Wrk frquncy (MHz) :100 # Rgitr : 1 9-bit rgitr : 1 # Addr/Subtractr : 6 9-bit addr : 6 Fig. 5 Fig. 6 CONCLUSIONS AND FUTURE WORK It i pibl t mak th fllwing cncluin frm th dignd mdul and frm th achivd rult: - Paralll prcing with th prpd blck tructur implifid th hardwar implmntatin fr th arithmtic pratin ralizatin (Tабл.);

6 Tabl Tabl 3 Filtr (5/3) Thi Kihr Thi DSP [9] Dwt[10] wrk A. [5] wrk Fl. pint Fpga Addr 4 8 Shiftr 4 1µ 400µ 0µ - Th frward and backward intgr DWT by Ll chm hav th am calculatin cmplxity; - Th pibility fr paralll and rial pratin with data in a clck prid by uing th tat chart; - It i pibl t b ud prcing f data that hav nt nly th pwr tw; - Th tandard mthd fr (5, 3) filtr bank rquir 8 pratin whil th LS nly 5. Thi mak uful and ffctiv th intgr valu filtr fr calculating pd incra; - A givn intgr valu f ignal aftr tranfrmatin i ll tranfrmatin (Fig.5); - Th architctur fr fixd pint arithmtic (th prpd mdul and th in [10]) with cmparin f th with flating pint arithmtic giv m highr pd fr prcing f lin with 56 ampl with 8 bit accuracy (Tabl 3); In th futur wrk it i xpctd t b applid th mdul fr IDWT with vral lvl and analyzing with LS algrithm fr und and imag cmprin. Thi i a pibility fr mdul ASIC implmntatin. Rfrnc: [1] Daubchi I., Tn Lctur n wavlt, Nw Yrk, Siam, 199. [] Daubchi I., Swldn W., Factring wavlt tranfrm int lifting tp, Jurnal Furir Analyi Applicatin, vl. 4, pp , [3] Gnavi S., Pnna B., GrangttM, and Magli E., Olm G., DSP prfrmanc cmparin btwn lifting and filtr bank fr imag cding, Prc. f ICASSP, pp. III III-3147, 00. [4] Jnn A., La Cur-Harb A., Rippl in mathmatic - th dicrt wavlt tranfrm, Springr Vrlag, 001. [5] Kihr A., Chaitali C., A VLSI Architctur fr Lifting-Bad Frward and Invr Wavlt Tranfrm, IEEE Tranactin n Signal Prcing, vl.50, 00. [6] Rnikff H. L., Wavlt analyi Scalabl tructur f infrmatin, Springr, [7] Rittr J., Mlitr P., A piplind architctur fr partitind DWT bad ly imag cmprin uing FPGA, Prc. 9 th Intrnatinal Sympium n FPGA, 001. [8] Swdn W., Th lifting chm: A cutm dign cntructin f birtgnal wavlt, Jurnal Applicatin Cmp. Harmnic Analyi, vl. 3, n., pp , [9] Swdn W. Schrdr P, Building yur wn wavlt at hm, tch. rp., Indutrial mathmatic Initiav, Univrity f Suth Carlina, n 5, [10] Trna M. A., Opz J. L, and Zapataa E. L, Cnfigurabl Architctur fr th Wavlt Packt Tranfrm, Jurnal f VLSI Signal Prcing 3, 55 73, 00. ABOUT THE AUTHOR Vail Klv, Intitut f Infrmatin and Cmmunicatin Tchnlgi, Bulgarian Acadmy f Scinc, Е-mail: klv_acad@abv.bg.