G406 Implementation of Haar Wavelet Transform on Xilinx Spartan-3E FPGA

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1 Prcding Cnfrnc n Applid Elctrmagntic Tchnlgy (AEMT) mbk, - 5 April G46 Implmntatin f Haar Wavlt Transfrm n ilinx Spartan-3E FPGA Risanuri Hidayat,Sasmit Aji, itasari 3,,3 Dpartmnt Elctrical Enginring, Enginring Faculty Univrsity f GadjahMada Univrsity f GadjahMada (UGM) Jln. Grafika Ygyakarta 558 INDONESIA Abstract This paprdiscusssth fficint and accurat implmntatin fth discrthaarwavlt Transfrm (HWT) by slctin f th bst fit filtrbank structur and data frmat. Implmntatin fth Haarwavlt transfrm is prfrmd nilinxspartan-3e Fild PrgrammablGatArray(FPGA) and it is intnddfrprcssing f vic signals. By using thlatticfiltr bank structurandfixd-pint data frmat, th implmntatin fhaar Wavlt Transfrm withsix dcmpsitin lvls rquir nly 5% f FPGA s slics and giv accuracy 98.9%. Kywrds Discrt Wavlt Transfrm (DWT), Haar Wavlt Transfrm (HWT), Fild Prgrammabl Gat Array (FPGA), Filtr Bank, Data Frmat, Dcmpsitin. I. INTRODUCTION Currntlymanypaprs discuss abut discrt wavlt transfrm (DWT)ithr its usfulnssr its implmntatin prcss bth insftwarandhardwar. On f thhardwarcan b usdfr thimplmntatin f thdwt is Fild Prgrammabl Gat Array (FPGA). Thrar manypaprsthat discussthwavlt transfrmnfpgaspcially fr signal prcssing and als th ptimizatin t imprv th spdandth fficincy f FPGA s rsurcs[,, 3, 4, 5, 6]. Th paprthat fcuss n FPGAcan t b sparatdfrm thptimizatint imprvth fficincy f FPGA s rsurcs bcausth rsurcswhich availablin thfpga is limitd. S it must b find th tchniqusandmthds in rdr t gt ptimal, fficint, and accurat f FPGAimplmntatin. Almst all fpaprs abut FPGAalwayshavdiscussinabutcmputing spd, th rsurcs fficincy andals th rsult accuracy. Thrar manypaprdiscussing th implmntatin and ptimizatin fdwtnfpga thatusdfrimagandvidprcssing [, 4, 6, 7, 8, 9, ].Inimagandvidprcssing, DWTis usdfrcmprssinandd-nising. Bsids usdfrimag prcssing, implmntatin f DWTnFPGAis alsusdfrvicsignalprcssing [].Althughthr armany paprs thatimplmntdwt n FPGA, thr islimitd papr that studis abut th prfrmanc fthfiltrbankstructurand data frmatin th DWT. Th study n th filtr bank structur and th data frmat is imprtant t prduc an fficint and accurat implmntatin f DWT. This papr discusss th implmntatin f filtr bank structur and data frmat in DWT in rdr t gt an fficint and accuratimplmntatin f DWT. Thr ar tw typs f filtr bank structur that studid i..plyphas and lattic and als thr typs f data frmats including n flating pint and tw fixd pint data frmat. Bsids fcus n th filtr bank structur and data frmat, this papr als discuss abut th ffct f th dcmpsitin lvl n th FPGA s rsurcs. Th DWT is implmntd n FPGA ilinx Spartan 3-E (C3S5E-4FG3) II. HAAR WAVEET TRANSFORM (HWT) In th analysis prcss fdwt, th input signal x[k] ntrd int th lw pass filtr () and highpass filtr (H). Ths filtrs sparat th signal int lw and high frquncy with th sam lngth and numbr f data. T liminat data rdundancy, th filtring stag is fllwd by dwn sampling ( ). In th synthsis prcss, th signal will b up sampl ( ) and thn passd t lw pass filtr ( ') and highpass (H'). Th prcss f DWT is shw in Fig.. w pass and high pass filtr f HWT is shwn in () []. H H x x Analysis Synthsis Fig.. Analysis and Rcnstructin f DWT [3] 67

2 Prcding Cnfrnc n Applid Elctrmagntic Tchnlgy (AEMT) mbk, - 5 April ' H H ' A. Filtr Bank Structur Tprfrmth HWT, lw passandhigh passfiltr must barrangd t frmfiltr bank. Filtr bank structur affcts thcmputatins thatth slctin f th bst fit filtr bank structur can givptimal cmputatin. Thr arsvraltyps ffiltrbanks structur such as dirct frm, plyphas, lattic, andlifting. Inthis papr will b fcusd n plyphas and lattic filtr bank structur. Plyphasand thlattic filtr bankis shwnin Fig.and Fig.3. Ths filtr bankscan b xprssdby() and(3). [n] Y Y [n] Y Y H Z - k H H H Fig..PlyphasFiltrbank Structur Z - z -k k z Fig. 3.attic Filtrbank Structur k z with k & () β -β (3) () Y [n] Y [n] Y [n] Y [n] B. Data Frmat Th data frmat influncs th rsult accuracy f HWT. Th data frmat shall b cmprmisd t cmputatinal rsurcs. Thr ar thr typs fdata frmatthat studid including f tw typs f fixd pint data frmats and th flating pint data frmat. Th data frmat is shwn in Fig. 4, Fig. 5 and Fig. 6. In th fixd-pint data frmats, thr ar 8- bit data, cnsist f sign bit, intgr and fractin. On fixdpint data frmat cnsists f a 3-bit intgr and 4-bit fractin and calld Fixd Pint-I, whil anthrfixd pint data frmat cnsists f a 4-bit intgr and 3-bit fractin and calld as Fixd Pint-II. Th flating pint data will cnsist f a -bit sign (S), 8-bit xpnnt (Exp) and 3-bit mantissa (M). And can b xprssd with flating pint can b xprssd by (4) [4]. S ( Exp 7) N ( ) M (4) b7 b6 b5 b4 b3 b b b b9 b8 b7 b6 b5 b4 b3 b b b Sign bit intgr fractin Fig. 4.Data Frmat Fixd Pint b7 b6 b5 b4 b3 b b b b9 b8 b7 b6 b5 b4 b3 b b b Sign bit intgr fractin Fig. 5.Data Frmat Fixd Pint-II S Exp Fractin 3 3 (8-bits) (3-bits) Bias = 7 bit indx Fig. 6.Data Frmat Singl Prcisin Flating Pint[4] III. METHODOOGY Th implmntatin f HWT includs implmntatin n sftwar and FPGA. Implmntatin f HWT n sftwar is rquird t gt data rfrnc as cmparisn fr implmntatin f HWT n FPGA. T prfrm HWT n FPGA, th input datais ntrd t FPGA frm cmputr by using srial cmmunicatin and th rsult f HWT will b snt back frm FPGA t th cmputr in th sam srial cmmunicatin lins. As input datais usd vic signals that riginating frm th prnunciatin f th vwl "I". This vics signal is savd in wav frmat and cut int 64 data pints. Each data pint is rprsntd by 8-bit fixd pint r 3-bit singl prcisin flating pint. T givan ptimal and fficint f HWT, th bst fit f filtr bank structur, data frmat and th dcmpsitin lvl is slctd. Sm HWT prgrams with diffrnt filtr bank structurs, data frmats, and dcmpsitin lvl ar writtn and implmntd n FPGA by using Vrilg HD. Th usag f FPGA s rsurcs including slic flip-flp, k Up Tabl (UT), slic, Input Output Blck (IOB), Randm Accss Mmry (RAM) and Multiplir arstudid fr diffrnt implmntatin.th cmputatin prcss f HWT n th FPGA can b illustratd by Fig. 7. Th implmntatin f HWT with th minimal us f FPGA srsurcs will giv bttr fficincy. Bsid f fficincy aspct, thispapr als xamins th accuracy f 68

3 Prcding Cnfrnc n Applid Elctrmagntic Tchnlgy (AEMT) mbk, - 5 April HWT implmntatin. Th accuracy is btaind by cmparing th HWT rsults with data rfrnc. Th input data cm frm vic signal is ntrd t FPGA and th rsult f HWT n FPGAs is snt back t cmputr t b cmpard tdata rfrnc in rdr t gt accuracy. N. f Slic (max. 4656) 87 (6%) 86 (8%) N. f RAM (max. ) 3 (5%) 3 (5%) N. f Multiplir 8x8 (max. ) 4 (%) 4 (%) a. Rsurc rquird fr dcmpsitin prgram b. Rsurc rquird fr ttal prgram including Input data prcssing, dcmpsitin, and utput data prcssing st EVE DECOMPOSITION MEMORY_ x[] x[] x[] x[3] x[4] x[n/-] x[n/] x[n-5] x[n-4] x[n-3] x[n-] x[n-] MEMORY_ sum sum sum sum sum sum diff diff diff diff diff diff MEMORY_ x[] x[] x[] x[3] x[4] x[n/-] x[n/] x[n-5] x[n-4] x[n-3] x[n-] x[n-] [] [] [] [3] [4] [n/-] [n/] [n-5] [n-4] [n-3] [n-] [n-] st Dcmpsitin nd Dcmpsitin 3 rd Dcmpsitin mth Dcmpsitin Fig. 7. Dcmpsitin Prcss n FPGA IV. RESUT AND DISCUSSION An fficint f HWT is btaind by th slcting filtr bank structur, data frmat, and th dcmpsitin lvl. A. Slctin f Filtr Bank Structur Thr ar tw filtr bank structurs that studid, thy ar plyphas and lattic. FPGA s rsurcs rquird t implmnt th HWT with plyphas filtr bank structurs is shwn in Tabl I and fr lattic filtr bank structur is shwn in Tabl II. Frm Tabl I and Tabl II, it can b btaind that th lattic structur rquirs lss f FPGA rsurcs.s lattic structur is mr fficint than plyphas structur. If bth implmntatin f HWT ar tstd, it giv 99.67% accuracy (rrr =.33%) fr th plyphasstructur and 99.65% accuracy (rrr =.35%) fr th lattic structur.bth implmntatins f HWTwith plyphas and lattic structur giv gd accuracy. TABE I. RESOURCES FOR HWT WITH POYPHASE FITERBANK STRUCTURE N. f Slic Flip-Flp (max. 93) 339 (3%) 653 (5%) N. f UT (max. 93) 47 (5%) 553 (6%) TABE II. RESOURCES FOR HWT WITH ATTICE FITERBANK STRUCTURE N. f Slic Flip-Flp (max. 93) 6 (%) 478 (5%) N. f UT (max. 93) 346 (3%) 47 (5%) N. f Slic (max. 4656) 9 (4%) 763 (6%) B. Slctin f Data Frmat Thrar thrdata frmatsthat studid including fixdpint-i, fixdpint-ii, and singlprcisinflating pint. Th implmntatin f HWT with thr typs f data frmat us lattic filtr bank structur. atticfiltr bank structur givsfficintimplmntatin f HWT basd n part IV.A.Th FPGA s rsurcsrquird fr implmntatin f HWT with thr typ data frmat ar shwn in Tabl III, Tabl IV, and Tabl V. TABE III. RESOURCES FOR HWT WITH FIED POINT- I DATA FORMAT N. f Slic Flip-Flp (max. 93) 6 (%) 478 (5%) N. f UT (max. 93) 346 (3%) 47 (5%) N. f Slic (max. 4656) 9 (4%) 763 (6%) TABE IV. RESOURCES FOR HWT WITH FIED POINT-II DATA FORMAT N. f Slic Flip-Flp (max. 93) 6 (%) 478 (5%) N. f UT (max. 93) 346 (3%) 47 (5%) N. f Slic (max. 4656) 9 (4%) 763 (6%) TABE V. RESOURCES FOR HWT WITH FOATING POINT DATA FORMAT N. f Slic Flip-Flp (max. 93) 789 (9%) 87 (3%) N. f UT (max. 93) 93 (%) 34 (36%) N. f Slic (max. 4656) 4 (3%) (47%) N. f IOB (max. 3) 7 (3%) 3 (5%) N. f Multiplir 8x8 (max. ) 4 (%) 4 (%) Basd n Tabl III, Tabl IV, and Tabl V, bth fixdpint data frmats rquir th sam numbr f rsurcs vn thugh th data frmats havdiffrnt numbr f intgr and fractin. S th fixd pint data frmat will rquir th sam numbr f rsurcsas lng as it has th sam data siz. Th 69

4 N. f FPGA Rsurcs Prcding Cnfrnc n Applid Elctrmagntic Tchnlgy (AEMT) mbk, - 5 April flating pint data frmat rquirs mr rsurcs cmpard t fixd pint data frmats. As th xampl, th ttal FPGA slic rquird fr flating pint data frmat is 6% highr than fixd pint data frmats. Althugh thnumbr f FPGA srsurcs in flating pint data frmat is highr, th flating pint data frmat ffrs xcllnt accuracy and vry wid data rang. Ths advantags ar nt wnd by th fixd pint data frmat. In th fixd pint data frmat,data rang and accuracy smtims giv ppsit dirctin r ffct. T gt bttr accuracy, th numbr f fractin shall b incrasd, but this will mak narrwr data rang. Thrfr bfr usingfixd pint data frmat, th inputdata rang and th xpctd accuracy shall b cnsidrd and cmprmisd. Aftr that th apprpriat fixd pint data frmat can b dtrmind. Cnsidring th larg numbr f FPGA s rsurcs which is rquird fr implmntatin f HWT with flating pint data frmat, thn th usag f fixd pint data frmat is gd chic. Bsid fficint in th usag f FPGA s rsurcs, th implmntatin f HWT with fixd pint data frmat can als giv gd accuracy. As th vidnc, whn using fixd pint data frmat with lattic structur fr implmntatin f HWT, its accuracy is 99.65%(as pr part IV.A). C. Effct f Dcmpsitin vl n FPGA Rsurcs It has bn implmntd th HWT with svral dcmpsitin lvl frm st up t 6 th dcmpsitin lvl. Th implmntatin f HWT uss lattic structur and fixd pint data frmat. Th numbrs f FPGA s rsurcs rquird fr implmntatin ar shwn in Tabl VI t Tabl. Th FPGA srsurc fr implmntatin f HWT with st dcmpsitin has bn shwn in Tabl IV. TABE VI. RESOURCES FOR HWT WITH ND DECOMPOSITION EVE N. f Slic Flip-Flp (max. 93) 68 (%) 485 (5%) N. f UT (max. 93) 385 (4%) 46 (5%) N. f Slic (max. 4656) 8 (4%) 789 (6%) TABE VII. RESOURCES FOR HWT WITH 3 RD DECOMPOSITION EVE N. f Slic Flip-Flp (max. 93) 76 (%) 49 (5%) N. f UT (max. 93) 434 (4%) 56 (6%) N. f Slic (max. 4656) 36 (5%) 8 (7%) TABE VIII. RESOURCES FOR HWT WITH 4 TH DECOMPOSITION EVE N. f Slic Flip-Flp (max. 93) 86 (%) 55 (5%) N. f UT (max. 93) 48 (4%) 5 (6%) N. f Slic (max. 4656) 3 (4%) 87 (7%) TABE I. RESOURCES FOR HWT WITH 5 TH DECOMPOSITION EVE N. f Slic Flip-Flp (max. 93) 89 (%) 56 (5%) N. f UT (max. 93) 467 (5%) 59 (6%) N. f Slic (max. 4656) 5 (5%) 8 (7%) TABE. RESOURCES FOR HWT WITH 6 TH DECOMPOSITION EVE N. f Slic Flip-Flp (max. 93) 93 (%) 5 (5%) N. f UT (max. 93) 58 (5%) 6 (7%) N. f Slic (max. 4656) 76 (5%) 858 (8%) If Tabl IV and Tabl VI t Tabl ar dscribd in graphics, it will b btaind Fig. 8. Frm Fig. 8, it clar thatth incrasingf dcmpsitinlvl ds nt significantly affctt th incrasing f FPGA rsurcs.at6 th dcmpsitin lvl, th implmntatin f HWTnly rquir FPGA rsurcs that% highr cmpard t th implmntatin f HWT with st dcmpsitin lvl. Whn tstd, th HWT with 6 th dcmpsitin lvl giv 98.3% accuracy frfixd pint- Idata frmatand98.9% frfixd pint-iidata frmat Dcmpsitin vl vs N. f FPGA Rsurcs Dcmpsitin vl Fig. 8. Dcmpsitin lvl and Rsurcs f FPGA slic slic flip-flp UT IOB Mmry Multiplir Basd n part IV.A, IV.B and IV.C, th implmntatin f HWT rquirs small numbr f FPGA s rsurcs if it uss an apprpriat filtr bank structur and data frmat. By using th lattic structur and fixd pint data frmat, th implmntatin nly rquir 4% f slic fr HWT with st dcmpsitin lvl and 5% f slic fr HWT with 6 th dcmpsitin lvl. attic structur canrduc th cmputatin, rduc mmry usag and rduc multiplir significantly. It nly nds tw mmris and singl multiplir t implmnt HWT with th lattic structur. 7

5 Prcding Cnfrnc n Applid Elctrmagntic Tchnlgy (AEMT) mbk, - 5 April Th data frmat affcts th usag f FPGA s rsurcs. Singl prcisin flating pint data frmat ffrs xcllnt accuracy and wid data rang, but rquir mr FPGA s rsurcs. As an xampl th numbr f slic rquird fr flating pint data frmat is 6% highr than fixd pint data frmat. Fixd pint data frmat rquirs lss f FPGA, s it mr fficint. Bsid that, it can giv gd accuracy as lng as th numbr f intgr and fractinis matchd t th rang f signal t b prcssd. Althugh fixd pint data frmat has diffrnt numbr f intgr and fractin, th HWT will rquirsam numbr f FPGA s rsurcs as lng asthat fixd pint data frmat has sam data width. An incrasing f dcmpsitin lvl ds nt incras th numbr f FPGA rsurcs significantly. Bcaus whn dcmpsitin lvl incrass, th numbr f data bing prcssd dcrass int half f th riginal numbr. Th implmntatin f HWT with 6 th dcmpsitin lvl nly rquirs FPGA s rsurcs % highr cmpard t HWT with st dcmpsitin lvl. But at 6 th dcmpsitin lvl, th accuracyis dcrasing t 98.9% frm 99.67% at st dcmpsitin lvl. Th dcrasing f accuracy is affctd by runding rrr prpagatinthat ccurs frm th st dcmpsitin lvl up t 6 th dcmpsitin lvl. [7] A. Bnkrid, K. Bnkrid and D. Crks, "Dsign and Implmntatin f a Gnric -D Orthgnal Discrt Wavlt Transfrm n FPGA," in th Annual IEEE Sympsium f Fild Prgrammabl Custm Cmputing Machin (FCCM'3), 3. [8] K. H. Talukdr and K. Harada, "Haar Wavlt Basd Apprach fr Imag Cmprssin and Quality Assssmnt f Cmprssd Imag," IAENG Intrnatinal Jurnal f Applid Mathmatics, 6. [9] R. M. Jiang and D. Crks, "FPGA Implmntatin f 3D Discrt Wavlt Transfrm fr Ral-Tim Mdical Imaging," IEEE, 7. [] A. Ahmad, P. Nichll and B. Krill, "Dynamic Parial Rcnfiguratin f -D Haar Wavlt Transfrm (HWT) fr Fac Rcgnitin Systm". [] J. Chil and T. indblad, "Hardwar Implmntatin f D Wavlt Transfrm n an FPGA fr Infrasund Signal Classificatin," in IEEE Transactin n Nuclar Scinc Vl. 55, 8. [] M. Vttrli and J. Kvacvic, Wavlt and Suband Cding, Nw Jrsy: Prntic Hall PTR, 7. [3] M. Stinbuch and M. Van d Mlngraft, Wavlt Thry and Applicatin a itratur Study, Eindhvn: Eindhvn Univrsity Tchnlgy Dpartmnt f Mchanical Enginring Cntrl Systm Grup, 5. [4] R. Wd, J. McAllistr, G. ightbdy and Y. Yi, FPGA-basd Implmntatin f Signal Prcssing Systms, Wiltshir, Unitd Kingdm: Jhn Wily & Sns, 8. V. CONCUSION This papr succssfully implmnts th discrt HWT n ilinx Spartan-3E FPGA (C3S5E FG3) with gd fficincy and accuracy. An fficint and accurat HWT implmntatin is btaind by slctingth bst fit filtr bank structur and data frmat. attic structur and fixd pint data frmat giv fficint and accurat implmntatin f HWT. Bsid that th dcmpsitin lvl will nt incras th usag f FPGA s rsurcs significantly. Th implmntatin f HWT with 6 th dcmpsitin lvl nly rquirs5% f slics and givs 98.9% f accuracy. Th fficint and accurat implmntatin f HWT will prvid flxibility fr furthr dvlpmnt f HWT spcially fr mr cmplx signal prcssing. REFERENCES [] M. Anglpulu, K. Massls, P. Chung and Y. Andrpuls, "A Cmparisn f -D Discrt Wavlt Transfrm Cmputatin Schduls n FPGA," 6. [] Q. Huang, Y. Wang and S. Chang, "High Prfrmanc FPGA Implmntatin f Discrt Wavlt Transfrm fr Imag Prcssing,". [3] M. Guarisc,. Zhang, H. Rabah and W. Srg, "An Efficint Implmntatin f Scalabl Architctur fr Discrt Wavlt Transfrm On FPGA," in IEEE, 7. [4] M. Katna, A. Pizurica, N. Tslic, V. Kvacvic and W. Philips, "FPGA Dsign and Implmntatin f a Wavlt Dmain Vid Dnising Systm". [5] P. Gupta and S. K. nka, "A Nvl VSI f Architctur f High Spd D Discrt Wavlt Transfrm," Intrnatinal Jurnal f Elctrical and Elctrnic Enginring (IJEEE), vl. 3, n. I, pp , 3. [6] H. Sahlizadh and A. Kshavarz, "A FPGA Implmntatin f Nural / Wavlt Fac Dtctin Systm," Australian Jurnal f Basic and Applid Scinc, pp ,. 7