Multi-level Discrete Wavelet Transform Architecture Design

Transcription

1 Prcdings f th Wrld Cngrss n Enginring 009 Vl I WCE 009, July - 3, 009, ndn, U.K. Multi-lvl Discrt Wavlt Transfrm Architctur Dsign Dhaha Dia, Mdin Zghid, Taufi Saidani, Mhamd Atri, Blgacm Buallgu, Mhsn Machhut and Rachd Turi Abstract A flxibl architctur is prpsd in this papr fr implmntatin Discrt Wavlt Transfrm (DWT) f 5/3 filtr. Th prpsd architctur includs transfrms mduls, a and bus intrfacs. This architctur wrs in nn sparabl fashin using a srial-paralll filtr with distributd cntrl t cmput all th DWT (D-DWT and D-DWT) rslutin lvls. Th s-calld lifting schm rprsnts th fastst implmntatin f th DWT. A VD mdl was dscribd and synthsizd using implmntatin f ur architctur. Synthsis rsults shw that Xilinx XCV600E FPGA implmntatin can b achivd with a frquncy f abut 08 Mhz, allwing prcssing rat btwn 85 and 87 frams pr scnd fr a rang f standard pictur dimnsins. Spd/Ara rsulting frm this prcssr is analyzd and is shwn t dmnstrat that ur dsign achivs favurabl prfrmancs with thr FPGA basd implmntatins. Indx Trms Architctur, DWT, Flxibl, ifting Schm, 5/3 filtr. I. ITRODUCTIO Fr multimdia prcssing, Discrt Wavlt Transfrm (DWT) basd imag cding has bttr prfrmanc than traditinal DCT basd imag cding, spcially fr lw bit-rat applicatins []. Thrfr many famus cdrs hav bn prpsd t ffctivly cmprss imags r frams prcssd via DWT. Bsids, th DWT is mplyd in JPEG000, th nw standard fr imag cmprssin, whr th 9/7 and th 5/3 wavlt filtrs ar mplyd as th dfault filtrs fr lssy and lsslss cmprssin rspctivly. DWT has traditinally bn implmntd by cnvlutin r th finit impuls rspns (FIR) filtr ban structurs. Such implmntatins rquir bth larg numbr f arithmtic cmputatins and a larg strag, faturs that ar nt dsirabl fr ithr high spd r lw pwr imag/vid prcssing applicatins. Thrfr a nw apprach is calld th lifting schm basd wavlt transfrm r simply lifting has bn prpsd by Swldn basd n a spatial cnstructin f th wavlt and a vry vrsatil schm fr its factrisatin has bn suggstd in []. Th architctur lifting-basd D-DWT dvlpd in [3] has rgular data flw and lw cntrl cmplxity, and achivs 00% hardwar utilizatin. Th thr architctur Manuscript rcivd March, 009; rvisd 8 April 009. This wr was supprtd by Elctrnic and Micrlctrnic abratry, Mnastir. Dhaha Dia is with Elctrnic and Micrlctrnic abratry, Faculty Scincs f Mnastir, 5000 Tunisia (phn: ; fax: ; -mail: dhaha.dia@issats.rnu.tn). was basd prprity f prfct rcnstructin f filtr ban dvlpd in []. Many architcturs f DWT wr prpsd in litratur cmbind lssy and lsslss transfrm li [5], th aim f this brif is t mbd th 5/3 wavlt cmputatin int th 9/7, in rdr t xplit as much as pssibl th 5/3 rsults t achiv th 9/7 ns, with a rducd numbr f addrs cmpard t thr slutins. In [6] th prpsd architctur can b rcnfigurd fr 5/3 and 9/7 wavlt transfrms. This rducs significantly th rquird numbrs f th multiplirs, addrs and rgistrs, as wll as th amunt f accssing xtrnal mmry, and lads t dcras fficintly th hardwar cst and pwr cnsumptin f dsign. In [7] th architctur fr D-DWT principl can b xtndd t architcturs fr sparabl D-DWT li th n dvlpd in [8], [9]. Th thr basd pyramid algrithm was dvlpd in [0]. In this papr ur architctur is srial-paralll basd bi-rthgnal filtr it implmnt D-DWT and D-DWT, thrfr w gt a dsign f DWT rcnfigurabl with th multi-lvls rslutin fr th up nds. W dscrib ur architctur f DWT using lifting schm structur with distributd cntrl t cmput all th rslutin lvls f DWT. This architctur is rcnfigurabl and scalabl in its ttality, sinc w chang th lvls and typs f transfrms (D-DWT r D-DWT) withut changing th dsign f th cntrl units. Th rmaining papr is rganizd in th fllwing mannr: th nxt sctin prvids a brif vrviw f th lifting schm DWT algrithm. In th sctin 3, th prpsd architctur systm and its intrnal cmpnnts ar dscribd in dtails. Th synthtic rsults f th FPGA implmntatin ar givn in th sctin. Cmparisns rsults with thr architcturs rlatd wrs ar als prsntd in sctin 5. Finality, cnclusins ar discussd in sctin 6. II. DWT BY IFTIG SCEME Th lifting schm is an algrithm usd fr implmntatin hardwar and sftwar f DWT; it is cnstitutd f stps f Imag igh Pass Split Prdictin Up dating w Pass Fig. ifting schm frward transfrm ISB: WCE 009

2 Prcdings f th Wrld Cngrss n Enginring 009 Vl I WCE 009, July - 3, 009, ndn, U.K. prdictins and updating dscribd by th Fig.. Th advantag f lifting schm is th frward and invrs transfrm was btaind frm th sam architctur. Th invrs gs frm right t th lft, by invrsing th cfficints f nrmalizd and changs th sign psitiv t ngativ. Whr is th cnstant f nrmalisatin and th stps f th prdictins and th updating at in plyphas matrix. Th plyphas rprsntatin f discrt filtr h (n) is dfind as: h( = h ( z ) z h ( z ) () whr h and h ar rspctivly btaind frm th vn and dd zta transfrm rspctivly. If w rprsnt h and g th lw pass and high pass cfficints f th synthsis filtr rspctivly, th plyphas matrix writtn as: h p( = h g g Th filtrs h, h, g and g ar aurnt plynmials, as th st f all plynmials xhibits a cmmutativ ring structur, within which plynmial divisin with rmaindr is pssibl, lng divisin btwn tw aurnt plynmials is nt a uniqu pratin. In Euclidan algrithm can b usd, th plyphas p is finally btaind as: () dirct lifting schm f bi-rthgnal 5/3 filtr, whr th cnstant is qual unit. X X ( n ) d ( n ) [ X (n) X (n )] [ d (n ) d(n ) ] X ( n) a ( n) Fig. ifting schm f 5/3 filtr Th lifting basd implmntatin f tw lvls D-DWT may b cmputd using filtr bans as shwn in Fig.3. Th input sampls X(n) ar passd thrugh tw stags f analysis filtrs. Thy ar first prcssd by lw-pass () and high-pass () hrizntal filtrs and ar sub sampld by tw. Subsquntly, th utputs (, ) ar prcssd by lw-pass and high-pass vrtical filtr. t that:, ar th utputs f D-DWT;,, and n-lvl f D-DWT. X(n) rizntal filtr Vrtical filtr m p( = i 0 s ti i = (3) rizntal filtr Vrtical filtr Fig.3 Subband fr tw-lvl D-DWT Whr s i and t i primary lifting and dual lifting stps filtrs rspctivly, is a cnstant f nrmalisatin at lw and high cfficints filtrs. Th 5/3 wavlt filtr transfrm is mr suitabl lsslss data cmprssin adptd in JPEG000 and 9/7 filtr is usd in JPEG000 fr lssy cmprssin data. Th 5/3 filtr has n prdictin and n up-dating cmpard t tw prdictins and tw up-dating fr 9/7 filtr. Th fllwing stps ar ncssary t gt thir wavlt cfficints as th fllwing taps fr 5/3 filtr: Split th input signal (imag) int cfficints at dd and vn psitins. Prfrm a prdict stp, that is th pratin givn blw in (). Prfrm up-dating stp which is th pratin givn blw in (5). x(n) x(n ) d (n ) = x(n ) () d ( n ) d ( n ) a ( n ) = x ( n ) (5) Ths quatins ar illustrat and prsntd in th Fig. fr III. OUR PROCESSOR DESIG AD IMPEMETATIO This sctin prsnts th architctur dsign f ur prgrammabl DWT prcssr. This prcssr can prfrm th D-DWT and D-DWT with multi-lvls upn in th usr nds. A. Cmpnnts f ur prcssr dsign A blc basd tp-lvl implmntatin f ur prpsd prcssr is shwn in Fig.. Th prpsd systm supprts svn blcs. Th architctur shwn n lvl but it is rcnfigurabl fr th multi-lvls in ur nd. In this Fig., basic units f th architctur systm ar shwn. Th fllwing units ar: A Bus Intrfac Unit has bn intgratd in rdr t achiv cmmunicatin fficintly with th xtrnal nvirnmnt. Th Cntrl Unit is dsignd t cntrl th data flw in th dsign, as wll as th data transfr btwn th intrfac Unit, th Cmputatin Unit and th Unit. A FSM is usd fr this purps. During ISB: WCE 009

3 Prcdings f th Wrld Cngrss n Enginring 009 Vl I WCE 009, July - 3, 009, ndn, U.K. initializatin phas, th usr with th apprpriat writ cmmands slcts th DWT typ (D-DWT, D-DWT and with multi-lvls s). Th Cntrl Unit crdinats all systm pratins and prcsss. Aftr th initializatin phas, th cntrl unit is ttally rspnsibl fr th systm pratin. Th cntrl unit manags th pratin f D-DWT srial-paralll vn-dd filtr (Fig.). It cntrls th data input, th synchrnizatin f th pratins, and th data utput. Th blc prcssing lmnts: ach f thm cntains a multiplir and an addr. Evry fiv clc cycl n prcssing lmnt is gnratd fr band and band transfrmd pixls. Th blc has th highr cmputatin tas f ur architctur. Th blcs prcssing band and band ar ndd in th cas f D-DWT and multi lvls s. Ths blcs usd th arithmtic lgic pratin f dtails and apprximatin cfficints rspctivly. Th blc is usd fr strag f th and cfficints fr th nxt transfrmatins typs (D-DWT r multi lvls ). Th utput accumulatr is th final blc in th architctur. This prducs utput data by string th rsults f diffrnt transfrmatins; it is gnratd undr th cntrl f a synchrnus availabl signal. Md vl ad Bus Intrfac Unit Cntrllr Unit Vctr Start Transfrmd Cntrl Blc D-DWT B a n d B a n d Output Accumulatr Fig. Our dirct DWT Architctur Dsign B. Wring Prcdurs On vl D-DWT D-DWT Our dsign prsnts varius transfrmatins li th D-DWT, D-DWT and multi lvl f DWT. Th schm is lvl by lvl and dscribd as fllws: Th D-DWT, in first-lvl, th bus intrfac unit slcts data (pixls) frm input imag. Th transfrm mdul (, prcssing band and prcssing band ) dcmpss t th fur sub-bands,, and, and savs band t th mdul. Aftr finishing th first lvl, th cntrllr unit slcts data frm mdul. Th band is thn snt t th mdul transfrm t prfrm th scnd lvl. Th transfrm mdul dcmpss th band t th fur sub-bands,, and, and savs band t th mdul fr nxt lvl. This prcdur rpats until th dsird lvl (last lvl) is finishd. Th D-DWT, in first-lvl th bus intrfac unit slcts data (pixls) frm input imag. Th transfrm mdul () dcmpss t th tw sub-bands and and savs band t th mdul. In scnd lvl th cntrllr unit slcts data (band ) frm mdul. Th mdul transfrm (prcssing band ) dcmps th band t th tw sub-bands and and sav band t th mdul fr nxt lvl. Thy blcs f prcss ar shwn in Fig.5. rizntal Multi-lvl Strag : Outputs D-DWT, Vrtical, Strag : Vrtical, Outputs D-DWT Fig.5 Srial-Paralll mdul transfrms IV. EXPERIMETS RESUTS Th implmntatin f multi-lvl f D-DWT r D-DWT fr imag clc f siz is carrid ut ifing Schm (.S) using Xilinx XCV600E. In ur implmntatin, th numbr f lgic lmnts, numbr f rgistrs and th maximum prating frquncy ar cmputd and th synthtic rsults ar givn in Tabl I. W implmntd an xilinx FPGA dsign that fficintly prfrms bth D-DWT and D-DWT dpnding up n th cntrl signals start and md. Fig. shws th tp lvl schmatic f th intgratd chip. Whn md = 0, it signals th data path unit that D-DWT with band transfrmd nds t b prfrmd. Similarly, if md =, D-DWT and band transfrmd will b prfrmd. Whn md = 00 r 0 D-DWT r D-DWT dirctly must b cnfigurd. Th dscribd dsign has bn implmntd in VD using th MdlSim Simulatr and synthsizd, placd, and rutd using targt dvic f Xilinx XCV600E FPGA. Th architctur was simulatd fr vrificatin f th crrct functinality, by using th tst imags. Tabl I FPGA Synthsis rsults Paramtr Valus umbr f Slics 835 umbr f DFFs 656 umbr f UTs 3359 umbr f IOs 8 umbr f GCKs Frquncy (Mh 08 Pwr (mw) 7 Th prcssr ngin was abl t prat at 08 Mz. Furthrmr, during slf-tst at 50 Mhz, th rcnfigurabl prcssr cnsumd 7 mw. Th dsign rquirs a small ISB: WCE 009

4 Prcdings f th Wrld Cngrss n Enginring 009 Vl I WCE 009, July - 3, 009, ndn, U.K. numbr f GCKs, larg numbr f UTs and middl numbr f Slics. Thrfr ur architctur rquirs lss FPGA rsurcs (UTs, Slics) than thrs architcturs li th n dvlpd in []. In simulatins, w usd na cdd with 8 bpp, this was tan as input fr valuating th D-DWT r -D DWT with multi-lvls s algrithm. Our architctur transfrs imag int tw r mr filtrd and dcimatd imag crrspnding t diffrnt frquncy sub-bands. Th numbr f s prfrmd n riginal imag btaining sub-bands is calld sub-band lvl. Tabl II, shws cmputatin tim ur architctur with diffrnt thr lvls f D-DWT and D-DWT fr na and Barbara imags. W find that th cmputatin tim incras accrding t th incras lvl fr bth DWT (D and D) in thm tw imags. Th cmputatin tim f D-DWT ar lss than D-DWT in all lvls, bcaus th D-DWT uss nly th blc f prcssing. In ppsitin t D-DWT in this prcss, ur architctur us thr prcssing blcs: th blc prcssing, th prcssing band and prcssing band. thrfr ur D-DWT prcss prsnt highst tim than D-DWT. Th multi-lvl tas n lvl cmputatin f DWT fr D-DWT r D-DWT. Th n lvl tas n tims fr th crrspnding transfrm f DWT. In all cas ur architctur has th fastst cmputing tim small 3ms cmpard than as architctur in [7], fr thr lvl s. Th cmputatin tim has bn nrmalizd t th sam intrnal clc rat and calculatd by th fllwing quatin (6): T = i= T = T = 3 i ( ) 3... Whr th paramtr; is th imag siz, and th lvl DWT (D-DWT r D-DWT). Tabl II Cmputatin tim f thr lvls D-DWT D-DWT Imags Siz (56 56) Tim (ms) vl Tim(ms) vl st nd 3 rd st nd 3 rd na Barbara V. PERFORMACES AD COMPARISOS In this sctin, w prsnt th diffrnt prfrmanc f ur architctur srial-paralll and cmpar th rsults with th Rcursiv Pyramid Algrithm (RFA), mdifid in [7] and, (6) with Pyramid Algrithm Analysis dvlpd in [0], which hav th sam dvic f ur architctur. W cmpar ur architctur with thr diffrnt dvic li th rcnt wr f implmntatin f 5/3 lifting architcturs Basd-Blc (BB) implmntatin in FPGAs dvlpd in [], and architctur dvlpd in [] similar in ur architctur. Thrfr, this prfrmanc cmparisn f diffrnt architcturs is prsntd in Tabl III. Our architctur uss srial input f rad data (pixls f imag) and paralll prcssing f diffrnt pixls. Thrfr w cmpar ur architctur with diffrnt tplgis f D-DWT architcturs. Our architctur is fficint and flxibl li th n paralll architctur dvlpd in []. In Fig.6 w shwd n lvl na imag f D-DWT by lifting schm 5/3 filtr f ur architctur. W shw in this Fig.6 th diffrnt bands f D-DWT. Fig.6 On lvl f D-DWT Tabl III, cmpars th hardwar prfrmanc f th implmntd architctur. This tabl prsnts cmparativ rsults f ur architctur, in trms f frquncy, numbr f FPGA slics, cmputing tim, hardwar fficincy and cntrl cmplxity with thrs architcturs. W cmpar ur architctur at 08 Mhz with thr thr using sam XCV600E dvic; th mdifid RPA [7] at 5 Mhz, th n mdifid RFA [7] at 5 Mhz and architctur in [0] at 75 Mhz. W cmpar it again with thr diffrnt dvics; architctur APEX0KE [] at 66.8 Mhz and architctur BB XCVX5 in [] at 7.6 Mhz. As wll as bing highly scalabl, ur architctur rquirs 08 Mhz frquncy fr clc cycls. It uss th minimum strag unit siz pssibl t prfrm th transfrm. In thr cmparisns t th sam dvic architcturs givn in [7] (mdifid RPA and n mdifid RPA) and architctur in [0]. Our architctur rquirs,36 ms cmputatin tim cmpard t 5,88 ms and 7,68 ms rspctivly fr th mdifid RPA [7], and th n mdifid [7]. In numbr slics urs rquirs nly 835 slics cmpard t th 55 slics fr th mdifid RPA, 765 slics fr th n mdifid RPA and 70 slics fr architctur in [0]. In hardwar fficincy ur architctur is 00% usd, cmpard t th mdifid RPA in [7] whr 65.6% is usd and 69% fr th architctur in [0]. Thrfr ur architctur prsnts mr advantags cmpard than th thr architctur using sam dvic. In th sam tabl III, w cmpar ur architctur with th thr diffrnt dvics dvlpd in [] and in [], th sam cmparisn with thr dvis ar usd. Th slics numbr f ur architctur (835 slics) is vry lw cmpard t th tw architcturs [] (776 slics) and [] (66 slics). Our architctur is running against an avrag frquncy ISB: WCE 009

5 Prcdings f th Wrld Cngrss n Enginring 009 Vl I WCE 009, July - 3, 009, ndn, U.K. cmpard t th thr tw architcturs. In all diffrnt cmparisns, ur architctur prsnts a cmplxity simplr than that f all th thr prsntd architcturs. Tabl III Prfrmanc and Cmparisns D-DWT f ur Architctur Our RFA [7] RFA [7] Architctur Architctur Architctur Paramtrs Architctur mdifid n mdifid [0] [] (BB) [] 5/3 5/3 r 9/7 5/3 r 9/7 9/7 r 5/3 9/7 5/3 Implmntatin.S /A /A /A.S.S Imag siz /A Input data Prcisin 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits Dvic XCV600E XCV600E XCV600E XCV600E APEX0KE XCVX5 Cmputatin tim.36 ms 5.88 ms 7.68 ms /A /A /A umbr Slics Frquncy 08 Mhz 5 Mhz 5 Mhz 75 Mhz 66.8 Mhz 7,6 Mhz ardwar fficincy 00% 65.6% 00% 69% 00% 00% Cntrl cmplxity simpl cmplx cmplx cmplx cmplx cmplx VI. COCUSIO In this wr w hav prpsd flxibl architctur fr th implmntatin f multi-lvl DWT (D and D) by 5/3 filtr. A VD basd mthdlgy has bn usd targting FPGA dsign. Th rsults f th synthsis n a xilinx XCV600E shw a wring frquncy f 08 Mz allwing th prcssing f imags sizd pixls. Our architctur has th lwst hardwar cst in cmparisn t th diffrnt paramtrs includ in tabl III. Thrfr, ur architctur has bn crrctly vrifid as 00% hardwar utilisatin, fast cmputing tim and lw cntrl cmplxity. Our wrs ar suitabl fr th nxt gnratin imag/vid cmprssin using multilvl DWT. REFERECES [] M.A. Suhail and M.S. Obidat On digital Watrmaring in JPEG 000 Elctrnics, Circuits and Systms. Th 8 th IEEE Intrnatinal Cnfrnc n Vlum, ICECS 00, Pags: [] T. Acharya and C. Charabarti A Survy ifting-basd Discrt Wavlt Transfrm Architcturs Jurnal f VSI Signal, 3-339,3 Fbruary 006. [3] S. Barua, J.E. Charltta, K.A. Kttri and A.E. Bll An fficint architctur fr lifting-basd tw-dimnsinal discrt wavlt transfrms Intrgratin, th VSI Jurnal 38, 3-35, July 00. [] K. A. Kttri, A. E. Bll and J. E. Carltta Dsign f Multiplirlss, igh-prfrmanc, Wavlt Bans With Imag Cmprssin Applicatins IEEE Transactins Circuits and Systms I: Rgular Paprs, vl. 5, 3, March 00. [5] M. Martina and G. Masra Multiplirlss, Fldd 9/7-5/3 Wavlt VSI Architctur IEEE Transactins n Circuits and Systms- II:Exprss Brifs, vl.5. 9, Sptmbr 007. [6] X. Chngyi, T. Jinwn and. Jian w cmplxity rcnfigurabl architctur fr th 5/3 and 9/7 discrt wavlt transfrm Jurnal f Systms Enginring and Elctrnics vl. 7, pp , 006. [7] R.J.C. Palr, R.G. Girnés and A.S. Crts A vl FPGA Architctur f a -D Wavlt Transfrm Jurnal f VSI Signal, 73-8, August, 005. [8] P.C. Wu and.g. Chn An fficint architctur fr tw-dimnsinal discrt wavlt transfrm IEEE Transactin n Circuit and Systms and Systms fr Vid Tchnlgy, Vlum,, April 00, Pags [9] J. Jythswar and S. Mahapatra Efficint FPGA implmntatin f DWT and mdifid SPIT fr lsslss imag cmprssin Jurnal f Systms Architctur 53, , 9 January 007. [0] A. Bnrid, D. Crs and K. Bnrid Dsign and Implmntatin f Gnric -D Birthgnal Discrt Wavlt Transfrm n an FPGA IEEE, Prcdings f th 9 th Annual IEEE Sympsium n Fild-Prgrammabl Custm Cmputing Machins, 00. [] A. Pand, J. Zambrn Dsign and analysis f fficint rcnfigurabl wavlt filtr IEEE f Intrnnatinal Cnfrnc n Vlum, issu 8-0, May 008, Pags: [] M.E. Anglpulu, P.Y.K. Chung, K. Massls and Y. Andrpulus Implmntatin and cmparisn f 5/3 ifring D Discrt Wavlt Transfrm Cmputatin Schduls n FPGAs Jurnal f Signal Systms 5, 3-, 008. ISB: WCE 009