Fault Emulation: A New Approach to Fault Grading

Transcription

1 Fult Emultion: A New Approh to Fult Grding Kwng-Ting Cheng Shi-Yu Hung Deprtmentl of Eletril & Computer Engineering University of Cliforni, Snt Brr Snt Brr, CA Wei-Jin Di Quik-Turn Design System In. 440 Clyde Avenue Mountin View, CA Astrt In this pper, we propose method of using n FPGAsed emultion for fult grding. The rel-time simultion pility of hrdwre emultor ould signifintly improve the run-time of fult grding, whih is one of the most resoure-intensive tsks in the design proess. A seril fult emultion lgorithm is employed nd enhned y two speed-up tehniques. First, set of independent fults n e emulted in prllel. Seond, simultneous injetion of multiple dependent fults is lso possile y dding etr supporting iruitry. Beuse the reonfigurtion time spent on mpping the numerous fulty iruits into the FPGA ords ould e the ottlenek of the whole proess, using etr logi for injeting lrge numer of fults per onfigurtion n redue the numer of reonfigurtions, nd thus, signifintly improve the effiieny. Some modeling issues tht re unique in the fult emultion environment re lso ddressed. The performne estimtion indites tht this pproh ould e severl orders of mgnitude fster thn the eisting softwre pprohes for lrge designs. 1 Introdution In tody s qulity-onsious VLSI world, mesuring design s qulity y the fult overge is onsidered essentil. Usully, the fult overge figure is derived y fult simultion, whih is very time onsuming proess. Very few eisting fult simultors n hndle design with more thn 200K gtes without resorting to some DFT (Design for Testility) tehnique. Furthermore, even for those tools tht n hndle suh design, the proess my tke severl weeks or even months to omplete [9]. In reent yers, lot of effort hs een put into the development of ll kinds of prllel lgorithms tht n run fult simultion on mhines rnging from orse-grined distriuted to mssively prllel Connetion Mhine [3,11,13]. Their poliies inlude distriuting gtes or distriuting fults on multiple proessing elements (PEs), prtitioning the fult simultion kernel, or doing the fult simultion in pipelined mnner. Also, some lgorithms [4,6,7,8] using ero-dely model long with some effiient tehniques hve suessfully hndled very lrge sequentil iruits. On the other hnd, speil purpose hrdwre elertor for fult simultion [1] hs lso een devised nd implemented in ord tht plugs into SUN worksttion. In [1], onurrent fult simultion lgorithm is prtitioned into pipeline stges. Eh prt is performed y proessing element ontrolled y dedited miroprogrm. This pproh, requiring lrge numer of memory hips, hieves n order of mgnitude run time speed up over onventionl softwre fult simultor. Logi emultion s [2,15] re now ommerilly ville for fst prototyping nd for rel-time opertion nd verifition. A logi emultor onsists of oth hrdwre nd softwre. It n utomtilly implement the of gte-level logi design on ord omposed of doens of FPGA (Field Progrmmle Gte Arry) hips. Even lrger emultor n e uilt y integrting severl FPGA ords. The softwre ided implementtion proess n e divided into two phses, iruit ompiltion nd itstrem downloding s shown in Fig. 1. The iruit ompiltion proess mps the given gte-level netlist into the trget FPGA-ords. It involves iruit prtitioning, plement nd routing for FPGAs. The output of the ompiltion proess is itstrem representing the onfigurtion for the trget implementtion. The itstrem is then downloded into the FPGA-ords y progrmming the lookup tles (LUTs) inside eh FPGA hip, whih define oth the of eh (Configurle Logi Blok) nd the interonnetion etween s. After the itstrem downloding is ompleted, the is redy for emultion. Usully hrdwre emultion engine is used to id the emultion proess. Given test sequene, the emultion engine is responsile for pplying this sequene nd then heking if ny mismth ours etween the emulted responses nd the prestored orret responses. A stteof-the-rt logi emultor n implement logi design with up to 3 million gtes nd operte t speed of 100 KH to severl MH [17]. Aordingly, it n emulte 100K to severl million test ptterns per seond, whih is out 10,000 to 1,000,000 times fster thn the trditionl softwre simultors. ASIC netlist Compiltion (formt trnsltion, prtitioning, plement, routing) Bitstrem Configurtion downloding FPGA-hips Emultion Hrdwre Fig. 1. The synthesis proess of logi emultion. In this pper, we develop the tehniques to etend the usge of logi emultor for fult grding. This new pproh is referred to s fult emultion. A seril fult emultion sheme is dopted. To further enhne the performne, we eploit the prllelism etween set of fults to llow onurrent emultion. We lso propose dynmi fult injetion tehnique to redue the reonfigurtion time for fult injetion. Like rel hip, the FPGA ords nnot simulte the unknown logi vlue X properly. We will disuss the impt of the lk of X vlue in the fult emultion

2 environment nd del with this prolem using the dulriled logi. The rest of this pper is orgnied s follows. Setion 2 desries the senrio of our enhned seril fult emultion lgorithm nd gives performne estimtion. In Setion 3 we propose strtegy to hndle unknown logi vlue in hrdwre. Some eperimentl results will e presented in Setion 4, nd onluding remrks in Setion 5. 2 Fult Emultion 2.1 Primitive Senrio The seril fult emultion proess is shown in Fig. 2. One fult is injeted nd emulted t eh itertion. To injet seleted fult, the FPGA-hip tht ontins the fulty signl is reonfigured (slightly) to trnsform the fult-free iruit to the trget fulty iruit. This requires inrementl reompiltion (prepring new dt used to reprogrm the FPGAs) nd reonfigurtion (reprogrmming FPGA(s), whose ontents need to e hnged, through downloding the itstrem generted in the reompiltion phse). The test sequene is then pplied to the FPGA-ords tht implement the fulty iruit. The output response re ompred with the prestored epeted response. If ny mismth is oserved, the injeted fult is delred s deteted y the given test sequene. The proess ontinues until ll fults re injeted one. The preproessing prt inludes the implementtion of the originl design to the FPGA-ords nd the fult ollpsing tht will generte ollpsed fult list. Sine the iruit prtitioning lgorithm used in the tehnology mpper for FPGA will proly duplite prt of the originl netlist to minimie the mount of interonnetion ross hips, single stuk-t fult in the originl netlist my orrespond to multiple stuk-t fult in the FPGA-implementtion. Thus, the fult list generted for emultion is, in generl, set of multiple stuk-t fults. test vetors ompiltion onfigurtion FPGA-implementtion of fult-free iruit ASIC netlist Fult injetion reompiltion reonfigurtion fult emultion more fults? no overge report nd ditionry genertion fult list genertion (fult-ollpsing) fult list Any stuk-t fult n e injeted y simply hnging the ontents of the ffeted s. For emple, onsider the shown in Fig. 3(). To injet the s..0 fult t signl e, we n simply hnge its ontents to the one shown in Fig. 3(). In this wy, no glol reompiltion is required. A stuk-t fult of multipliity n requires reprogrmming of t most n s. With the informtion etrted t ompiltion-time, we n diretly mnipulte the orresponding itstrem of those ffeted s nd then downlod the modified portion into the FPGA-ords to injet fult effi- yes Fig. 2. Primitive seril fult emultion proess. iently. Current FPGA s rhiteture requires the reprogrmming of n entire hip even if just one needs to e hnged. However, ord-level prtil reprogrmming is possile. The emultion of [17] ontins the hipddressing iruitry on the ord to diret the itstrem to ny individul FPGA-hip. As result, it llows prtil reprogrmming for smll numer of hips in the. Aording to the Xilin s FPGA Dtook [16], it tkes out severl milli-seonds to reprogrm hip. This is out the ost to injet fult in our. In the future, if prtil reprogrmming n e done t the level, injeting stti fult n e even more effiient. e s..0 () The netlist efore fult injetion () After fult injetion Fig 3. Fult injetion y hnging the ontent of. The totl run time for suh proess onsists of two mjor prts: (1) The reompiltion nd reonfigurtion time. For eh fult injetion, ertin mount of omputtion is required to derive the informtion regrding wht needs to e hnged in the mpped FPGAs. The time spent in this omputtion is referred to s reompiltion time. The following reonfigurtion of the FPGAs lso tkes some time, whih is referred to s reonfigurtion time. If the sum of the reompiltion time nd the reonfigurtion time for one fult injetion is T, the totl time spent in reompiltion nd reonfigurtion will e nt, where n is the numer of fult injetions. (2) Emultion time. Suppose the emultor n typilly operte t 1 MH. Simultion of 100K vetors tkes only 0.1 seond. Therefore, the tul emultion time is only smll portion of the reompiltion nd reonfigurtion time tht domintes the totl run time of the entire proess. For lrge designs with lrge numer of fults to e emulted, pure seril fult emultion my e too run-time epensive due to the lrge numer of reonfigurtions nd reompiltions. Two tehniques re proposed to enhne the performne. (1) Injetion of multiple independent fults simultneously [5]. A set of fults F is lled independent if for eh fult f in F, the pperne of f will not ffet the vlues t the fult sites of other fults in F for ll possile input sequenes. Independent fults n e injeted simultneously. (2) We dd etr logi into the prototype design suh tht numer of dependent fults n e injeted in one onfigurtion. Using this tehnique, the totl numer of reompiltions nd reonfigurtions n e redued drmtilly. 2.2 Emulting Independent Fults in Prllel Definition 1: Output Imge of fult f, denoted s Imge(f), is the set of primry outputs tht re rehle struturlly from the fulty signl. In the se of sequentil iruit, it inludes those primry outputs tht re rehle from the fulty signl through numer of FFs. Definition 2: A set of fults F is lled (struturlly) independent if the output imges of the fults in F re mutully disjoint. Consider the emple in Fig. 4(), Suppose F is n independent fult set ontining two fults f1 nd f2. Then we

3 n emulte f1 nd f2 in single run y injeting oth fults into the fult-free iruit simultneously. The reson is Imge(f1) nd Imge(f2) re disjoint, we n still derive the et output responses of the iruit with only f1 nd the iruit with only f2 respetively. If we oserve fult effet t primry output in Imge(f1) (Imge(f2)), then we know f1 (f2) is deteted. In ontrst, if the output imges of f1 nd f2 re not disjoint like the se in Fig. 4(), then we nnot emulte these two fults simultneously due to the possile effet of fult msking. f1 f2 f1 f2 () independent fult set () dependent fults Fig. 4. Illustrtion of independent fult set. In the preproessing stge, we identify the independent fult sets. In the fult emultion stge, eh set is emulted in prllel. We etend the lgorithm proposed in [5] for sequentil iruits to identify the independent fult set. Eperimentl results of the verge sie of n independent fult set for ISCAS89 enhmrk iruits will e presented in Setion Dynmi Fult Injetion In generl, the verge sie of n independent fult set is quite smll for sequentil iruits (will e shown in Setion 4). In this setion, we propose dynmi fult injetion tehnique tht llows the injetions of lrge numer of fults within single FPGA-onfigurtion to redue the runtime overhed used y the lrge numer of reonfigurtions. Fig. 5 illustrtes the ide. Figure 5() shows portion of iruit whih hs een mpped into FPGAs. The smll oes represent the logi loks (s) in FPGAs. Suppose the stuk-t-1 fult t signl nd the stuk-t-0 fult t signl g re not independent. Therefore, they nnot e injeted nd emulted t the sme time. In Fig. 5() we dd ontroller, whih hs two outputs, nd y. An etr gte is lso 1 2 d g e f outputs dded for eh fult. For emple, n OR gte G 1 is dded for injeting the -stuk-t-1 fult dynmilly. When hs vlue 1, the fult is present (euse the output of the OR gte is onstnt 1 regrdless of the vlue t ). On the other hnd, if is set to 0, no fult effet is reted nd 1 eomes fult-free. Similrly n AND gte, G 2, is dded for injeting the g stuk-t-0 fult dynmilly. When y hs vlue 1, the fult is present. When y is set to vlue 0, 2 is fult-free. The ontroller is designed in suh wy tht only one fult is present (tivted) for eh emultion run. For emple, initilly the ontroller produes y = 10 t the eginning to emulte -stuk-t-1 iruit. After the test sequene is pplied, we mke ontroller to produe y = 01, whih tivtes the seond fult, g-stuk-t-0. If the ontroller nd the gtes G 1, G 2 re dded in the originl netlist efore ompiltion, then we n emulte two fults (tht re not independent) without ny reonfigurtion. Note tht two psses of emultion re still required. But sine the emultion time is not the ottlenek, sving in the reonfigurtion time will reflet in the overll fult grding time. The performne estimtion in Setion 2.4 will show the potentil of this tehnique. Sine the injeted fults need to e tivted one y one during the emultion stge, irulr shift register (CSR) n e used to implement the fult tivtion ontroller. At the eginning of the emultion session, the ontents of this shift-register is initilied to with eh FF onneted to its orresponding fult tivtion signl. After the first emultion run is ompleted, the eternl lok for CSR is pplied to hnge the ontents of CSR to , tht tivtes the seond dynmi fult. Similr opertions re performed for the susequent tivtion of the rest of the injeted dynmi fults. Note tht one single fult tivtion signl n e used to tivte set of independent fults. For emple, the tivtion signl in Fig. 5() n lso e onneted to other s to tivte fults tht re independent of -stuk-t-1 fult. Similr to the stti fult injetion, reompiling the entire or prtil iruit to injet those dynmi fults is time-onsuming. We propose method to injet dynmi fults without hnging the lyout of the FPGAs. Our gol is to injet dynmi fult y only hnging the ffeted s ontents like the wy we injet stti fult. Suppose is ple of implementing ny ritrry 5-input. We dopt onservtive poliy tht mps only 4-input to eh. The intention is to reserve one input terminl in eh for fult tivtion signl. Fig. 6 illustrtes this ide. The of the is epressed in the Shnnon- () A portion of n originl iruit mpped into FPGAs enle fult tivtion ontroller y G1 1 d ef 2 G2 g outputs d good g(,,,d) good g(,,,d) MUX d fulty f(,,,d) good g(,,,d) MUX () Dynmi fults, signl stuk-t-1 nd signl g stuk-t-0, re injeted y dding two gtes, G1 nd G2. Fig. 5. Dynmi fult injetion y dding etr iruitry. () A fult-free () with dynmi fult injeted ( regrdless of the vlue of ) ( tivted s = 1 ) Fig. 6. Mpping only 4-input to eh for injeting dynmi fults effiiently.

4 Epnsion form. It ontins two 4-input l loks shring the sme input signls,,,d. Whih lok s will e seleted to the output t run time depends on the vlue of the fult tivtion signl, tht ontrols the output multipleer. In Fig. 6() the output ehiits fult-free regrdless of the vlue of euse oth l loks relie identil fult-free iruits. On the other hnd, Fig. 6() shows with n injeted dynmi fult. When equls 0, the output is fult-free. But when equls 1, the injeted dynmi fult is tivted nd the fulty f(,,,d) is seleted to the output. Rell tht the of f(,,,d) is derived y evluting the of the when the trget fult is present s shown erlier in Fig. 3. FPGA-hip CSR-lok FF 1 FF 0 FF 0 FF 0 Cirulr Shift Register Fig. 7 shows the glol piture of this sheme. As illustrted, eh FF of the uilt-in ontroller is onneted to set of s ( olumn in this se). Initilly, we mp 4-input fult-free to eh like Fig. 6() to msk ll fult tivtion signls. During reonfigurtion, we mnipulte the ontents of the ffeted s like Fig. 6() to injet the seleted fults dynmilly (shdow s). Reompiltion is ompletely voided euse the lyout is fied. This tehnique trdes emultion pity for effiient dynmi fult injetion. Eperimentl results for ISCAS enhmrk iruits show tht only 22% inrese in terms of the numer of etr s for this onservtive 4-input relition (See Setion 4). The entire proedure of fult grding with this ide is summried in Fig. 8. For lrge design tht requires numer of FPGAs, similr ontroller should e uilt in eh hip nd onneted in glol wy tht only one fult tivtion signl is ti- Fig. 7. The fied lyout of fult tivtion signls ontrolled y glol irulr shift register. 1. Ciruit modifition: Build in the irulr shift register. Connet the output of eh FF to its lient s. 2. Compiltion: Compile the modified iruit. (One for the entire proedure) 3. Dynmi fult set seletion: Selet the fults to e emulted for the net onfigurtion. At most one fult for eh group of s. 4. Dynmi fult Injetion: Chnge the ontents of the ffeted s. 5. Emultion session: Ativte the injeted fults serilly until ll injeted fults re emulted. Eh fult goes through its own emultion run. 6. Go k to step 3 until ll fults re emulted. Fig. 8. Fult emultion proedure using proposed dynmi fult injetion. vted in the entire during ny emultion session. 2.4 Performne Estimtion Suppose the sequentil iruit to e emulted ontins N g gtes nd N f ollpsed fults. There re T input ptterns. The reprogrmming time of single Xilin s FPGA-hip is ssumed to e 0.5 seond pessimistilly (Dt Book s estimtion is in the order of 1 ms [16]). The itstrem mnipultion time is negligile nd the emultion ord is ssumed to operte t the speed of 1 MH. The totl fult grding time using the seril fult emultion lgorithm will e: Time (seril fult emultion) = T originl + N f *(reonfigurtion time + emultion time) = T originl + N f * (0.5 + T*10-6 ) (se T originl is the implementtion time of the originl fultfree design. Consider smple iruit with 100K gtes, 100K ollpsed fults, nd test sequene of 50K test ptterns. The seond term eome 100K( )=55K seonds, out 15.2 hours without fult dropping. Now if we inorporte oth tehniques mentioned ove, the fult emultion time n e epressed s: 6 T originl + { R T 10 } Dynmi Independent Where Dynmi is the verge numer of dynmi fults injeted in eh onfigurtion nd Independent is the verge sie of n independent fult set. The first term is the totl time for reonfigurtion nd the seond term is the totl emultion time. R is the reonfigurtion time, whih is longer thn its ounterprt in the seril fult emultion. Suppose we injet 5000 dynmi fults per onfigurtion for 100K gte iruit (out 20 fults per FPGA-hip), the reonfigurtion time R is in the order of tens of seonds, sy 1 minute. The verge sie of the independent fult set, Independent, for ISCAS89 enhmrk iruits is out Therefore, the estimted fult emultion time (eluding T originl ) eomes: 6 { R T 10 } Dynmi Independent 100K 100K 6 = { min K 10 } 5K 1.36 = 20 min min. = 81 min. 3 Hndling the Unknown Logi Vlue A softwre fult simultor typilly use the 3-vlued logi, 0, 1, nd X, where X is n rtifiil logi vlue to represent the unknown. The emultion s, similr to n tul hip, do not hve the notion of X. The lk of X vlue hs oth disdvntges nd dvntges. The presene of the hypertive fults tht use the X vlue to populte lrge portion of the design retes lrge numer of unneessry events in simultion using the X vlue. Simultion for these fults is very omputtionlly epensive nd signifintly degrdes the performne of the softwre fult simultors. However, on the other hnd, fult emultion my not e le to differentite the hrd-deteted fult nd the potentilly deteted fult euse of the lk of the X vlue. A fult is hrd deteted if fult effet (0/1 or 1/0) ppers t primry output. While fult is only potentilly deteted when either 1/X (i.e., the fult-free vlue is 1 nd the fulty vlue is unknown X) or 0/X ppers t the primry outputs.

5 Fult emultion will lssify potentilly deteted fult s either deteted or not deteted depending on the power-up stte of the emultion. For synhronous iruits, the perentge of potentilly deteted fults is usully very low (Some results on ISCAS enhmrk iruits will e presented in Setion 4). We n use dul-riled logi to ommodte the unknown logi vlue X in our emultion. The ide is to use two wires to represent 3-vlued logi signl. For instne, 00 represents logi 0, 11 represents logi 1, nd 01 represents unknown X, while the unused ode 10 is don t re term tht my e used to minimie the iruit. This enoding n e implemented y simple duplition of the originl netlist. For emple, onsider n AND gte shown in Fig. 9(). The new ell to implement the enoding sheme is given in Fig. 9(). It doules the fnins, the gte ounts, nd the fnouts. y.0 y.0.1 y.1 () Originl ell () The ell implemented in hrdwre emultor Fig. 9. A primitive non-inverting gte for hndling 3-vlued logi using dul-riled signls. y.0 y.0.1 y.1 () Originl ell () The ell implemented in hrdwre emultor Fig. 10. A dul-riled NOR-gte The orretness of the lity n e verified esily. Fig. 10 shows the trnsformtion of n NOR-gte. The two wires of the output signl need to e swpped. This simple duplition or swpped duplition trnsformtion n e pplied to omple gtes. We lso need to duplite ll the FFs nd implement them with set/reset fetures. At the eginning of n emultion run, the FFs re reset to 01 to represent unknown initil vlue X. One property tht n e used to redue the overhed is sed on the oservtion tht not every signl hs the possiility to hve n unknown vlue. Those signls tht re not rehle from the FFs (only rehle from primry ), will never e ontminted y the X vlue, nd thus do not hve to use doule rils. Insted, they remin single riled. When these signls feed into the X -ontminted region, they re duplited nd hnged into dul-riled. Tht is, 0 eomes 00 nd 1 eomes Eperimentl Results Severl eperimentl results on ISCAS enhmrk iruits re presented in this setion. Tle 1 shows the verge sie of n independent fult set for some enhmrk iruits. It indites the verge numer of fults tht n e injeted nd emulted in prllel. This property llows out 1.36 times inrese of performne without ny overhed when it is dded to the senrio of the seril fult emultion. Tle 2 shows the pproimte re penlty in terms of the numer of etr s to implement iruit under emultion on FPGA-ord using the proposed dynmi fult injetion pproh. The result is otined y mpping only one 4- input into using the tehnology mpper of SIS [10]. The overhed of the FFs tht form the fult tivtion ontroller, CSR, is reltively smll nd thus not shown here. The verge overhed for the proposed dynmi fult injetion tehnique is out 22%. Tle 3 shows the perentge of the potentilly deteted fults tht re otined y running softwre simultor, PROOFS [12], using two test sequenes, one is generted y n ATPG progrm nd the other is rndom. In the olumns lled fult-overge,the first numer is the fult overge ounting only hrd-detetion s detetion. The seond numer onsiders oth hrd-detetion nd potentil-detetion s detetions. If we do not use the dul-riled logi, the fult emultor would report overge within these two numers. Sine the differene etween these two numers is smll, the fult overge reported y the fult emultor (without dulriled logi) would e very lose to either one of the listed fult overges reported y the softwre simultor. Tle 4 shows the estimted overhed of pplying the dul-riled logi to hndle the X logi vlue in terms of the numer of etr gtes. The olumn under title -region represents the numer of gtes tht re rehle from present stte lines nd thus need to e duplited. 5 Conlusion Fult simultion for lrge sequentil iruits remins very time-onsuming tsk. With the inresing progress of the Field-Progrmmle Gte-Arry tehnology nd the logi emultion, hrdwre fult emultor hs eome not only fesile ut lso very effiient ompred to the eisting softwre-sed or hrdwre-elertor-sed pprohes. This pper ddresses the issues of reliing fult emultor sed on n eisting logi emultion. In ddition to primitive senrio of seril fult emultion, two tehniques re proposed to further speed up the proess: (1) Eploit the onept of the independent fult set to llow prllel fult emultion. (2) Use dynmi fult injetion to rek the performne ottlenek, i.e., reonfigurtion time. The eperimentl results show tht the overhed of our onservtive poliy of 4-input relition for effiient dynmi fult injetion is modest. Menwhile, the issue of inorporting the unknown logi vlue in the emultor is ddressed. A dul-riled logi n e used to ugment the emultor with the pility to emulte the unknown logi vlue nd thus to differentite the hrd deteted fults from those potentilly deteted fults. It is worth mentioning tht the use of the dul-riled logi is not lwys neessry: () For iruits with reset stte, there will e no potentilly deteted fults. () For synhronous iruits, the perentge of the potentilly deteted fults is usully very low. The performne estimtion of the proposed fult emultion sheme shows tht this novel pproh ould hieve severl orders of run time improvement s ompred to the eisting pprohes. Referenes 1. P. Agrwl, V. D. Agrwl, nd K. T. Cheng, Fult Simultion in Pipelined Multiproessor System, Pro. Int l Test Conferene, pp (Aug. 1989).

6 2. M. Butts, J. Btheller, nd J. Vrghese, An Effiient Logi Emultion System, Pro. Int l Conf. on Computer Design (ICCD-92), pp (Ot. 1992). 3. P. A. Du, R. K. Roy, J. A. Arhm, nd W. A. Rogers, Fult Simultion in Distriuted Environment, Pro. 25th Design Automtion Conferene, pp (June 1988). 4. N. Gouders, R. Kiel, PARIS: A Prllel Pttern Fult Simultor for Synhronous Sequentil Ciruits, Pro. Int l Conferene on Conputer-Aided-Design, pp (Nov. 1991) 5. V. S. Iyengr nd D.T. Tng, On Simultion Fults in Prllel, Digest of Ppers 18th Int l Symp. on Fult-Tolernt Computing, pp (June 1988). 6. D. H. Lee nd S. M. Reddy, On Effiient Simultion For Synhronous Sequentil Ciruits, Pro. 29th Design Automtion Conferene pp (June 1992). 7. H. K. Lee nd D. S. H, HOPE: An Effiient Prllel Fult Simultor for Synhronous Sequentil Ciruits, Pro. 29th Design Automtion Conferene pp (June 1992). 8. H. K. Lee nd D. S. H, New Methods of Improving Prllel Fult Simultion in Synhronous Sequentil Ciruits, Pro. Int l Conferene on Conputer-Aided- Design, pp (Nov. 1993). 9. C.Y. Lo, H. N. Nhm, nd A. K. Bose, Algorithms for n Advned Fult Simultion System in Motis, IEEE Trns. on Computer-Aided Design CAD-6, pp (Mrh 1987). 10.R. Murgi, N. Shenoy R. K. Bryton, nd A. Sgiovnni Vinentelli. Improved Logi Synthesis Algorithms for Tle Look Up Arhiteture. Proeeding of Interntionl Conferene on Computer-Aided Design, pp , (Nov. 1991). 11.V. Nrynn nd V. Pithumni, A Mssively Prllel Algorithm for Fult Simultion on the Connetion Mhine, Pro. 26th Design Automtion Conferene, pp (June 1989). 12.T. M. Niermnn, W. T. Cheng, nd J. H. Ptel, PROOFS: A Fst, Memory Effiient sequentil Ciruit Fult Simultor, IEEE Trns. on Computer-Aided Design CAD-11, pp (Fe. 1992). 13.D. L. Ostpko, Z. Brili, nd G. M. Silermn, Fst Fult Simultion in Prllel Proessing Environment, Pro. Int l Test Conf., pp (Sept. 1987). 14.E. G. Ulrih nd T. Bker, Conurrent Simultion of Nerly Identil Digitl Networks, Computer, pp (April 1974). 15.S. Wlters, Computer-Aided Prototyping for ASIC-Bsed System, IEEE Design & Test of Computer, pp (June 1991). 16.Xilin In., The Progrmmle Gte Arry Dt Book, Xilin Sn Jose, Cliforni, (1992). 17.Quik-Turn Design System In., MARSIII Emultion System User s Guide, Mountin View, Cliforni, (Jn. 1994). iruit # gtes # fults no. of independent fult set Avg. SIZE independent fult set s s s s s s s s s s s s Averge Tle 1. The verge sie of n independent fult set Ciruit # gtes originl # s #s using dynmi fult injetion Inrese RATIO s s s s s s s s s s s s Averge Tle 2. The etr s for dynmi fult injetion iruit # fults fult-overge (RANDOM) hrd /+potentil fult-overge (generted) hrd / +potentil s / / 100 s / / s / / s / / s / / s / / s / / s / / s / / s / / s / / s / / s / / s / / s / / s / / s / s / s / Averge / / Tle 3. The perentge of the potentilly deteted fults iruit # originl gtes sie of -region overhed rtio s s s s s s s s s s s s Averge Tle 4. The overhed of using dul-riled logi