Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework

Transcription

1 R-17 SASIMI 015 Proeeings Tehnology Mpping Metho for Low Power Consumption n High Performne in Generl-Synhronous Frmework Junki Kwguhi Yukihie Kohir Shool of Computer Siene, the University of Aizu Aizu-Wkmtsu City, Fukushim, Jpn {m ,kohir}@u-izu..jp Astrt In generl-synhronous frmework, in whih the lok is istriute perioilly to eh register ut not neessrily simultneously, iruit performne is expete to e improve ompre to omplete-synhronous frmework, in whih the lok is istriute perioilly n simultneously to eh register. To improve the iruit performne more, logi iruit synthesis for generl-synhronous frmework is require. In this pper, uner the ssumption tht ny lok sheule is relize y n iel lok istriution iruit, when two or more ell lirries re ville, tehnology mpping metho whih ssigns ell to eh gte in the given logi iruit y using integer liner progrmming is propose. In experiments, we show the effetiveness of the propose tehnology mpping metho. I. Introution In the onventionl integrte iruit esign, the omplete-synhronous frmework (-frme), in whih lok is istriute simultneously to eh iniviul register, hs een pursue for esy unerstning n esy esigning. However, the performne improvement on the premise pprohes limit, n the ost for the premise is very high. On the other hn, in generl-synhronous frmework (g-frme) [1 3] in whih lok is not ssume to e istriute to ll registers simultneously, sine ely in g-frme my e use more effiiently thn tht in -frme, it is expete to improve the performne suh s the lok perio, lok re, power onsumption, n reliility with low osts. Previous works for g-frme re summrize in [4]. In mny stuies of g-frme, lok sheuling lgorithms [1 3, 5 8] n lok istriution iruit synthesis lgorithms [9] [10] for given logi iruits hve een investigte. However, the given logi iruits re synthesize in -frme. Sine the optimum logi iruit in g-frme is ifferent from tht in -frme, the performne might not e improve enough in g-frme. In orer to improve the lok perio in -frme, the iruits re synthesize so tht the mximum ely etween registers is s smll s possile. However, in g-frme, the lok perio might not e reue even if the mximum ely is reue sine the lok perio is otine y onstrint grph whih is efine y mximum n minimum elys etween registers Fig. 1. Ciruit grph G [3]. Therefore, the logi iruit with low osts n e otine y synthesizing logi iruit for g-frme. The ely insertion [11 14], gte sizing [15] n register relotion [1, 17] hve een propose. Although the lok perios re improve y the existing methos, they o not tke power onsumption n how to relize the iruit moifition into onsiertion n/or o not gurntee the optimlity. When two or more ell lirries re ville, there is tre-off etween the ely n power onsumption for eh gte. The ssignment for ell in ell lirries to eh gte is lle tehnology mpping. In this pper, uner the ssumption tht ny lok sheule is relize y n iel lok istriution iruit, when two or more ell lirries re ville, tehnology mpping metho whih ssigns ell to eh gte in the given logi iruit y using integer liner progrmming (ILP) is propose. In experiments, we show the effetiveness of the propose tehnology mpping metho. II. 4 Preliminries In this pper, we ssume tht iruit onsists of registers, gtes, n wires onneting registers n gtes. We refer to registers, gtes, n wires s elements. A iruit is represente y the grph G =(V,E), where V is the vertex set orresponing to elements in the iruit n E is the irete ege set orresponing to signl propgtions in the iruit. In this pper, we ssume tht eh element hs unique non-negtive ely. Let (v) e the weight of v V whih orrespons to the ely of orresponing element. Let V r e the register set of G n V g e the gte set of G. Neessrily, V r n V g re susets of V. An exmple of the iruit grph is shown in Fig. 1. In Fig. 1, {,,, } is the register set, n the vlue in eh vertex represents

2 S() T Time D mx(,) S() D min(,) S() S() Fig.. Timing hrt T-1 T-1 T-8 T- T- D mx(,) D min(,) ()H(G) ()H(G, 9) Fig. 3. Constring grph for iruit G shown in Fig. 1. ely. A. Generl-synhronous frmework In g-frme, the lok input timing of register my e ifferent from other registers. The lok timing S(r) of register r is efine y the ifferene etween lok rrivl time etween r n n ritrry hosen referene register. A iruit works orretly with lok perio T if the following two types of onstrints re stisfie for every register pir with signl propgtions (Fig. ) [1]. Setup (No-Zero-Cloking) Constrints S() S() T D mx (, ) Hol (No-Doule-Cloking) Constrints S() S() D min (, ), where D mx (, ) is the mximum ely n D min (, ) is the minimum ely from register to. Let T S (G) e the minimum lok perio of iruit G in g-frme uner the ssumption tht lok n e input to eh register t n ritrry timing. The minimum lok perio T S (G) ofg in g-frme is etermine y the onstrint grph H(V r,e r ), where vertex set V r orrespons to registers in G n irete ege set E r orrespons to two types of onstrints [3]. An ege in E r from register to with weight D min (, ), lle D-ege, orrespons to the hol onstrint, n n ege from register to with weight T D mx (, ), lle Z-ege, orrespons to the setup onstrint. Herefter, the onstrint grph H(V r,e r ) is simply represente y H(G). Let H(G, t) e the onstrint grph in whih the lok perio T of Z-eges in H(G) is set to t. Theorem 1 [3] T S (G) is the minimum t suh tht there is no negtive-yle in the onstrint grph H(G, t). Fig. 4. Ciruit G whih is ssigne ell of two or more ell lirries to eh gte Fig. 5. Constrint grph H(G 8) for iruit G shown in Fig For exmple, the ely from register to in G shown in Fig. 1 is 1 whih is the mximum ely etween registers. Therefore, the minimum lok perio in -frme is 1. The onstrint grph H(G, T ) is shown in Fig. 3 (). Sine H(G, 9) shown in Fig. 3 () inlues no negtiveyle n yle (,,, ) shown in Fig. 3 () is negtive when T<9, the minimum lok perio T S (G) is9. B. Tehnology Mpping When two or more ell lirries re ville, there is tre-off etween the ely n power onsumption for eh gte. The iruit G otine from G shown in Fig. 1 y ssigning ell in two or more ell lirries to eh gte in onsiertion of the minimiztion of T s is shown in Fig. 4. The gte represente y slsh in Fig. 4 is ifferent from tht in G. The onstrint grph H(G, 8) is shown in Fig. 5. Sine H(G, 8) inlues no negtive-yle n yle (,,, ) is negtive when T < 8, the minimum lok perio T S (G )is8. G is expete to eome low power onsumption ompre with G sine ell lirry with lrge ely hs low power onsumption. Therefore, G is expete to eome low power onsumption n high performne in g-frme ompre with G. III. 1 Propose Metho Setup n Hol onstrints re given y liner expression [1]. Therefore, when the ely of eh iruit element is given, the prolem whih otins the minimum lok perio T s is efine s follows: ojetive onstrints Setup onstrins minimize S(r i ) S(r j ) T D mx (r i,r j )((r i,r j ) E r (G)) (1) T

3 Hol onstrins S(r j ) S(r i ) D min (r i,r j ) ((r i,r j ) E r (G)) () D 1 D D 3 D 4 D 5 ILP1 whih is n ILP whih minimizes the lok perio in g-frme y tehnology mpping n ILP whih is n ILP whih mximizes the numer of the ell with low power onsumption with the minimum lok perio y tehnology mpping in g-frme re formulize y moifying the ove prolem efinition. A. ILP1 When k ell lirries re ville, let i (1), i (),..., i (k) e the elys of ells to gte i. ILP1 whih is n ILP whih minimizes the lok perio in g-frme y tehnology mpping is efine s follows: ojetive onstrints For e =(t, u) E, if t, u / V r, if t V r,u / V r, if u V r,t / V r, if t, u V r, For i V g vrile onstrints minimize T r t r u D u (3) t u D u (4) S(t) r u D u (5) S(t) u D u () r t S(u) T 0 (7) t S(u) 0 (8) S(t) S(u) T 0 (9) S(t) S(u) 0 (10) k g i (j) = 1 (11) j=1 D i = k i (j) g i (j) (1) j=1 g i (j) ={0, 1} (i V g, 1 j k) (13) Let r, e vriles to reue the numer of the onstrints s mentione lter. Let g i (j) e vrile whih is set to either 0 or 1 n it represents the ssignment for the ell in ell lirry j with ely i (j) to gte i. The ell with ely i (j) is ssigne to gte i if n only if D 0 D 8 Fig.. Formultion to ILP. g i (j) = 1. Eqution (11) mens tht extly one ell is ssigne to eh gte. Eqution (1) sets the ely of ssigne ell to the gte ely D i. Equtions from (3) to (10) orrespon to Setup onstrints (eqution (1)) n Hol onstrints (eqution ()). For exmple, Setup n Hol onstrints etween register (, ) of the iruit G shown in Fig.1 re isusse (Fig. ). The onstrints from (3) to (10) on the pths etween register (, ) in iruits G re efine s follows: D S() r 0 D 0 (14) S() 0 D 0 (15) r o r 4 D 4 (1) o 4 D 4 (17) r o r D (18) o D (19) r 4 r 5 D 5 (0) 4 5 D 5 (1) r r 5 D 5 () 5 D 5 (3) r 5 S() T 0 (4) 5 S() 0 (5) Eqution () is otine y the ition of equtions (14), (1), (0), (4). Equtions from (7) to (9) re similrly otine y the ition of equtions from (14) to (5). S() S() T D 0 D 4 D 5 () S() S() T D 0 D D 5 (7) S() S() D 0 + D 4 + D 5 (8) S() S() D 0 + D + D 5 (9) Equtions from () to (9) men tht the elys of ll pths etween register pir (, ) stisfy Setup n Hol onstrints. The numer of equtions for ll pths etween register pirs suh s equtions from () to (8) my inrese exponentilly sine the orer of the numer of pths etween registers eomes exponentil oring to the numer of gtes in some ses. On the other hn, the numer of equtions from (3) to (10) is O( E g ) n the numer of equtions (11) n (1) is O( V g ). B. ILP In ILP1, lthough the lok perio is minimize in g- frme, the power onsumption is not tken into onsiertion. Therefore, fter the minimum lok perio y D

4 TABLE I Cell Lirries. Type of Trnsister High integrtion High spee Low Lekge SNC MNC Stnr SN MN High Spee SZ MZ Power onsumption MZ T MZ Ts MN T MN Ts MNC T MNC Ts ILP1 Ts ILP Ts Clok perio Fig. 7. Averge of lok perio n power onsumption. tehnology mpping T opt is otine y ILP1, the power onsumption is minimize without inresing the minimum lok perio. ILP whih is the minimiztion of the power onsumption n whih hieves the minimum lok perio T opt y tehnology mpping is formulize se on ILP1. The ojetive is efine s follows: Minimize k {α j g i (j)} j=1 α j is the priority of ell lirry j. The ell lirry with low power onsumption is ssigne preferentilly y setting smller vlue to α j for the ell lirry with low power onsumption. In orer to minimize the power onsumption without inresing the minimum lok perio T opt whih is otine y ILP1 in g-frme, the following eqution is e to ILP1 s onstrint. T T opt Other onstrints re the sme s the onstrints of ILP1. IV. Experimentl Results We use the ell lirries of 5nm CMOS stnr ell in experiments. The ell lirries hve two types: high integrtion n high spee. Moreover, they re ivie into high spee, stnr n low lekge oring to the type of trnsistor. It is shown in Tle I. The ely n power onsumption of the iruit were evlute y Synopsys Design Compiler. The SDF file ws generte y using only eh of ell lirries MZ, MN, MNC. Moreover, the ely written in SDF file ws set s the ely of eh ell, n ILP1 n ILP were formulize. ILP1 n ILP otine solutions using CPLEX[18] in PC with.93ghz Intel Core i7 CPU n GB RAM. The verilog files orresponing to the ell ssignment otine y ILP1 n ILP were me y our progrm. The perfor- TABLE II The numer of ells in eh ell lirries. ILP1 ILP #gte #MZ #MN #MNC #MZ #MN #MNC s s s s s s s s s s s s s s5n s s s s s s s s s s s s s s s s s s s s s x x x s s s x x x s x x x s x x x s x x x s x x x s x x x s x x x s x x x s s prolog x : out of memory mne of the iruits otine y ILP1 n ILP ws lso evlute y Design Compiler. The experiment results of the iruits onstitute from only eh ell lirry n the iruits otine y ILP1 n ILP re ompre. We pplie these methos to ISCAS89 enhmrk suite. The numer of ells in eh ell lirry of the iruits otine y ILP1 n ILP is shown in tle II. The experiment results normlize using the minimum lok perio n the power onsumption of the iruits onstitute from only MZ re shown in tle III. In ILP, in 9 iruits, the solution is not otine y ILP ue to out of memory in CPLEX. The solution whih is not otine is shown y x in tle II n tle III. Ave. shown in tle III is the verge vlue of remining 39 iruits. The reltion of verges of the minimum lok perio n power onsumption is shown in Fig. 7. In orer to hek the effet of the power onsumption y tehnology mpping, the power onsumption is estimte without hnging frequeny n synthesizing lok tree. Therefore, sine gtes in g-frme re the sme s those in -frme, the power onsumption in g-frme n tht

5 in -frme re the sme. The minimum lok perio in g-frme is smller thn tht in -frme. Although etils re omitte for the spe of the pper, in ILP1, the verge of reltive error of the minimum lok perio T s otine y CPLEX n the minimum lok perio T opt whih is evlute y Design Compiler is 0.55%. In ILP, the verge of reltive error is.38%. In ILP1 n ILP, sine the ely of eh gte is otine y the ely of the iruit onstitute from only eh ell lirry, the error of the estimtion of gte ely is ourre y susequent gtes. In ILP1, in 1 iruits, the minimum lok perio T s n the power onsumption of iruits otine y ILP1 re smller thn those of iruits onstitute from only MZ. In the remining 7 iruits, the minimum lok perio T s n the power onsumption of iruits otine y ILP1 re the sme s those of iruits onstitute y only MZ sine most gtes in the iruits otine y ILP1 re ssigne ells in MZ. In 13 iruits, the minimum lok perio T s n the power onsumption of iruits otine y ILP re smller thn those of iruits onstitute from only MZ. In 5 iruits, lthough the minimum lok perio T s of iruits otine y ILP re the sme s tht of iruits onstitute from only MZ, the power onsumption of iruits otine y ILP is smller thn tht of the iruit onstitute from only MZ. In remining 1 iruits, lthough the power onsumption of iruits otine y ILP is smller thn tht of the iruit onstitute from only MZ, the minimum lok perio T s of iruits otine y ILP is lrger thn tht of iruits onstitute from only MZ sine the error is ourre y the estimtion of elys. The power onsumption of iruits otine y ILP is smller thn tht of iruits otine y ILP1 sine most gtes in the iruits otine y ILP re ssigne ells of ell lirry with low power onsumption. However, the minimum lok perio T s of iruits otine y ILP is lrger thn tht of iruits otine y ILP1. In experiment results, the iruits with low power onsumption n high performne re otine y ILP. V. Summry n Conlusions In this pper, we propose the tehnology mpping metho for low power onsumption in g-frme. The propose tehnology mpping metho improves lok perio n power onsumption. Moreover, in the experiments, the effetiveness of the propose tehnology mpping metho is shown. In our future works, we will propose heuristi tehnology mpping metho whih ssigns ell to eh gte sine solution is not otine y ILP in lrge iruits. Aknowlegements This work is supporte y VLSI Design n Eution Center (VDEC), the University of Tokyo in ollortion with Synopsys In., eshuttle In. n Fujitsu Semionutor Lt. This work is prtly supporte y JSPS KAK- ENHI Grnt-in-Ai for Young Sientists (B) Referenes [1] J. Fishurn, Clok skew optimiztion, IEEE Trn. on Computers, vol. 39, no. 7, pp , [] R. Deoker n S. Sptneker, A grph-theoreti pproh to lok skew optimiztion, in ISCAS, pp , [3] A. Tkhshi n Y. Kjitni, Performne n reliility riven lok sheuling of sequentil logi iruits, in ASP-DAC, pp , [4] A. Tkhshi, [invite tlk] generl synhronous iruits using glol lok -esign methoologies, tools, n prospets, IPSJ SIG Tehnil Report, 00-SLDM-1, vol. 00, no. 111, pp , 00. [5] A. Tkhshi, Prtil fst lok-sheule esign lgorithms, IEICE Trns. Funmentls, vol. E89-A, no. 4, pp , 00. [] Y. Zhi, H. Zho, n X. Zeng, A prtil metho for multi-omin lok skew optimiztion, in ASP-DAC, pp. 51 5, 011. [7] L. Li, Y. Lu, n H. Zhou, Optiml multi-omin lok skew sheuling, in DAC, pp , 011. [8] Y. Kohir n A. Tkhshi, -st se liner time optimum two-omin lok skew sheuling, in ASP-DAC, pp , 014. [9] K. Inoue, W. Tkhshi, A. Tkhshi, n Y. Kjitni, Sheule-lok-tree routing for semi-synhnorous iruits, IEICE Trns. Funmentls, vol. E8-A, no. 11, pp , [10] S. Ishijim, T. Utsumi, T. Oto, n A. Tkhshi, A semi-synhronous iruit esign metho y lok tree moifition, IEICE Trns. Funmentls, vol. E85-A, no. 1, pp. 59 0, 00. [11] K. Morishit, A. Tkhshi, n Y. Kjitni, Clokperio minimiztion y ely optimiztion on the semisynhronous iruit, IPSJ SIG Tehnil Report, pp , [1] T. Yo n A. Tkhshi, Clok perio minimiztion of semi-synhronous iruits y gte-level ely insertion, IEICE Trns. Funmentls, vol. E8-A, no. 11, pp , [13] Y. Kohir n A. Tkhshi, Clok perio minimiztion metho of semi-synhronous iruits y ely insertion, IEICE Trns. Funmentls, vol. E88-A, no. 4, pp , 005. [14] Y. Kohir, S. Tni, n A. Tkhshi, Minimiztion of ely insertion in lok perio improvement in generlsynhronous frmework, IEICE Trns. Funmentls, vol. E9-A, no. 4, pp , 009. [15] T. Ysui, K. Kurokw, M. Toyong, n A. Tkhshi, A iruit optimiztion metho y the register pth moifistion in onsiertion of the rnge of fesile lok timing, DA Symposium 00, IPSJ Symposium Series, vol. 00, no. 10, pp. 59 4, 00. [1] Y. Kohir n A. Tkhshi, Gte-level register relotion in generlize synhronous frmework for lok perio minimiztion, IEICE Trns. Funmentls, vol. E90-A, no. 4, pp , 007. [17] Y. Kohir n A. Tkhshi, A fst gte-level register relotion metho for iruit size reution in generlsynhronous frmework, IEIICE Trns. Funmentls, vol. E91-A, no. 10, pp , 008. [18] CPLEX ommere/optimiztion/plex-optimizer/

6 TABLE III Experimentl Results. MZ MN MNC ILP1 ILP T C T S P T C T S P T C T S P T S P Time[s] T S P Time[s] s s s s s s s s s s s s s s5n s s s s s s s s s s s s s s s s s s s s s x x x s s s x x x s x x x s x x x s x x x s x x x s x x x s x x x s x x x s s prolog Ave T C minimum lok perio in -frme T S minimum lok perio in g-frme P power onsumption in gte level x out of memory