Design and Implementation of Reversible Binary Comparator N.SATHISH 1, T.GANDA PRASAD 2

Transcription

1 ISSN Vol.03,Issue.03, March-2014, Pages: Design and Implementation of Reversible Binary Comparator N.SATHISH 1, T.GANDA PRASAD 2 1 PG Scholar, Dept of ECE, Padmasri Dr.B.V.Raju Institute of Technology, Vishnupur, Medak, Andhrapradesh, India. sathish.nallagonda@gmail.com. 2 Asst Prof, Dept of ECE, Padmasri Dr.B.V.Raju Institute of Technology, Vishnupur, Medak, Andhrapradesh, India. gangaprasad.t@bvrit.ac.in. Abstract: This paper proposes the design of digital comparator with two different parallel architectures. Reversible logic has attracted significance attention in recent years, leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose the design and optimization of 32-bit reversible binary comparator. The circuit for MSB and one-bit comparator cell using NOT, PG and CNOT gates are designed. The 32-bit reversible binary comparator is designed using circuit for MSB as first stage to compare MSBs and one-bit comparator cell as second stage and so on to compare lesser significant bit positions. The power consumption and delay are computed. These comparators are first realized in Verilog and simulated with Xilinx ISE 8.2i platform and then compared with the Existing designs. Simulation results show that the first proposed architecture has % less combinational delay (logic + interconnect) and the second proposed architecture is even much faster and has a combinational delay of % less compared to the existing design. Keywords: Binary comparator, Reversible Binary Comparator, Reversible Logic, Garbage Output, Constant Input, parallel architecture, compare look ahead logic, tree comparator, combinational path delay. I. INTRODUCTION A comparator is a circuit that takes two numbers as input in binary form and determines whether one number is less than, greater than or equal to the other number. Comparator circuits are very important and commonly used for computing systems like Analog to Digital and Digital to Analog Convertors, Error Detectors, Microprocessors, Microcontrollers, and communications systems etc. and it is an important data-path element for any general purpose architecture as well as an essential device for applicationspecific and signal processing architectures[1,2]. Comparators are also used in sorting networks which play an important role in areas such as parallel computing, multiaccess memories and multiprocessing [3, 4, 5, 6]. In conventional circuits, the comparison is carrying out irreversibly i.e. once output bits are generated the input bits are lost forever, but this is not in the case of reversible logic circuits. In recent years, reversible logic circuits are used at large level in low power VLSI design. The conventional logic gates like AND, OR, EXOR, NAND etc. are not reversible as they are all multiple inputsingle output gates. Input states are lost because there are less number of outputs than inputs, i.e. output contain less information than input. This loss of information leads to the loss of energy in the form of heat. According to R. Landauer [8], circuit design based on irreversible logic operations produces ktln2 joules of energy, where k is Boltzmann s Constant; T is the absolute temperature (300K). According to C.H. Bennet [9], a circuit designed using reversible logic gates consume zero power and no heat is dissipated. In reversible logic gates there are equal number of inputs and outputs. A reversible gate only moves the states around and no information is lost i.e. no energy is lost and heat dissipation is zero. The recycling of real life entities like bottles, cans, paper etc., were impossible decades back, but they are quite prominent today. The same applies to the computing world also. Today s computers consume huge amount of energy, as millions of bits are manipulated billion times in every second. The irreversible logic devices are used in computers been recognized as energy inefficient for several decades. The reversible computing, which does not compute bits that are no longer needed, that allows their energy to be recovered and recycled for use in later operations. The demand for energy efficient becomes more prominent hence reversible computing will become popular. Before the computer industry reaches the fundamental brick wall of performance and energy constraints of computing devices, reversible computing needs to be fully developed. Comparator forms a fundamental component of processors and digital systems. For processors, in order to achieve high throughput with fast clock rates, it is necessary that such devices have less delay. Consequently, the designing of high speed comparator architecture becomes a relevant and essential research topic. Previously published comparator implementations having serial and parallel architecture can 2014 SEMAR GROUPS TECHNICAL SOCIETY. All rights reserved.

2 N.SATHISH, T.GANDA PRASAD both be found in literature. The serial architecture is suitable for short inputs (i.e. when both the inputs have lesser number of bits). For longer inputs (say, 32 bit, 64 bit inputs), the circuit complexity and the combinational delay increase drastically. As a result, parallel approach is generally preferred for comparators with longer inputs. The comparator designs presented in this paper are based on parallel approach. II. DESIGN OF IRREVERSIBLE FOUR-BIT BINARY COMPARATOR A. Existing Architecture-1 Four-bit magnitude comparator [7] is shown in Fig.1. The design is a parallel architecture. The circuit has three output bits: A>B, A<B, A=B. In many applications, only two output signals A>B, A<B are sufficient. The output bit (A=B) goes high if all the bits of A are equal to the corresponding bits of B. The two output signals A>B and A<B, are determined based on the following two conditions. If MSBs of the two numbers are unequal, i.e when Ai=1, Bi =0 then A>B or Ai=0, Bi =1 for A<B. OR if the pair of bits in the significant bit positions are equal, and LSBs are different i.e. Ai=Bi and A i-1 = 1, Bi-1 =0 then A>B or Ai=Bi and Ai-1=0, Bi-1=1 then A<B. The procedure for binary numbers with more than 2 bits can also be found in the similar way. The figure 1 shows the 4-bit magnitude comparator. Input A=A3A2A1A0 B=B3B2B1B0 1. A= B : A3=B3, A2=B2, A1=B1, A0=B0 xi = AiBi + Ai Bi XOR-Invert = (AiBi +Ai Bi) = (Ai +Bi) (Ai+Bi ) = Ai Ai + Ai Bi + AiBi + BiBi = AiBi + Ai Bi Output: x3x2x1x0 2. A> B Output: A3B 3 + x3a2b 2 + x3x2a1b 1+ x3x2x1a0b 0 3. (A< B) Output: A 3B3 + x3a 2B2 + x3x2a 1B1+ x3x2x1a 0B0 Fig.1. Existing architecture 1 B. Existing Architecture-2 The second architecture proposed in this paper can be called a look-ahead comparator and has a parallel approach. It has two output bits: A>B and A<B. The circuit of the 4- bit design of this comparator is displayed in Fig.2. The first stage of this architecture employs a compare look-ahead logic as shown in Fig.2. This look-ahead section generates compare signals CMPi for each bit position, i (i= 0, 1, 2, 3). The CMPi signal goes high if: The i th bits of A and B are unequal or The MSBs are equal and more significant positions of A and B are unequal. For a given pair of numbers, only one of the compare signals will be high. A high CMPi will activate Gi and Si gates. If Ai =1 and Bi = 0, output of Gi and hence, (A>B) goes high. On the other hand, if Ai =0 and Bi =1, output of

3 Design and Implementation of Reversible Binary Comparator Si and hence, (A<B) goes high. Fig.2. Existing architecture 2 Fig.3. Compare look ahead logic III. PROPOSED ARCHITECTURES A. Universal Gates used in Proposed Architecture-1 In order to implement the below circuit with fewer gates, In order to reduce the area, we can still decrease the number of gates. The logic of A<B can be decided by A>B and A=B. 2-input NOR is used here to realize the function of A<B. The area of 2-input NOR is much less than that of SS2. On the other hand, fewer gates mean fewer powers, so this modification can greatly reduce the power dissipation. Therefore, the logic optimization is completed. Fig.4. Proposed architecture 1 Seeing from the above diagram, we can use 11 gates to implement the 4-Bit comparator beside the inverters. The kind of gates includes XOR, AND, NOR. 4 gates of XOR are the same. 5 gates of AND have different number of inputs, but the principle of layout is the same. So does the NOR gate. B. Reversible logic gates used in proposed architecture-2 Reversible logic circuits are designed using reversible logic gates. Reversible logic gates have equal number of inputs and outputs. Reversible logic gate has distinct output for each distinct input. In reversible logic gates the input states are uniquely determined from the output states. A reversible logic gate is balanced, i.e. the outputs are 1s for exactly half of the inputs. Optimization parameters are very important for designing an optimized reversible logic circuit and determine the complexity and performance of the circuit. The optimization parameters are as follows: Reversible Gates: The number of reversible gates used to realize the function and should be as minimum as possible so as to reduce delay, quantum cost and area. Quantum Cost: This refers to the cost of the circuit in terms of reversible gates used and should be minimum to reduce the circuit cost. Garbage Output: This refers to the no. of outputs which are not used and therefore it should be as small as possible.

4 N.SATHISH, T.GANDA PRASAD Constant Input: This refers to the no. of inputs to be maintained constant at either logic 0 or logic 1 and should be minimum. Delay: The delay is the propagation delay of the critical path where, critical path is the path to the output which has the maximum delay and so it should be minimum. Fan-out: Fan-out is not allowed in reversible logic circuits. The simplest reversible gate is NOT gate and is a 1*1 gate. Controlled NOT (CNOT) gate is an example for a 2*2 gate. There are many 3*3 reversible gates such as Fred kin (F), Toffoli (TG), Peres (PG) and TR gate. C. Circuit for MSB The circuit for MSB is to binary comparator using reversible logic is shown in Figure 8. This circuit consists of three inputs An, Bn and logical low i.e., 0 and the outputs A Equal to B (AEB), A Greater than B (AGB) and A Less than B (ALB). The reversible circuit for MSB is designed using one PG, two CNOT and one NOT gates. The circuit for MSB alone can function as one-bit comparator and has one garbage output, two constant inputs and the quantum cost of six as PG gate costs four and each CNOT gate costs one. This circuit for MSB is connected at the first stage of the serial design of 32-bit reversible binary comparator. In proposed architecture design following reversible logic gates is used: NOT Gate (as an inverter) Feynman Gate / CNOT gate and Peres Gate(PG) NOT Gate: NOT gate is the only conventional logic gate which is also reversible logic gate. It is used as an inverter to invert the applied input. It is a one input-one output reversible logic gate as shown in Fig. 5 and implements the logic function: P = A. Fig.5. NOT Gate Feynman / CNOT Gate: Feynman gate is also known as controlled-not gate shown in Fig.6. It implements the logic functions: P = A and Q = A XOR B. Since the fan-out in the reversible circuit is 1, this gate is often used as a copying gate to duplicate the required output. Fig.6. Feynman / CNOT Gate Peres Gate: The three inputs and three outputs i.e., 3*3 reversible gate having inputs (A, B, C) mapping to outputs (P = A, Q = A XOR B, R = (A.B) XOR C). Since it requires two V+, one V and one CNOT gate, it has the quantum cost of four. Fig.7. Peres Gate Fig.8. The circuit for MSB of the reversible binary comparator The input Bn is connected to the NOT gate to get Bn at the output of the NOT gate and the inputs An, Bn and logical Low are connected to PG gate. The output x is garbage output represented as g1 and output y of the PG gate is (A XOR B) is connected to input of CNOT1 gate, another input to CNOT1 gate is Logical High i.e., 1. The output z of the PG gate is AB and output m of CNOT1 is (A XOR B) are connected to inputs of the CNOT2 gate. The final outputs of the circuit for MSB are given in Equation 1, 2 and 3. AEB = (A B) (1) AGB = AB (2) ALB = A B (3) D. One-bit Reversible Binary Comparator Block A is shown in Figure 9 is used in the one-bit comparator cell, which consists of two NOT, one PG and one CNOT gate. The output i of PG is garbage output and output j of the PG gate is (A B) is connected to NOT gate and then to input of the CNOT gate. The output k of the PG gate is connected to input of CNOT gate which results in C1 i.e., AB and C2 i.e., A B. One-bit reversible binary comparator consists of three PG and four CNOT gates. It has five inputs viz., Pn (AEB), Qn (AGB), Rn (ALB), An-1

5 Design and Implementation of Reversible Binary Comparator and Bn-1 and three outputs Qn-1 i.e., AGB, Pn-1 i.e., AEB and Rn-1 i.e., ALB as shown in the Figure 10. In this PG gates are used to generate the product functions like AB and A B and connecting these to three CNOT gates and one NOT gate to get the final outputs of one-bit comparator. This circuit designed to be fit at lesser significant bit positions in 32-bit binary comparator. This design has a quantum cost of sixteen as three PG gates costs twelve and four CNOT gates costs four, constant inputs of three denoted as logical Low and five garbage outputs represented as g1 to g5. Fig.9. Block diagram of block A Fig.11. Four-bit reversible binary comparator The QC of four-bit reversible binary comparator is given in an Equation: QC = QC of circuit for MSB + (3 * QC of one-bit Comparator cell) (4) QC = x 16 = 54. The number of CIs of four-bit reversible binary comparator is given in an Equation: CIs = CIs of circuit for MSB + (3 * CIs of one-bit Comparator cell) (5) CIs = x 3 = 11. The GOs of four-bit reversible binary comparator is given in an Equation: GOs = GOs of circuit for MSB + (3 * GOs of one- bit comparator cell) (6) GOs = x 5 = 16. IV. MODIFIED COMPARATOR MODULE FOR 32- BIT TREE STRUCTURE A. Design comparator using Irreversible logic gates: The schematic for 32-bit level implementation of the traditional and proposed comparators is shown in Fig.12. The blocks of the first stage compute the comparison result for every 4 bits of the input numbers. The blocks in the second stage take the result of four sets of 4-bit numbers and compute the result for the two 16-bit numbers which are obtained when the four sets of 4-bit numbers are concatenated. This logic is repeated in the third stage where the 2-bit block takes the results of two sets of 16-bit numbers and computes the result for the two 32-bit numbers. Fig.10. One-bit reversible binary comparator E. Four bit Reversible Binary Comparator: Four stages of four-bit reversible binary comparator are shown in Fig.11. First stage is circuit for MSB stage compares the MSB bits of the two numbers. Second stage is one-bit comparator cell compares the result of the first stage and the input bits A2, B2. Third stage is also one-bit comparator cell compares the output of the second stage and the input bits A1, B1. Fourth stage compares the result of third stage and the LSB bits A0, B0 of the two numbers resulting the final output of the four-bit numbers A and B. In the 32-bit level implementation of both the proposed comparators, a modified 2-bit comparator module has been utilized. Since the numbers input to the 2-bit comparator module are the outputs of 4-bit comparators, certain pairs of numbers can never be the input combinations: (10,10), (10,11), (11,10), (11,01), (01,11), (01,01). This is because the (A>B) and (A<B) output bits of the 4- bit comparator module can never be 1 at the same time. As a result, the Boolean expression for the (A>B) output of 2-bit comparator module becomes: (7)

6 N.SATHISH, T.GANDA PRASAD Fig bit tree structure comparator The logic-level circuit diagram of the modified 2-bit comparator module is shown in Fig.13. Fig.13. Modified 2-bit comparator B. Design comparator using Reversible logic gates: Thirty-two-bit reversible binary comparator are shown in Fig.14. First stage is circuit for MSB stage works as onebit comparator compares the MSB bits of the two numbers A32, B32. Second stage is one-bit comparator cell compares the result of the first stage and the input bits A31, B31. Third stage is also one-bit comparator cell compares the output of the second stage and the input bits A30, B30. Fourth stage compares the result of third stage and the input bits A29, B29 of the two numbers and so on. The final stage compares the output of the thirty-first stage and the LSB bits A1, B1 resulting the final output of the thirty-two-bit numbers A and B. The QC of Thirty-two-bit reversible binary comparator is given in an Equation: QC = QC of circuit for MSB + (31 * QC of one-bit Comparator cell) (7) QC = x 16 = 502. The number of CIs of Thirty-two-bit reversible binary comparator is given in an Equation: CIs = CIs of circuit for MSB + (31 * CIs of one-bit Comparator cell) (8) CIs = x 3 = 95. The GOs of Thirty-two-bit reversible binary comparator is given in an Equation: GOs = GOs of circuit for MSB + (31 * GOs of one-bit comparator cell) (9) GOs = x 5 = 156. V. SIMULATION AND RESULTS All the simulations of the 32-bit level implementation of the Existing and proposed comparators have been carried out using Verilog HDL programming in Xilinx ISE 8.2i platform. Adequate testing of each design was done to verify correct operation. The results obtained after the simulation of the traditional and the proposed comparators are summarized in Table 1. TABLE1: Delay Comparison of Comparator Designs for 32-bit operation Fig.14. Thirty-two-bit reversible binary comparator.

7 Design and Implementation of Reversible Binary Comparator Referring to the above table, it can be seen that there is a decrease in routing delay as well as logic delay of both the proposed comparators in comparison to the Existing comparator. This leads to an overall reduction in their combinational path delay. Fig.18. Simulation result for proposed 2 architecture Fig.15. RTL schematic for 4-bit Comparator using universal Gates. VI. CONCLUSION The proposed comparators have been discussed, simulated and compared with the Existing comparators. Simulation results show % decrease in path delay in case of the proposed architecture-i and 21.83% decrease in path delay in case of proposed architecture-ii over Existing architecture. VII. REFERENCES [1]J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, [2]J. Eyre and J. Bier, DSP processors hit the mainstream, IEEE Computer, pp , [3] Shun-Wen Cheng, Arbitrary Long Digit Sorter HWISW Co-Design, in Proc. Asia and South Pacific Design Automation Conj, ASPDAC 03, pp , Jan Fig.16. Simulation result for proposed 1 architecture [4] D. E. Knuth, Sorting and Searching. Reading: Addison- Wesley, [5] D. Norris, Comparator circuit, U.S. Patent 5,534,844, April 3, [6] Shun-Wen Cheng, A high-speed magnitude comparator with small transistor count in Proceedings of the th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp , 2003 [7] M. Morris Mano, Digital Logic and Computer Design. Fig.17. RTL schematic for 4-bit Comparator using Reversible logic Gates. [8] R Landauer, Irreversibility and Heat Generation in the Computational Process, IBM Journal of Research and Development, vol. 5, no. 3, pp , July 1961.

8 N.SATHISH, T.GANDA PRASAD [9] C H Bennett, Logical Reversibility of Computation, IBM Journal of Research and Development, vol. 17, no. 6, pp , November [10] Kerntopf P, M A Perkowski and M H A Khan, On Universality of General Reversible Multiple Valued Logic Gates, Proceedings of the Thirty Fourth IEEE International Symposium on Multiple valued Logic, pp , [11] H Thapliyal, N Ranganathan and Ryan Ferreira, Design of a Comparator Tree based on Reversible logic, Proceedings of Tenth IEEE International Conference on Nanotechnology Joint Symposium with Nano, pp , August [12] W. David, Mahesh Nalasani, Reversible Logic, IEEE Potentials 2005 pp Information Processing Letters, Vol. 70, 199, pp , 2005.