Issue = Select + Wakeup. Out-of-order Pipeline. Issue. Issue = Select + Wakeup. OOO execution (2-wide) OOO execution (2-wide)

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1 Out-of-order Pipeline Buffer of instructions Issue = Select + Wakeup Select N oldest, read instructions N=, xor N=, xor and sub Note: ma have execution resource constraints: i.e., load/store/fp Fetch Decode Rename Dispatch Issue Reg-read Execute Writeback Commit Insn Inp R Inp R Dst Age xor p p 0 Read! add n p4 In-order front end Out-of-order execution sub p5 p addi n Read! 40 Issue = Select + Wakeup Wakeup dependent instructions CAM search for Dst in inputs Set read Also update read-bit table for future instructions Insn Inp R Inp R Dst Age xor p p 0 add p4 sub p5 p addi Read bits p p p3 p4 p5 n n Select/Wakeup one ccle Dependents go back to back Next ccle: add/addi are read: Issue Insn Inp R Inp R Dst Age add p4 addi OOO execution (-wide) OOO execution (-wide) xor RDY add sub RDY addi p 7 p xor add RDY sub addi RDY xor p, p sub p5, p p 7 p

2 OOO execution (-wide) OOO execution (-wide) xor add sub addi add, p4 addi, p 7 p xor 7, 3 sub 6 3 xor add sub addi p 7 p add _, 9 addi _, OOO execution (-wide) OOO execution (-wide) p 7 p 7 xor add sub addi p xor add sub addi p Note similarit to in-order OOO execution (-wide) p 7 p Multi-ccle operations Multi-ccle ops (load, fp, multipl, etc.) Wakeup deferred a few ccles Structural hazard? Cache misses? Speculative wake-up (assume hit) Cancel exec of dependents Re-issue later Details: complicated, not important 54 55

3 Re-order Buffer (ROB) All instructions in order Two purposes Misprediction recover In-order commit Maintain appearance of in-order execution Freeing of phsical registers RENAMING REVISITED Renaming revisited Overwritten register Freed at commit Restore in map table on recover Branch mis-prediction recover Also must be read at rename Original insns xor r,r r3 addi r3, r r p r3 p3 p xor r,r r3 xor p, p addi r3, r xor r,r r3 xor p, p addi r3, r r p r3 p3 p0 r p r3 p0 60 6

4 xor r,r r3 xor p, p add, p4 addi r3, r xor r,r r3 xor p, p addi r3, r r p r3 p0 r p r3 r4 p xor r,r r3 xor p, p sub p5, p addi r3, r xor r,r r3 xor p, p sub p5, p addi r3, r r p r3 r4 p0 r p r3 r4 p xor r,r r3 xor p, p addi r3, r sub p5, p addi, [p] xor r,r r3 xor p, p addi r3, r sub p5, p addi, [p] r p r3 r4 p0 r r3 r4 p

5 ROB ROB entr holds all info for recover/commit Logical register names Phsical register names Instruction tpes Dispatch: insert at tail Full? Stall Commit: remove from head Not completed? Stall Recover Completel remove wrong path instructions Flush from IQ Remove from ROB Restore map table to before misprediction Free destination registers Recover example bnz r loop bnz p, loop xor r, r r3 xor p, p add r3, r4 r4 sub r5, r r3 addi r3, r sub p5, p addi, [p] Recover example bnz r loop bnz p, loop xor r, r r3 xor p, p add r3, r4 r4 sub r5, r r3 addi r3, r sub p5, p addi, [p] r r3 r4 p0 r p r3 r4 p Recover example bnz r loop bnz p, loop xor r, r r3 xor p, p add r3, r4 r4 sub r5, r r3 sub p5, p Recover example bnz r loop bnz p, loop xor r, r r3 xor p, p add r3, r4 r4 r p r3 r4 p0 r p r3 p0 7 73

6 bnz r loop xor r, r r3 Recover example bnz p, loop xor p, p Recover example bnz r loop bnz p, loop r p r3 p3 p0 r p r3 p3 p What about stores Stores: Write D$, not registers Can we rename memor? Recover in the cache? No (at least not easil) Cache writes unrecoverable Stores: onl when certain Commit Commit xor r, r r3 xor p, p add r3, r4 r4 sub r5, r r3 addi r3, r sub p5, p addi, [p] At commit: instruction becomes architected state In order Onl when instructions are finished Free overwritten register (wh?) xor r,r r3 addi r3, r Freeing over-written register xor p, p sub p5, p addi, [p] Commit Example xor r,r r3 xor p, p addi r3, r sub p5, p addi, [p] Before xor: r3 p3 After xor: r3 Insns older than xor reads p3 Insns ounger than xor read (until next r3-writing instruction) At commit of xor, no older instructions exist No one else needs p3 free it! r r3 r4 p

7 Commit Example xor r,r r3 addi r3, r xor p, p sub p5, p addi, [p] Commit Example addi r3, r sub p5, p addi, [p] r r r3 r4 r5 p p5 p0 p3 r r r3 r4 r5 p p5 p0 p3 p Commit Example Commit Example addi r3, r sub p5, p addi, [p] addi r3, r addi, [p] r r r3 r4 r5 p p5 p0 p3 p4 r r r3 r4 r5 p p5 p0 p3 p4 p 8 83 Standard stle: large and cumbersome Change laout slightl Columns = stages (dispatch, issue, etc.) Rows = instructions Content of boxes = ccles For our purposes: issue/exec = ccle Ignore preg read latenc, etc. Load-use, mul, div, and FP longer ld [p] p add p, p3 p4 ld [] Buffer of instructions Fetch Decode Rename Dispatch Issue Reg-read Execute Writeback Commit 84 85

8 ld [p] p add p, p3 p4 ld [] ld [p] p add p, p3 p4 ld [] -wide Infinite ROB, IQ, Pregs Loads: 3 ccles Ccle : Dispatch xor and ld ld [p] p 5 ld [p] p 5 add p, p3 p4 add p, p3 p4 ld [] ld [] 3 6 Ccle : Dispatch xor and ld st Ld issues -- also note WB ccle while ou do this (Note: don t issue if WB ports full) Ccle 3: add and xor are not read nd load is issue it ld [p] p 5 ld [p] p 5 6 add p, p3 p4 5 6 add p, p3 p ld [] 3 6 ld [] 3 6 Ccle 4: nothing Ccle 5: add can issue Ccle 6: st load can commit (oldest instruction & finished) xor can issue 90 9

9 ld [p] p 5 6 ld [p] p 5 6 add p, p3 p add p, p3 p ld [] 3 6 ld [] Ccle 7: add can commit (oldest instruction & finished) Ccle 8: xor and ld can commit (-wide: can do both at once) 9 93 ld [p] p add p, p3 p4 ld [] Buffer of instructions HANDLING MEMORY OPS Fetch Decode Rename Dispatch Issue Reg-read Execute Writeback Commit Dnamicall Scheduling Memor Ops Compilers must schedule memor ops conservativel Options for hardware: Hold loads until all prior stores execute (conservative) Execute loads as soon as possible, detect violations (aggressive) When a store executes, it checks if an later loads executed too earl (to same address). If so, flush pipeline Learn violations over time, selectivel reorder (predictive) Before Wrong(?) ld r,4(sp) ld r,4(sp) ld r3,8(sp) ld r3,8(sp) add r3,r,r //stall ld r5,0(r8) //does r8sp? st r,0(sp) add r3,r,r ld r5,0(r8) ld r6,4(r8) //does r8+4sp? ld r6,4(r8) st r,0(sp) sub r5,r6,r4 //stall sub r5,r6,r4 st r4,8(r8) st r4,8(r8) 96 Loads and Stores fdiv p,p p3 st p4 [p5] st p3 ld [] 5 3 Ccle 3: Can ld[] execute? (wh or wh not?) 97

10 Loads and Stores Loads and Stores fdiv p,p p3 5 fdiv p,p p3 5 st p4 [p5] 3 st p4 [p5] 3 st p3 st p3 ld [] ld [] Aliasing (again) p5?? Suppose p5 and!= Can ld[] execute? (wh or wh not?) Memor Forwarding Stores write cache at commit Commit is in-order, delaed b all instructions Allows stores to be undone on branch mis-predictions, etc. Loads read cache Earl execution of loads is critical Forwarding Allow store load communication before store commit Conceptuall like reg. bpassing, but different implementation Wh? Addresses unknown until execute Forwarding: Store Queue Store Queue Holds all in-flight stores CAM: searchable b address Age logic: determine oungest matching store older than load Store execution Write Store Queue Address + Data Load execution Search SQ Match? Forward Read D$ address address load position Store Queue (SQ) age Data cache data in value data out head tail 00 0

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