SUBMITTED TO A JOURNAL 1. Decentralized Equalization with Feedforward Architectures for Massive MU-MIMO

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1 SUBMITTED TO A JOURNAL 1 Decentralized Equalization with Feedforward Architecture for Maive MU-MIMO Charle Jeon, Kaipeng Li, Joeph R. Cavallaro, and Chritoph Studer arxiv: v1 [c.it] 13 Aug 2018 Abtract Linear data-detection algorithm that build on zero forcing ZF) or linear minimum mean-quare error L-MMSE) equalization achieve near-optimal pectral efficiency in maive multi-uer multiple-input multiple-output MU-MIMO) ytem. Such algorithm, however, typically rely on centralized proceing at the bae-tation BS) which reult in i) exceive interconnect and chip input/output I/O) data rate and ii) high computational complexity. Decentralized baeband proceing DBP) partition the BS antenna array into independent cluter that are aociated with eparate radio-frequency circuitry and computing fabric in order to overcome the limitation of centralized proceing. In thi paper, we invetigate decentralized equalization with feedforward architecture that minimize the latency bottleneck of exiting DBP olution. We propoe two ditinct architecture with different interconnect and I/O bandwidth requirement that fue the local equalization reult of each cluter in a feedforward network. For both architecture, we conider maximum ratio combining, ZF, L-MMSE, and a nonlinear equalization algorithm that relie on approximate meage paing, and we analyze the aociated pot-equalization ignal-to-noie-and-interferenceratio SINR). We provide reference implementation reult on a multi graphic proceing unit GPU) ytem which demontrate that decentralized equalization with feedforward architecture enable throughput in the Gb/ regime and incur no or only a mall performance lo compared to centralized olution. Index Term Data detection, decentralized baeband proceing, linear and nonlinear equalization, general-purpoe computing on graphic proceing unit GPGPU), maive MU-MIMO. I. INTRODUCTION MASSIVE multi-uer MU) multiple-input multiple-output MIMO) i widely believed to be a key technology for next-generation wirele ytem [2] [4]. By equipping the infratructure bae-tation BS) with hundred or thouand of active antenna element and erving ten or hundred of uer equipment UE) imultaneouly and in the ame frequency band, maive MU-MIMO promie order-ofmagnitude improvement in pectral efficiency and energy efficiency compared to traditional, mall-cale MIMO [5], [6]. However, the large number of antenna at the BS caue ignificant challenge when implementing thi technology. One of the mot prominent challenge i the exceively high amount C. Jeon and C. Studer are with the School of Electrical and Computer Engineering at Cornell Univerity, Ithaca, NY; jeon@cl.cornell.edu, tuder@cornell.edu; webite: vip.ece.cornell.edu K. Li and J. R. Cavallaro are with the Department of Electrical and Computer Engineering at Rice Univerity, Houton, TX; kl33@rice.edu, cavallar@rice.edu. A imulator to reproduce our main reult will be made available on GitHub upon poible acceptance of thi paper. Part of the theoretical performance reult in thi paper have been preented at the 2017 IEEE International Sympoium on Information Theory [1]. of fronthaul data that mut be tranferred from the radiofrequency ) antenna unit at the BS antenna array to the baeband proceing unit BBU) [7] [10]. For example, the fronthaul data rate from chain to the BBU) exceed 200 Gbit/ for a maive MU-MIMO ytem with 128 BS antenna, each uing two 10 bit analog-to-digital converter for in-phae and quadrature component) operating at 80 MS/ ampling rate. Such high data rate not only exceed the bandwidth of exiting high-peed interconnect tandard, uch a the common public radio interface CPRI) [11], but will alo approach the limit of exiting chip input/output I/O) interface in term of bandwidth and power diipation [12]. Furthermore, traditional data-detection algorithm that achieve near-optimal pectral efficiency in the MU-MIMO uplink [5], uch a zero-forcing ZF) and linear minimum mean-quare error L- MMSE)-baed equalization, rely on centralized proceing in a ingle computing fabric, which reult in exceively high complexity for large antenna array [8], [13]. A. Decentralized Baeband Proceing In order to mitigate the bandwidth and computing bottleneck of centralized maive MU-MIMO architecture, exiting tetbed either ditribute the mot critical baeband proceing tak in the frequency domain or ue maximum ratio combining MRC). Concretely, the tetbed decribed in [14] [17] parallelize the key baeband proceing tak acro the ubcarrier of orthogonal frequency-diviion multiplexing OFDM)-baed ytem. While thi approach enable high parallelim, it require that each frequency cluter obtain data from all BS antenna, which alone doe not enable one to cale uch ytem to thouand of antenna element [8]. In contrat to frequency parallelization, MRC enable antenna parallelization that divide array into independent cluter [2], [18]; thi approach ignificantly reduce the interconnect bandwidth between the chain and the BBU. MRC, however, uffer from low pectral efficiency for realitic antenna configuration and high-rate modulation and coding cheme [5]. Conequently, realizing maive MU-MIMO in practice require olution that reduce the interconnect and chip I/O bandwidth a well a the baeband proceing complexity per computing fabric, without acrificing pectral efficiency. Decentralized baeband proceing DBP) ha been propoed in [8] to alleviate the fronthaul and I/O bandwidth bottleneck, and enable parallel baeband proceing acro BS antenna on multiple computing fabric, uch a application-pecific integrated circuit ASIC), field-programmable gate array FPGA), or graphic proceing unit GPU) [19], [20],

2 2 SUBMITTED TO A JOURNAL while achieving high pectral efficiency. The idea of DBP i to partition the BS antenna array into C independent cluter, each aociated with local computing fabric that carry out the neceary and baeband proceing tak in a decentralized and parallel fahion. The algorithm propoed in [8] perform linear equalization and precoding in an iterative manner by exchanging conenu information among the cluter. However, implementation reult on a GPU cluter revealed that the tranfer latency of uch conenu-haring method are limiting the achievable throughput. To avoid thi drawback, reference [1], [7], [12], [21] recently propoed feedforward architecture that minimize the tranfer latency. B. Contribution We propoe two ditinct feedforward architecture for partially decentralized PD) and fully decentralized FD) equalization, which mitigate the interconnect, I/O, latency, and computation bottleneck. For both of thee architecture, we invetigate the efficacy of MRC, ZF, L-MMSE, and a nonlinear equalization method that build upon the large-mimo approximate meage paing LAMA) algorithm [22]. Our main contribution can be ummarized a follow: We develop a framework that enable a precie analyi of the pot-equalization ignal-to-noie-and-interference-ratio SINR) of decentralized equalization with feedforward architecture in the large-ytem limit. We how that the PD feedforward architecture achieve the ame SINR performance a centralized olution for equalization with MRC, ZF, L-MMSE, and PD-LAMA. We how that the FD feedforward architecture i able to provide near-optimal SINR performance, but further reduce the interconnect and I/O bandwidth. We analyze optimal antenna partitioning trategie that maximize the SINR for the FD architecture. We conduct error-rate imulation for a realitic 3GPP long-term evolution LTE)-like maive MU-MIMO ytem that upport our theoretical finding. We provide reference throughput and latency reult for linear and nonlinear equalization in centralized, PD, and FD architecture on a multi-gpu ytem. Our reult demontrate that feedforward equalization enable throughput in the Gb/ regime for maive MU-MIMO ytem with hundred of antenna element, and incur no or only a mall lo in pot-equalization SINR and error-rate performance compared to that of centralized olution. C. Relevant Prior Art Decentralized baeband proceing DBP) for maive MI- MIMO ytem ha been propoed in [8] together with conenu-haring equalization and precoding algorithm. Ditributed proceing acro antenna element i alo a critical component of coordinated multipoint CoMP) [23] and cloud radio acce network CRAN) [24] for multi-cell tranmiion. While all thee architecture and algorithm are able to reduce the raw baeband data rate and mitigate the computation bottleneck, their performance ha not been analyzed and the achievable throughput uffer from high interconnect latency caued by iterative exchange of conenu information. To avoid the conenu haring among cluter, we focu on decentralized feedforward architecture that minimize the tranfer latency and enable a theoretical performance analyi. Feedforward architecture for decentralized maive MU- MIMO equalization have been propoed in [1], [7], [12], [21]. The preent paper extend our theoretical reult from [1] and, in contrat to [7], [12], [21], provide two ditinct architecture and a correponding SINR analyi for a range of linear and nonlinear equalization algorithm. In addition, we provide reference implementation reult on a GPU cluter to ae the throughput and latency of our architecture and algorithm. The pot-equalization SINR performance of centralized linear equalization algorithm, uch a MRC, ZF, and L-MMSE, ha been analyzed in [25] [28] in the large-ytem limit. We will invetigate the SINR performance of thee algorithm for the two propoed decentralized feedforward architecture, and alo invetigate the efficacy of nonlinear equalization for decentralized maive MU-MIMO architecture. Nonlinear equalization for maive MU-MIMO ytem via approximate meage paing AMP) ha been tudied in [22], [29], [30]. A ditributed verion of AMP ha been propoed in [31] for compreive ening application [32], [33]. The key difference of our nonlinear equalization algorithm to thee reult are a follow: i) We conider decentralized feedforward architecture; ii) the method in [22], [29], [30] are centralized; iii) the ditributed AMP-baed method in [31] require iterative conenu haring; iv) we analyze the pot-equalization SINR and error-rate performance in maive MU-MIMO ytem. D. Notation Lowercae and uppercae boldface letter deignate vector and matrice, repectively; uppercae calligraphic letter denote et. The tranpoe and Hermitian of the matrix A are repreented by A T and A H, repectively. The M N all-zero matrix i 0 M N and the M-dimenional identity matrix i I N. The kth entry of a vector a i a k. We define x = 1 N N k=1 x k. The circularly-ymmetric multivariate complex-valued Gauian probability denity function pdf) with covariance K i denoted by CN 0, K). E X [ ] and Var X [ ] repreent the mean and variance with repect to the random variable X, repectively. E. Paper Outline The ret of the paper i organized a follow. Section II introduce the ytem model and the two feedforward architecture. Section III and Section IV invetigate equalization algorithm for the PD and FD architecture, repectively. Section V provide theoretical and imulative reult for the propoed method. Section VI detail the multi-gpu implementation and provide throughput and latency reult. Section VII conclude the paper. All derivation and proof are relegated to the appendice. II. DECENTRALIZED EQUALIZATION ARCHITECTURES We tart by introducing the conidered maive MU-MIMO ytem model and the baic of equalization-baed data

3 C. JEON ET AL. 3 CHEST CHEST preproceing + equalization equalization preproceing equalization CHEST CHEST a) Partially decentralized PD) equalization architecture. b) Fully decentralized FD) equalization architecture. Fig. 1. Partially decentralized PD) and fully decentralized FD) feedforward equalization architecture for the maive MU-MIMO uplink. The antenna array i divided in C cluter, each aociated with local radio-frequency ) proceing and channel etimation CHEST). a) PD perform decentralized CHEST and preproceing; equalization i performed in a centralized fahion and operate on a low-dimenional data dimenion i the number of UE). b) FD perform CHEST, preproceing, and equalization in a decentralized manner; the final equalization reult i formed by a weighted average of local etimate. The operator in a) denote matrix/vector-addition and in b) denote a weighted vector addition; ee Eq. 19 in Section IV for the detail. detection. We then dicu the two feedforward equalization architecture for DBP depicted in Fig. 1, and detail the SINR analyi framework that we will ue throughout the paper. A. Uplink Sytem Model and Equalization We conider a narrowband maive MU-MIMO uplink ytem in which U ingle-antenna UE tranmit data to a BS with B antenna element. To model thi cenario, we ue the tandard input-output relation [2] y = H 0 + n. 1) Here, y C B i the receive vector at the BS, H C B U repreent the MIMO ytem matrix, which we aume i perfectly known at the BS, 0 O U contain the tranmit ymbol for each UE, O i the contellation et e.g., QPSK or 16-QAM), and n C B i i.i.d. circularly ymmetric complex Gauian noie with variance N 0 per complex entry. We aume an i.i.d. prior p 0 ) = U u=1 p 0u) for the tranmit vector and the following ditribution for each tranmit ymbol: p 0u ) = 1 O δ 0u a), 2) a O where O i the cardinality of the contellation O and δ ) i the Dirac delta function. In what follow, we aume zeromean contellation and define the average energy per tranmit ymbol a E = E [ 0u 2], u = 1,, U. Equalization i concerned with forming an etimate z of the tranmit ignal vector 0 along with reliability etimate for each entry in z. Thee two quantitie are then ued to compute hard-output etimate for the tranmit ymbol or bit-wie oft information in the form of log-likelihood ratio [34], [35]. Conider a general centralized equalizer {z, σ 2 } = Ey, H) that take the received vector y and the MIMO channel matrix H in order to compute i) an etimate z for the true tranmit vector 0 and ii) the aociated error variance vector σ 2. The error variance vector characterize the pot-equalization reidual interference and noie variance on each entry of the etimate z. Mathematically, thi quantity correpond to the variance of each entry in the reidual interference and noie vector defined a e = z 0, i.e., σ 2 = E [ e 2] where 2 operate element-wie on vector. The literature decribe a range of linear and nonlinear equalization algorithm for mall-cale and maive MU-MIMO data detection [13], [22], [36], [37]. Linear method, uch a MRC, ZF, and L-MMSE are among the mot common algorithm, mainly due to their implicity and low computational complexity [13]. Neverthele, nonlinear equalizer, uch a the LAMA algorithm put forward in [22], have been hown to often ignificantly) outperform linear equalizer at the cot of higher computational complexity [22], [30], [38]. B. Baic of Decentralized Equalization A in [8], we partition the B BS antenna element into C {1, 2,, B} independent antenna cluter. The cth antenna cluter i aociated with B c = w c B BS antenna o that w c [0, 1] and C w c = 1. Each cluter contain local component and only require acce to local channel tate information CSI) acquired in a local channel etimation CHEST) unit. Without lo of generality, we partition the receive vector y = [y1, T, yc T ]T, the channel matrix H = [H T 1,, H T C ]T, and the noie vector n = [n T 1,, n T C ]T in 1). For thi antenna partitioning cheme, the input-output relation correponding to the local receive vector y c aociated with the cth cluter can be written a y c = H c 0 + n c, c = 1,, C, 3) with y c C Bc, H c C Bc U, and n c C Bc. The following ubection decribe two decentralized equalization architecture that compute etimate for the tranmit vector 0 by performing local computation in each antenna cluter uing only information of the local receive vector y c and channel matrix H c followed by fuion of the reult from all cluter. C. Partially Decentralized PD) Equalization Architecture The partially decentralized PD) equalization architecture i illutrated in Fig. 1a). Firt, each cluter c = 1,, C independently and in parallel) preprocee the local receive

4 4 SUBMITTED TO A JOURNAL vector y c and channel matrix H c by computing the U- dimenional local MRC vector yc MRC = H H c y c and the U U local Gram matrix G c = H H c H c. Second, a feedforward adder tree, indicated with the ymbol in Fig. 1a), i ued to compute the complete MRC vector and Gram matrix a follow: y MRC = yc MRC and G = G c. 4) Third, we perform linear or nonlinear equalization in a centralized unit that compute the etimate z C U and the pot-equalization error variance vector σ 2 C U. The tuple {z, σ 2 } i then ued to compute hard- or oft-output etimate. In Section III, we will detail MRC, ZF, L-MMSE equalization, and a new LAMA-baed equalization algorithm [22] for the PD architecture, all of which directly operate on the U-dimenional fued MRC vector y MRC and Gram matrix G. Since the MRC vector i a ufficient tatitic for the tranmit ignal 0 [34], we will how that the PD equalization doe not incur a SINR performance lo compared to centralized MRC, ZF, L-MMSE, and LAMA equalizer. Remark 1. For the PD architecture, the local MRC vector yc MRC, c = 1,, C, have to be ummed and tranmitted to the centralized equalization unit at ymbol rate; in contrat, the local Gram matrice G c, c = 1,, C, only have to be ummed and tranmitted when the MIMO channel change. D. Fully Decentralized FD) Equalization Architecture The PD architecture require a ummation of both the local MRC vector and the local Gram matrice, which involve potentially large amount of data to be tranmitted to the central equalization unit, epecially in channel with hort coherence time. The fully decentralized FD) equalization architecture illutrated in Fig. 1b) avoid the tranmiion of the local Gram matrice altogether at the cot of a typically mall) performance lo. Firt, each cluter c = 1,, C independently and in parallel) perform CHEST, preproceing, and equalization, i.e., directly form a local etimate z c C U and local pot-equalization error variance vector σc 2 C U. Second, a feedforward fuion tree, indicated with the ymbol in Fig. 1b), optimally combine the local etimate z c uing information from the error variance vector σc 2 in order to generate the final output tuple {z, σ 2 }. In Section IV, we will detail the optimal fuion rule a well a MRC, ZF, L-MMSE, and LAMA-baed equalization for the FD architecture. We will alo provide an SINR performance analyi in the large-ytem limit. Remark 2. For the FD architecture, the local etimate z c, c = 1,, C, and aociated error variance vector σ 2 c, c = 1,, C, have to be fued and tranmitted at ymbol rate. In contrat to the PD architecture, no local Gram matrice mut be ummed and tranmitted, which ignificantly reduce the interconnect bandwidth overhead of the FD architecture. E. Signal-to-Interference-and-Noie-Ratio SINR) Analyi To analyze the performance of linear and nonlinear equalization algorithm for the PD and FD architecture, we will focu on the large-ytem limit and Rayleigh-fading channel. Hence, we will make frequent ue of the following two definition. Definition 1 Large-ytem limit). The large-ytem limit i defined by fixing the ytem ratio β = U/B and U. Definition 2 Rayleigh fading). A MIMO channel i Rayleigh fading if the channel matrix H ha i.i.d. circularly ymmetric complex Gauian entrie with variance 1/B per entry. By conidering the large-ytem limit and Rayleigh-fading channel, Te and Hanly have hown in [26] that linear equalizer, uch a MRC, ZF, and L-MMSE, decouple MIMO ytem into parallel and independent additive white Gauian noie AWGN) channel. Thi mean that the etimate z of uch linear equalizer can be modeled on a per-ue bai in a tatitically equivalent manner a follow: z u = 0u + e u, u = 1,, U, 5) where e u C repreent reidual interference and noie. Furthermore, the quantity e u turn out to be i) tatitically independent of 0u and ii) circularly ymmetric complex Gauian with decoupled noie variance σ 2, which doe not depend on the UE index u. Thi reult alo implie that all entrie of the error variance vector σ 2 correpond to σ 2. In Section III and Section IV for the PD and FD architecture, repectively, we will build upon thi aymptotic analyi framework in order to theoretically characterize the per-ue pot-equalization SINR of the decoupled ytem 5): inr E σ 2. 6) Numerical reult that validate our aymptotic analyi in finitedimenional ytem will be preented in Section V. III. PARTIALLY DECENTRALIZED PD) EQUALIZATION We tart by reviewing linear equalization algorithm for the PD architecture depicted in Fig. 1a), and adapt the wellknown Te-Hanly equation [26] to analyze the aociated potequalization SINR performance in the large-ytem limit. We then preent a new, nonlinear equalization algorithm that build upon LAMA propoed in [22], and we develop a correponding SINR performance analyi for the PD architecture. A. Linear Equalization Algorithm for the PD Architecture Since the MRC output y MRC in 4) i a ufficient tatitic for the tranmit ignal vector 0, a variety of optimal and uboptimal equalization-baed data detection algorithm can be derived from thi quantity [34]. For MRC-baed equalization in the PD architecture, we ue 4) to form the etimate z MRC = diagg) 1 y MRC, where the diagonal matrix diagg) 1 i computed in the centralized equalization unit; ee Fig. 1a). The MRC etimate z MRC can then be ued to perform either hard- or oft-output data detection. For oft-output data detection, one require the error variance vector given by σ 2 MRC = diag diagg) 1 GdiagG) H N 0 + diagg) 1 G I U ) diagg) 1 G I U ) HE )

5 C. JEON ET AL. 5 that contain the pot-equalization SINR for each entry of z MRC. Note that MRC-baed equalization wa hown to be optimal i) for a fixed number of UE and infinitely many BS antenna [2], which i equivalent to β 0 in the large-ytem limit, or ii) in the low-snr regime [26]. The etimate of the ZF equalizer for the PD architecture i given by z ZF = G 1 y MRC, where the matrix G 1 i computed in the centralized equalization unit. The aociated error variance vector i given by σ 2 ZF = diagg 1 )N 0. For L-MMSE equalization, we have z L-MMSE = G + ρi U ) 1 y MRC. where the matrix G + ρi U ) 1 i computed in the centralized equalization unit. The L-MMSE regularization parameter i et to ρ = N 0 /E for complex-valued contellation e.g., QPSK or 16-QAM). The aociated error variance vector i given by σ 2 L-MMSE = diag G + ρi U ) 1 GG + ρi U ) H N 0 + G + ρi U ) 1 G I U ) G + ρiu ) 1 G I U ) HE ). We reiterate that the MRC, ZF, and L-MMSE equalizer for the PD architecture deliver exactly the ame etimate a their centralized counterpart the only difference i the way the involved quantitie are computed. A hown in [26] and outlined in Section II-E, centralized MRC, ZF, and L-MMSE equalizer decouple MIMO ytem in the large-ytem limit and for Rayleigh fading channel; thi implie that the entrie of the error variance vector σmrc 2, σzf 2, and σ2 L-MMSE converge to the decoupled noie variance σ2 of the MRC, ZF, and L-MMSE equalizer, repectively. Since linear equalizer in the PD architecture yield exactly the ame etimate a in a centralized architecture, we can directly characterize the aociated decoupled noie variance σpd 2 in the PD architecture uing the following reult. Theorem 1 [26, Thm. 3.1]). Fix the ytem ratio β = U/B, and aume the large-ytem limit and Rayleigh fading channel. Then, the decoupled noie variance σ 2 PD for MRC, ZF, and L-MMSE equalization in a centralized or PD architecture, i the olution to the following fixed-point equation σ 2 PD = N 0 + βψσ 2 PD), 7) where the MSE function Ψσ 2 ) i given by Ψσ 2 ) = E, Ψσ 2 ) = σ 2, Ψσ 2 ) = E E + σ 2 σ2, for MRC, ZF, and L-MMSE equalization, repectively. MRC) ZF) L-MMSE) We note that the expreion for the ZF equalizer only hold for β < 1, wherea the expreion for MRC and L-MMSE hold for general ytem ratio β. 1 From Theorem 1, we obtain 1 The aymptotic SINR performance of ZF equalization via the Moore- Penroe peudo invere when β 1 wa analyzed in [39]. cloed-form expreion for the pot-equalization inr in 6) for MRC, ZF, and L-MMSE equalization in the PD architecture. Corollary 2. Aume that the condition of Theorem 1 hold. Then, the pot-equalization inr for MRC, ZF, and L-MMSE equalization in the PD architecture are given by inr MRC PD = E /N βe /N 0, MRC) inr ZF PD = E 1 β), for β < 1, N 0 inr L-MMSE PD = 1 1 E ) 2 1 β) + 4 E 2 N 0 N 0 ZF) 1 E ) ) 1 β). L-MMSE) N 0 We note that in the maive MU-MIMO regime, which correpond to β 0, all pot-equalization SINR expreion converge to E /N 0, which confirm the well-known fact that MRC i optimal in thi cenario [2]. It can alo be hown that inr L-MMSE PD bound inr MRC PD and inr ZF PD from above for all ytem ratio and in all SNR regime. Hence, L-MMSE equalization i often the preferred choice in realitic maive MU-MIMO ytem [5], [13]. We reiterate that the SINR expreion lited in Corollary 2 are alo valid for centralized architecture. B. LAMA for the PD Architecture The LAMA algorithm developed in [22] i a nonlinear equalizer i able to achieve individually-optimal performance in the large-ytem limit given certain condition on the antenna ratio β and the noie variance N 0 are atified. LAMA operate directly on the input-output relation in 1) and i, hence, deigned for centralized proceing. We now develop a novel variant of LAMA that directly operate on the complete MRC output y MRC and the Gram matrix G in 4) to enable it ue in the PD architecture. Since the antenna configuration in maive MU-MIMO ytem typically atifie U B, the LAMA- PD algorithm operate on a lower dimenion which reduce complexity while delivering exactly the ame etimate a the original LAMA algorithm. We note that LAMA wa derived in the large-ytem limit and for Rayleigh fading channel [40], but thee aumption are not required in practice. We next ummarize the LAMA-PD algorithm; the derivation can be found in Appendix A-A. Algorithm 1 LAMA-PD). Initialize l = E S [S] for l = 1,, U, φ 1) = Var S [S], and v 1) = 0 B 0. Then, for every iteration t = 1, 2,, T max, compute the following tep: z t = y MRC + I G) t + v t 8) t+1 = Fz t, N 0 + βφ t ) φ t+1 = Gz t, N 0 + βφ t ) v t+1 = βφt+1 N 0 + βφ t zt t ).

6 6 SUBMITTED TO A JOURNAL The function F l, τ) and G l, τ) are the meage mean and variance, repectively, operate element-wie on vector, and are computed a follow: Fz l, τ) = l f l ẑ l )d l 9) l Gz l, τ) = l 2 f l ẑ l )d l Fz l, τ) 2. l Here, f z) i the poterior pdf f z) = 1 Z pz )p) with pz ) CN, τ), p) i given in 2), and Z i a normalization contant. The etimate and error variance of LAMA are z t and σt,lama 2 = N 0 + βφ t, repectively. In order to analyze the pot-equalization SINR of LAMA-PD, it i key to realize that the equalization output z t i equivalent to that of the original centralized LAMA algorithm in [22]. A hown in [22], LAMA and hence LAMA-PD) decouple the MIMO ytem into parallel AWGN channel. More pecifically, the equalizer output 8) of LAMA can be modeled a in 5), where the decoupled noie variance σt 2 at iteration t can be tracked uing the tate evolution SE) framework in the largeytem limit and for Rayleigh fading channel. The following reult, with proof in [41], ummarize thi SE framework. Theorem 3 [22, Thm. 1]). Fix the ytem ratio β = U/B and the ignal prior 2). Aume the large-ytem limit and Rayleigh fading channel. Then, the decoupled noie variance σt 2 of LAMA and LAMA-PD at iteration t i given by the recurion: Here, the MSE function i given by σ 2 t = N 0 + βψσ 2 t 1). 10) Ψσ 2 t 1) = E S,Z [ FS + σ t 1 Z, σ 2 t 1) S 2 ], 11) where the function F i given in 9), S p) a in 2), Z CN 0, 1), and σ 2 1 i initialized by σ 2 1 = N 0 + βe. For t, the SE recurion in 10) converge to the ame fixed-point equation of linear equalizer in 7), where the only difference i the MSE function 11). If there are multiple fixed point, then we elect the larget σpd 2, which i, in general, a ub-optimal olution. 2 A for linear equalizer, we can ue the fixed-point equation in 7) to analyze the potequalization SINR performance of LAMA and LAMA-PD. Unfortunately, there are no cloed-form expreion known for the decoupled noie variance or the SINR for LAMA and LAMA-PD with dicrete contellation, due to the pecific form of the MSE function 11). Neverthele, we can numerically compute 11) and, hence, analyze the SINR. A correponding SINR comparion with linear equalizer i given in Section V. IV. FULLY DECENTRALIZED FD) EQUALIZATION We next dicu optimal fuion for linear and nonlinear equalization in the PD architecture a depicted in Fig. 1b). We then analyze the pot-equalization SINR of the propoed equalizer depending on the antenna cluter allocation trategy. 2 See [38] for more detail on the exitence of multiple fixed-point and on condition for which LAMA achieve individually optimal performance. A. Optimal Fuion for the FD Architecture A detailed in Section II-D, each cluter c = 1,, C in the FD architecture independently compute a local etimate z c and aociated error variance vector σc 2. Then, the vector z c and σc 2 for c = 1,, C are fued to compute the final output tuple {z, σ 2 }. Since in the large-ytem limit and for Rayleigh fading channel, the conidered equalizer decouple MIMO ytem into parallel and independent AWGN channel ee Section II-E), we focu on linear fuion of the local etimate, indicated with in Fig. 1b). Specifically, the propoed FD architecture compute the fued etimate z by combining the local etimate for each UE a follow: z u = ν c,u z c,u, u = 1,, U. 12) Here, z c,u i the local etimate for UE u at cluter c and the weight ν c,u, u = 1,, U, depend on the per-cluter error variance vector σ 2 c. In what follow, we are intereted in the optimal et of weight for the following criterion. Definition 3 Optimal fuion). Optimal fuion for the FD architecture maximize the per-ue pot-equalization SINR of the final etimate z u obtained from 12) while C ν c,u = 1. In other word, optimal fuion define a et of weight ν c,u, c = 1,, C, u = 1,, U, o that the decoupled noie variance contained in σ 2 aociated with the fued etimate z are minimized. The following reult ummarize the optimal fuion rule; a hort proof i given in Appendix A-B. Lemma 4. Let σc,u, 2 c = 1,, C, u = 1,, U, be a et of given error variance for UE u and cluter c. Aume that the reidual interference and noie term are zero mean and uncorrelated among the cluter. Then, the weight that yield optimal fuion according to Definition 3 are given by ν c,u = 1 σ 2 c,u C 1 σ 2 c =1 c,u for c = 1,, C and u = 1,, U. ) 1, 13) B. SINR Analyi of Optimal Fuion in the FD Architecture We are now intereted in analyzing the pot-fuion SINR for the FD architecture in the large-ytem limit. The following theorem analyze the decoupled noie variance σc 2 for each cluter c = 1,, C; the proof i given in Appendix A-C. Lemma 5. Aume MRC, ZF, L-MMSE, or LAMA equalization in each cluter c = 1,, C. Conider the large-ytem limit and Rayleigh fading channel. Then, the input-output relation of each cluter i decoupled into parallel channel of the form 5) with decoupled noie variance σ 2 c given by a olution to the following fixed-point equation: w c σ 2 c = N 0 + βψσ 2 c ). Here, Ψσ 2 c ) i the MSE function of the equalizer in cluter c. Thi reult how that the per-ue error variance σ 2 c,u will become independent of the UE index u in the largeantenna limit and for Rayleigh-fading channel. Furthermore,

7 C. JEON ET AL. 7 the decoupled noie variance σ 2 c depend on the fraction w c of BS antenna aociated with cluter c. The following reult etablihe the pot-fuion SINR in the FD architecture; a hort proof i given in Appendix A-D. Theorem 6. Let the aumption of Lemma 5 hold and σc, 2 c = 1,, C, be the per-cluter decoupled noie variance. Then, the decoupled noie variance σfd 2 of the fued etimate in 12) of the FD architecture i given by C ) 1 σfd 2 1 = = N 0 + β ν c Ψσc 2 ). 14) σ 2 c We note that thi reult implie that the pot-fuion SINR with optimal fuion according to Definition 3, denoted by inr FD, correpond to the um of the per-cluter SINR value. Finally, we have the following intuitive reult which implie that for a given equalizer, the FD architecture cannot outperform the PD architecture; the proof i given in Appendix A-E. Lemma 7. Let N 0 > 0 and aume the large-ytem limit and Rayleigh-fading channel. Then, the output SINR for the FD and PD architecture atify inr FD inr PD. Equality hold for β 0, C = 1, or if MRC-baed equalization i ued. C. Antenna Partitioning Strategie for Linear Equalizer We now analyze the pot-fuion SINR performance of linear algorithm for the FD architecture, depending on the antenna allocation trategy, i.e., on the fraction of antenna w c ued per cluter c. For the following analyi, we aume the largeytem limit and Rayleigh fading channel. For MRC with the FD architecture, the pot-fuion SINR i equivalent to that of the PD architecture and that of centralized proceing), a hown in Lemma 7. Hence, the antenna partitioning trategy doe not affect the SINR performance. For ZF equalization in the FD architecture, we have the following reult; the proof i given in Appendix A-F. Lemma 8. Aume that the B BS antenna are divided into C cluter o that w c β hold for c = 1,, C. Then, the pot-fuion SINR for ZF equalization i given by inr ZF FD = E N 0 1 Cβ). 15) Interetingly, we oberve that the pot-fuion SINR inr ZF FD doe not depend on the antenna allocation trategy; thi implie that the per-cluter antenna fraction w c can be choen arbitrarily a long a w c β for c = 1,, C. 3 Note, however, that equally-ized cluter are deirable in practice a they may minimize the interconnect or chip I/O bandwidth a well a the computational complexity per computing fabric. For L-MMSE equalization in the FD architecture, we have the following reult; the proof i given in Appendix A-G. Lemma 9. Aume that the B BS antenna are divided into C cluter o that C w c = 1 hold with w c 0 for c = 3 The condition w c β implie that C wc = 1 Cβ o the SINR expreion in Lemma 8 i well-defined. 1,, C. Then, the pot-fuion SINR of the L-MMSE equalizer i given by inr L-MMSE FD = 1 1 E ) 2 w c β) + 4 E w c 2 N 0 N 0 1 C E ) 1 Cβ) 16) 2 N 0 We ee from Lemma 9 that the pot-fuion SINR expreion for L-MMSE equalization depend on the antenna allocation trategy, i.e., on the weight w c, which i in contrat to ZF equalization cf. Lemma 8). In addition, L-MMSE equalization doe not require the retriction w c β for ZF-equalization a the pot-fuion SINR expreion hold even for underdetermined ytem [26]. Hence, it i natural to ak what the optimal cluter allocation trategy i. The following reult i rather diappointing; the proof i given in Appendix A-H. Lemma 10. The cluter allocation trategy that maximize the pot-fuion SINR for the L-MMSE equalizer inr L-MMSE FD i w c = 1 for ome c and w c = 0 for c c. Clearly, without any ytematic requirement on the cluter ratio w c, c = 1,, C, beide w c 0, maximizing inr L-MMSE FD o that C w c = 1 correpond to a centralized architecture, i.e., all antenna hould be allocated to a ingle cluter. Since the key idea of DBP wa to mitigate interconnect and I/O bandwidth a well a computation bottleneck, uch an optimal allocation trategy i undeirable in practice. We next how that the mot deirable from a practical viewpoint) cluter allocation trategy, i.e., one for which all cluter have an equal number of antenna, yield the wort pot-fuion SINR; the proof i given in Appendix A-I Lemma 11. Aume that the B BS antenna are divided into C cluter o that C w c = 1 with w c 0, c = 1,, C. Then, we have the following lower bound on the pot-fuion SINR: inr L-MMSE FD 1 1 E ) 2 1 Cβ) + 4 E C 2 N 0 N 0 1 C E ) 1 Cβ). 17) 2 N 0 Furthermore, the lower bound i achieved with equality if the antenna are ditributed uniformly acro all cluter, i.e., where w c = 1/C for c = 1,, C. We conclude by noting that even though uniform cluter ize are the wort for L-MMSE equalization in the FD architecture, L-MMSE equalization outperform ZF equalization for all poible partitioning cheme in term of the pot-fuion SINR. Hence, L-MMSE equalization i deirable in practice. Remark 3. The preented SINR analyi for optimal antenna partitioning with the L-MMSE equalizer alo applie to LAMA- FD. A detailed SINR analyi, however, require numerical integration a no cloed-form expreion exit for the MSE Ψσ 2 ) function for LAMA for QAM/PSK contellation [42], [43]. To enable the intereted reader to conduct thi performance analyi for a range of ytem configuration, we will provide a imulator upon poible acceptance of the paper.

8 8 SUBMITTED TO A JOURNAL min. BS-to-UE ratio β LAMA-PD L-MMSE-PD ZF-PD MRC SNR lo at 1 db LAMA-FD L-MMSE-FD ZF-FD min. BS-to-UE ratio β LAMA-PD L-MMSE-PD ZF-PD MRC SNR lo at 1 db LAMA-FD L-MMSE-FD ZF-FD SNR lo [db] a) QPSK and target rate of R = 1.99 [bit/ue/channel ue] SNR lo [db] b) 16-QAM with target rate of R = 3 [bit/ue/channel ue]. min. BS-to-UE ratio β LAMA-PD LAMA-FD L-MMSE-PD L-MMSE-FD ZF-PD ZF-FD MRC target rate of 1.99 bpcu min. BS-to-UE ratio β LAMA-PD LAMA-FD L-MMSE-PD L-MMSE-FD ZF-PD ZF-FD MRC target rate of 3 bpcu achievable rate [bit/ue/channel ue] achievable rate [bit/ue/channel ue] c) QPSK with fixed 1 db SNR lo. d) 16-QAM with fixed 1 db SNR lo. Fig. 2. Achievable rate analyi of DBP with feedforward architecture. Minimum BS-to-UE antenna ratio β 1 veru SNR lo for QPSK a) and 16-QAM b) for fixed target rate R. Minimum β 1 veru achievable rate for QPSK a) and 16-QAM b) for a given SNR lo of 1 db. LAMA outperform MRC, ZF, and L-MMSE in the FD and PD architecture, epecially at high target rate. At low target rate, all equalizer and architecture perform equally well. V. NUMERICAL RESULTS We now invetigate the performance of decentralized equalization in the large-ytem limit and for Rayleigh-fading channel uing the SINR expreion from Section III and IV. We how error-rate imulation reult to validate our aymptotic reult in finite-dimenional ytem. We alo provide reult for an LTE-like maive MU-MIMO ytem to demontrate the efficacy of our olution in a realitic cenario. A. Achievable Rate Analyi We firt invetigate the achievable rate of our feedforward architecture with focu on the large-ytem limit and Rayleigh fading channel. We conider C = 2 cluter with uniform antenna partitioning, i.e., w c = 1/C for c = 1,, C. We define the average receive ignal-to-noie ratio SNR) a SNR = βe /N 0 and ue an interference-free AWGN channel with variance N 0 a the baeline, which coincide to the largeantenna limit of maive MU-MIMO ytem with β 0. Concretely, we will ue the following performance metric. Definition 4 SNR lo). We define the SNR lo of an equalizer a the exce SNR required to achieve the ame target rate R of an interference-free AWGN channel with variance N 0. In Fig. 2a), we ue QPSK and a target rate of R = 1.99 bit/ue/channel ue; in Fig. 2b) we ue 16-QAM and a target rate of R = 3 bit/ue/channel ue. Both figure invetigate the minimum required BS-to-UE ratio β 1 for a given SNR lo, which characterize how many more BS antenna are required by a given equalizer and feedforward architecture to be able to approach AWGN performance up to a given SNR gap. We oberve that for a mall SNR lo i.e., when achieving imilar performance a that of an interference-free AWGN channel), we require ignificantly more BS antenna than UE, irrepective of the algorithm and architecture. For an SNR lo of 1 db hown by a thick vertical line in Figure 2a) and 2b)), we ee that the PD architecture outperform the

9 C. JEON ET AL. 9 ymbol error rate LAMA-PD L-MMSE-PD ZF-PD MRC LAMA-FD L-MMSE-FD ZF-FD ignal-to-noie ratio [db] Fig. 3. Symbol error-rate SER) comparion of equalization in the large-antenna limit indicated with line) v. the imulated performance indicated by the marker) in a B = 256 BS antenna U = 16 UE maive MU-MIMO ytem with Rayleigh-fading channel. Evaluating the SER uing our analytical SINR expreion for the large-antenna limit cloely matche numerical imulation in finite-dimenional ytem for all conidered equalizer and architecture. packet error rate LAMA-PD LAMA-FD L-MMSE-PD L-MMSE-FD ADMM LTE minimum ignal-to-noie ratio [db] Fig. 4. Packet error-rate PER) of an LTE-like maive MU-MIMO-OFDM ytem with B = 64 and U = 16. LAMA for the PD and FD architecture clearly outperform L-MMSE while meeting the 10% LTE minimum PER requirement. LAMA-PD or L-MMSE clearly outperform the conenu-baed ADMM method from [8] which uffer from tranfer latency), wherea LAMA- FD cloely approache the performance at minimal lower latency overhead. FD architecture; thi fact i more pronounced in the QPSK cenario a we are trying to achieve 99.5% of the maximum poible rate of 2 bit/ue/channel ue for QPSK, wherea for 16-QAM, we are only trying to achieve 75% of the maximum rate. We alo ee that LAMA-PD ignificantly outperform linear equalizer in the PD and FD architecture; MRC require ignificantly higher BS-to-UE antenna ratio. Interetingly, for QPSK, LAMA-FD ignificantly outperform linear equalization algorithm for the PD architecture in Fig. 2a) but perform trictly wore for 16-QAM in Fig. 2b); thi i due to the fact that the ytem-ratio threhold for LAMA to achieve individually-optimal performance i higher for QPSK than for 16-QAM [22]. In ummary, LAMA-FD achieve imilar performance a linear equalizer with the PD architecture while reducing interconnect and chip I/O bandwidth. In Fig. 2c) and Fig. 2d), we fix the SNR lo to 1 db and plot the minimum BS-to-UE ratio β 1 and varying achievable rate for QPSK and 16-QAM, repectively. For both contellation, MRC perform equally well than all other method in the low-rate regime; note that the low-rate regime tranlate to the low-snr regime for which MRC i known to be optimal. For higher rate, however, MRC require ignificantly higher BS-to-UE antenna ratio compared to L- MMSE or LAMA-baed equalization. The PD architecture ignificantly outperform the FD architecture for all equalizer, which implie that for high-rate the PD architecture i the preferred choice. Interetingly, the minimum BS-to-UE antenna ratio remain contant for ZF; thi implie that a long a one operate below a certain antenna ratio β, ZF i able to upport all tranmiion rate; ee [28] for additional detail on thi behavior. Finally, we ee that the minimum BS-to-UE ratio β 1 decreae for LAMA-FD and LAMA-PD at high rate; thi behavior i due to the fact that LAMA in overloaded ytem i particularly robut at low and high value of SNR ee [22] for a detailed dicuion). B. Aymptotic v. Finite-Dimenional Sytem In Fig. 3, we compare our analytical SINR expreion in the large-antenna limit to thoe in a finite-dimenional maive MU-MIMO cenario. Specifically, we ue the SINR from 5) in a decoupled AWGN channel to analytically compute the ymbol error-rate SER) a well a the imulated SER in an uncoded B = 256 BS antenna, U = 16 UE maive MU-MIMO ytem with Rayleigh fading channel. We conider C = 8 cluter with uniform antenna partitioning, i.e., w c = 1/8 for all C = 8 cluter. Firt, we oberve that the imulated reult indicated with marker) cloely match our analytical expreion indicated with line). Second, we ee that the PD architecture ignificantly outperform the FD architecture for C = 8 cluter and LAMA outperform ZF and L- MMSE for both architecture. Third, we ee that MRC yield poor SER performance, which i due to the fact that MRC require extremely high BS-to-UE antenna ratio to upport 4 bit/ue/channel ue for 16-QAM; ee alo Fig. 2d). C. Coded Error-rate Performance in Realitic Sytem In Fig. 4, we invetigate the coded packet error-rate PER) in a realitic LTE-like maive MU-MIMO ytem with B = 64 BS antenna and U = 16 UE. We conider C = 2 cluter with uniform antenna partitioning. We ue OFDM with 2048 ubcarrier 1200 ued for data tranmiion) with 16-QAM, 14 OFDM ymbol per packet, and ue a weak rate-5/6 convolutional code with oft-input Viterbi decoding. We conider a WINNER II channel model in an outdoor-toindoor cenario. For LAMA-PD and FD, we ue 10 iteration and perform meage damping to mitigate performance lo for finite-dimenional ytem with correlated MIMO channel matrice [44]. We alo compare LAMA and L-MMSE to the conenu-baed ADMM method for DBP propoed in [8], where we ue 10 iteration. Firt, we ee that LAMA-PD outperform all other equalization algorithm by a ignificant

10 10 SUBMITTED TO A JOURNAL margin, when conidering the LTE minimum PER pecification of 10%. Second, we oberve that the conenu-haring ADMM method perform lightly better than that of LAMA-FD. The ADMM-baed method, however, require iterative conenu exchange among the cluter which reult in low throughput; ee our GPU implementation reult in Section VI-C. VI. MULTI-GPU SYSTEM IMPLEMENTATION We now preent implementation reult of our algorithm and architecture on a multi-gpu ytem to validate the calability, throughput, and latency in a realitic cenario. We furthermore provide a comparion to exiting conenu-baed DBP algorithm and centralized equalizer. In order to fully utilize the available GPU reource, we conider an OFDMbaed ytem a in Section V-C, which enable u to not only parallelize acro antenna but alo acro ubcarrier. Remark 4. A in [8], the provided multi-gpu implementation erve a a proof-of-concept to ae the efficacy and calability of our olution when implemented on real hardware. In practice, we expect that our olution will be implemented on cluter coniting of field-programmable gate array FPGA) or application-pecific integrated circuit ASIC), which offer higher computing efficiency and lower tranfer latency. A. Experimental Platform In Fig. 5, we how the ued Nvidia DGX-1 multi-gpu ytem [45] coniting of eight Tela V100 Volta GPU with 300 GB/ bi-directional NvLink interconnect and two 20-core Intel Xeon E v4 CPU. Each GPU provide 5120 CUDA core and 16 GB high bandwidth memory HBM). In what follow, we ue C GPU when proceing C antenna cluter; other partitioning cheme are poible. Our equalization algorithm and architecture are implemented with the CUDA 9.2 toolkit [46] and the Nvidia collective communication library NCCL) v2.2 [47] oftware tack. The NCCL ue the meage paing interface MPI) library, which improve the efficiency of inter-gpu collective communication over NvLink [48] by leveraging the CUDA-aware MPI technology [49] for direct GPU-to-GPU memory copy. B. Implementation Detail All decentralized feedforward equalizer propoed in Section III and IV are proceed in the following three tep: i) calculate local intermediate reult at each antenna cluter, ii) fue local reult at the centralized proceor, and iii) perform neceary centralized computation to obtain the final equalization output. We ue the available CPU to chedule the workload and initialize C MPI procee, each proce uperviing an individual GPU for deign decentralization. The propoed decentralized algorithm were implemented on the multi-gpu ytem uing the following procedure: We accelerate local computation at the C antenna cluter, each uing a dedicated GPU with multi-threaded CUDA kernel function. We utilize collective inter-proce communication among the C GPU via NCCL over NvLink to realize low-latency gathering of the local reult at the mater GPU. We complete the centralized computation at the mater GPU for high efficiency. We note that equalization with the PD architecture generally require fewer local computation, but more data for fuion and computation at the centralized mater GPU, compared to equalization with the FD architecture. We now decribe the PD and FD architecture in detail. To keep the dicuion of the FD architecture hort, we only dicu the procedure for LAMA, a the ame methodology i ued for the linear equalization algorithm; ee [50] for more detail. 1) PD Architecture: The local computation at each GPU include the partial MRC output yc MRC = H c y c and the partial Gram matrix G c = H H c H c. To maintain high GPU occupancy, we aggregate thee workload acro a batch of ubcarrier and proce them in parallel. To proce the batched matrix-matrix or matrix-vector multiplication required for partial MRC and Gram computation efficiently, we take advantage of the cublas library, a collection of CUDAaccelerated baic linear algebra ubprogram BLAS), and pecifically, the cublacgemmbatched library function for fat matrix multiplication with complex-valued floating-point entrie. In a ingle invocation of the batched function call, we calculate G c for N c active ubcarrier batchize = N c ) aociated with a certain OFDM ymbol, and reue them acro N ym OFDM ymbol within the channel coherence time to reduce complexity. In contrat to the Gram matrix calculation, we compute yc MRC for a total of N c N ym ubcarrier batchize = N c N ym ) in a function call. Thi i neceary becaue yc MRC alo depend on receive vector y c, which varie for each OFDM ymbol. We finally fue the local G c and yc MRC that reult in a total meage ize of U U N c C + U N c N ym C at the mater GPU. For LAMA-PD hown in Algorithm 1, each iteration mainly involve matrix-vector multiplication and vector operation, which include vector addition, ubtraction, and dot-product. Although matrix-vector multiplication can be efficiently computed by the batched cublas function with batchize = N c N ym, a done for preproceing, we alo deigned cutomized multi-threaded kernel function for the vector operation to fully exploit the on-chip memorie of GPU. Specifically, for certain kernel, we combine multiple vector operation which can hare intermediate reult uing fat local regiter. Since the intermediate vector within each LAMA iteration, uch a, v, and z, cale with the UE number U, multi-threaded computation for vector addition, ubtraction, and caling are traightforward; we launch a kernel with N c N ym U thread to proce each of U entrie in a vector for a total of N c N ym ubcarrier in parallel. For the vector dot-product operation, a an example, when we update φ in Algorithm 1, we reort to the warp huffle technique, where a thread can directly retrieve regiter value from another thread efficiently, to obtain a um reduction of U vector entrie acro U thread in the ame warp. If U > warpize = 32, then we can alo ue the on-chip hared memory for the neceary inter-thread communication. After the lat LAMA iteration T max, we finally calculate the global LAMA-PD output at the mater GPU.