Analysis and Implementation of a Hardware-in-the-Loop Simulation

Transcription

1 DINAME 27 - Proceedings of the XVII International Syposiu on Dynaic Probles of Mechanics A. T. Fleury, D. A. Rade, P. R. G. Kurka (Editors), ABCM, São Sebastião, SP, Brail, March 5-, 27 Analysis and Ipleentation of a Hardware-in-the-Loop Siulation Eduardo Moraes Coraça, Janito Vaqueiro Ferreira Rua Mendeleyev, 2 - Cidade Universitária, Capinas - SP Faculdade de Engenharia Mecânica - UNICAMP eduardocoraca@gail.co, janito@fe.unicap.br Abstract: Coputer siulations are often perfored in order to analye systes and subsystes dynaic behavior. However there ay be soe parts that are too coplex to be atheatically odeled, which occurs due to nonlinearities and to coupling of subsystes. In this scenario, a hardware-in-the-loop (HiL) test can be used, which consists of separating the overall syste into two subsystes: a physical one, usually containing the coplex coponent, and a nuerical one, to be siulated on a coputer. The nuerical one calculates the variable to be iposed on the hardware, such as a displaceent or an electrical current. The hardware responds to the input and its response, such as a force or a voltage, is easured and sent back to the nuerical subsyste. Thus, the HiL test is a real-tie closed-loop syste, which has been used for the past 2 years in the autootive area, in applications such as anti-lock brake systes and sei-active suspensions. In order to close the loop, a transfer syste coposed of actuators and sensors is required. Since the transfer syste is a dynaic syste as well, it cannot respond instantaneously to a coand. So there is a tie lag between the two subsystes, which deteriorates the closed-loop response and can also lead to stability issues. Many studies in this area were conducted in order to analye the delay s effect and how to attenuate it, however none of the were % effective. In this paper a HiL test is perfored on a ass-spring-daper syste, using the spring as the hardware. A dspace DS-2 DSP board is used for the real-tie application together with MATLAB/Siulink. An Instron/Schenck hydraulic actuator is used, as well as LVDT and Load Cell sensors, to actuate and sense forces. Methods for delay copensation are presented, siulated in MATLAB and, then, copared experientally. Keywords: Hardware-in-the-loop, real-tie, siulation, delay copensation, closed-loop INTRODUCTION In the developent stage of new technologies, syste siulation before its conception is indispensable, leading to lower cost with prototypes and safer product validation. However, a atheatical odel of the syste of interest ay not be easily obtained, since non-linearities and coplexities ay be present. In this context, a Hardware-in-the-Loop (HiL) test ay be eployed, which consists of dividing the overall systes into two subsystes, one that is a nuerical odel (the software) and the other that is the physical coponent of interest (the hardware). With actuators and sensors, the two subsystes are coupled and a real-tie siulation can be eployed, thus analying the overall syste dynaics. Figure shows a generic HiL siulation block diagra. Signal r[k] is the external situation iposed in the syste, like a force or displaceent, and signal [k] is the physical subsyste s easured response. u[k] is the nuerical subsyste input, which is calculated based on signals r[k] and [k]. The software output y[k] is converted to a continuous signal y(t) through a D/A converter which is then sent to an actuator, who will ipose it to the physical coponent through signal x(t). The coponent s response f (t) is easured by a sensor, yielding (t), which is converted through an A/D converter to [k]. Fro this analysis it is clear that the HiL test is a closed-loop real-tie syste. r[k] + u[k] y[k] Model D/A y(t) Actuator x(t) Coponent [k] A/D (t) Sensors f(t) Software Interface Figure : Typical HiL test block diagra. Hardware HiL testing begun in aerospace industry, through flight siulators and issile location systes (Bacic, 25). In the past 2 years, the technique has been used ainly in autootive applications. Svenson et al. (29) developed a HiL

2 Analysis and Ipleentation of a Hardware-in-the-Loop Siulation siulator in order to test heavy trucks stability control systes, where the braking syste and its controllers were the hardware and, as software, the truck s odel was eployed. One of the ain applications of HiL is within suspension systes testing. Hong et al. (22) used HiL test to evaluate a Skyhook control ethod, developed by the authors, for McPherson sei-active suspensions. The hardware in this situation was the variable daper, which is a very non-linear coponent, while the controller odule and the other suspension coponents were the odeled software. The ain proble that arise fro HiL siulations is a tie delay inherent to the interface between software and hardware. Since the actuator cannot respond instantaneously to a coand, there is an inevitable tie delay which is inside the closed-loop syste. Hence, the response presents an error and, depending on the aount of delay and in dynaic characteristics of the subsystes, it ay also lead to instability. Delay copensation ethods were proposed and any works on this area were perfored in order to iprove HiL results, but no ethod is perfect. The Forward Prediction Method, as described by Wallace et al (25), adjusts a polynoial to the past calculated output values of the software and extrapolates this curve, forward predicting the signal s value in the future, in a tie equal to the tie delay. Thus, the closed-loop syste is copensated. Another ethod was proposed by Sith (959), but not for the HiL context. This ethod, known as the Sith Predictor, uses a odel of the syste under test in order to predict its future response, thus copensating the tie delay. However, a odel of the plant is not available when HiL test is eployed. By eploying an approxiation of the plant, errors arise, thus this is not the ost indicated ethod. A siilar idea was proposed by Gawthrop et al. (28) for real-tie siulations, where a odel is needed but, again, this is not the best solution for this application. A different approach was taken by Carrillo (22), where an analysis of the discrete operations perfored by the acquisition boards was eployed in order to characterie the tie delay. By choosing the siulation s saple tie as larger than the tie delay, the authors noticed that the equivalent delay becoes equal to one tie step, which allows for a different kind of correction based on the board s tasking order alteration. However, a high sapling period ay not be suitable for soe applications, leading even to stability issues. In this paper a Hardware-in-the-Loop test is applied to a ass-spring-daper syste. In order to investigate how the tie delay affects the syste s dynaics, the hardware is a known spring, because it can be identified and odeled. Delay copensation ethods are presented, applied and, because the hardware is known, it is possible to copare the results to a reference response. A new copensation ethod is then proposed and copared to the previous ones. Nuerical siulations are run by using a virtual spring and, then, experients are conducted with the real spring by using MATLAB/Siulink software, dspace acquisition board and Schenck hydraulic actuator. EXPERIMENTAL SETUP Equipent The following equipents were used in order to couple the nuerical and physical subsystes: MATLAB/SIMULINK software, to odel the nuerical subsyste; dspace DS-2 board, which contains A/D and D/A converters and the ControlDesk software to onitor the signals; Instron/SHENCK actuator syste, used for displaceent control, equipped with a LVDT sensor for displaceent sensing and load cell for force sensing, shown in Figure 2. Figure 2: Instron/SHENCK actuator. The dspace board works as a ero-order holder syste, which eans that the digital input signal in the D/A board is held constant during one sapling interval. The Instron/SHENCK actuator has its own control software called Rs- LabSite, in which it is possible to send coand signals to the cylinder and also set gains for the PID controller, which were not altered during the tests.

3 Eduardo Moraes Coraça, Janito Vaqueiro Ferreira Syste odeling A ass-spring-daper syste is analyed, with the spring being the physical coponent. The full syste odel and the syste without spring, to be ipleented in the HiL setup, are derived in the following subsections. Full ass-spring-daper odel The ass-spring-daper syste is indicated in Figure 3(a), where F p is the weight force in [N], which refers to ass in [kg], k is the stiffness of the spring in [ N Ns ] and c is the viscous daping paraeter in [ ]. Figure 3(b) shows a free-body diagra for this proble. F and F a are the forces due to the spring and daper, respectively, in [N]. y F y F k c F Fa (a) Mass-spring-daper. The equation of otion is then given by Equation. (b) Free-body diagra of the ass-springdaper syste. Figure 3: Model of the syste under analysis. ÿ + cẏ + ky = F F p () In order to represent the syste in state-space for, these equations need to be re-written in ters of states, which is indicated by Equations 2 and 3. x is the state vector, y contains the syste s outputs and u represents the inputs. ẋ = Ax + Bu (2) y = Cx + Du (3) The following states are adopted: x = y and x 2 = ẏ. The syste s input is u = F F p while the output is displaceent, y = x. This leads to the state-space odel described by Equations 4 and 5 [ ] [ ] ẋ = k c x + u (4) y = [ ] x + [ ] u (5) HiL odel with physical spring In this case the ter F, corresponding to the spring restoring force, is odeled as an input, which eans that u = F F p F. Then, Equation can be re-written in state-space for, adopting the sae state vector x, as Equations 6 and 7 [ ] [ ] ẋ = c x + u (6) y = [ ] x + [ ] u (7)

4 Analysis and Ipleentation of a Hardware-in-the-Loop Siulation Hardware identification Knowledge about the spring, sensor and delay characteristics is needed in order to validate the HiL siulation results. A displaceent sine wave was generated in Rs-LabSite software and iposed in the spring. The force/displaceent behavior is shown in Figure 4(a). Since a sall non-linearity was noted, a third order polynoial was fitted to the curve, which is described by Equation 8, where the unit of F is [kn] and the unit of y is []. Note that y = the spring is already copressed. F =,28. 7 y 3 3,44. 5 y 2 +,238y,73 (8) The syste delay is defined as the tie needed by the actuator to execute a coanded displaceent. By inputing a sine wave and easuring the response, it was possible to quantify the tie delay as T D = 6[s]. Figure 4(b) shows the actuator s behavior Measured displaceent Coanded displaceent F [kn] Displaceent [] (a) Force/displaceent behavior of the spring under test (b) Delay between coanded and executed displaceent. Figure 4: Syste characteristics. Finally, in order to deterine the gains involved in the voltage-displaceent conversion and vice-versa, a voltage sine wave was generated in SIMULINK, sent to the D/A board with the help of ControlDesk software and then sent to the actuator, which led to a 4 [ V ] gain. Then, by easuring force rather than displaceent, a [ kn V ] gain was deterined for the force-voltage conversion. DELAY COMPENSATION METHODS AND SIMULATIONS Three different ethods are presented and siulated in this work. The following subsections describe their functionalities. Tasking order sequence alteration ethod As analyed by Carrillo (22), the response delay is exactly T S when T S > T D, where T S is the sapling tie. The discrete state equations are represented by Equations 9 and, where the subscript d in the atrices represent their discrete equivalent. x[k + ] = A d x[k] + B d u[k] (9) y[k] = C d x[k] + D d u[k] () By analying the output equation in tie step k it can be seen that the calculation of y[k] depends on x[k] and u[k]. For this ipleentation, the tasking order states that vector y[k] = f (x[k], u[k]) is calculated before the state update equation x[k + ] = f (x[k],u[k]). However, as there is one tie step delay when easuring the physical subsyste s reaction force, the state equations input is u[k] = F[k] F P F [k ], which leads to a wrong value of u[k]. The correction proposed by the author lies on the tasking order alteration. The state vector is updated before the output equation, which eans that, at instant k, x[k] = f (x[k ],u[k ]) is calculated and, then, y[k] is coputed. Note that in order to achieve u[k ] the

5 Eduardo Moraes Coraça, Janito Vaqueiro Ferreira input force ust also be delayed. This ethod works as long as the output y[k] does not depend on u[k]. In other words, atrix D ust be ero. This ethod can be ipleented by changing the discrete state equations to and 2, which can be easily ipleented in SIMULINK. x[k] = A d x[k ] + B d u[k ] () y[k] = C d x[k] Polynoial extrapolation ethod As described by Wallace et al (25) this ethods consists of using the previous values of a signal y(t) to predict its future value. In order to do so, a N th order polynoial is calculated each tie step by using y[k] and its previous values y[k ], y[k 2],..., y[k (n )], where n is the the nuber of points and it ust follow the relationship stated in Equation 3. (2) n = N + (3) The value of y predicted P tie steps ahead, y = y[k + P], is given by Equation y = [ PT S... P N T N ] T S... ( T S ) N S (n )T S... ( (n )T S ) N y[k] y[k ]. y[k N] (4) Coputing Equation 4 every iteration should be avoided because it contains a atrix inversion procedure. In order to avoid this proble, it can be re-written by Equation 5, where the vector of coefficients a = [ a a... a N ] can be calculated before the real-tie siulation through Equation 6. y[k] y [k] = [ ] y[k ] a a... a N. y[k N]... a = [ PT S... P N T N ] T S... ( T S ) N S (n )T S... ( (n )T S ) N (5) (6) Taylor series ethod A novel ethod is proposed based on the Taylor series, which approxiates a function f (x) near a point a based on values of its derivatives evaluated at this point, as indicated by Equation 7 where n is the n th derivative of function f (x). f (x) n i= f (n) (a) (x a) n n! When applied to a real-tie siulation, the objective is to predict the nuerical subsyste output at a future tie y(t + T ), where t is the actual tie and t + T is the future tie. By adopting a = t and x = t + T on Equation 7, the prediction is indicated by Equation 8. (7) y(t + T ) y(t) + y () (t)t + y (2) (t) T 2 2! + y(3) (t) T 3 3! + + y(n) (t) T n n! By odeling the nuerical subsyste on a state-space for one have access to y(t), y () (t) and y (2) (t) through the states and inputs of the syste, therefore there is no need to differentiate signals. For a echanical syste, as the one (8)

6 Analysis and Ipleentation of a Hardware-in-the-Loop Siulation analyed in this work, it is known that y(t) = x (t) and y () (t) = x 2 (t). The second derivative can be obtained fro the input u and the states. For this syste specifically, through Newton s Second Law, it is known that y (2) = x 2 = u c x 2. By substituting the previous values into Equation 8, the predictor s expression is given by 9, where ε represents the truncation error. ( y(t + T ) = x (t) + x 2 (t)t + u(t) c ) T 2 x 2(t) + ε(t) (9) 2 The discrete version of the predictor is given by Equation 2, where y is the predicted value of y, which will be sent to the actuator. ( y [k] = x [k] + x 2 [k](t S P) + u[k] c ) x (TS P) 2 2[k] 2 [ Adopting C = 2. T S P c(t SP) 2 2 ] + ε[k] (2) e D = (T SP) 2 2, Equation 2 can be written in atrix for, indicated by Equation y [k] = C x[k] + D u[k] + ε[k] The value of ε ust be estiated in order to iprove the prediction, which can be done by estiating the displaceent error. Because y [k] will be delayed, there will be a difference between the nuerical subsyste output y[k] and the value executed in fact, y [k P]. Equation 22 indicates the estiation of ε. (2) ε[k] = y [k P] y[k] Nuerical siulations In order to copare the ethods listed before, nuerical HiL siulations were conducted by using a odel of the spring, given by Equation 8, as the siulated, or virtual, hardware. The sapling tie effect was analyed through two siulation setups:. Setup : T S > T D 2. Setup 2: T S < T D The SIMULINK block diagra used for T S > T D is shown in Figure 5(a), while the one used for T S < T D is shown in Figure 5(b). When adopting T S > T D the effective delay becoes a one-step tie delay, which is odeled by the / block in Figure 5(a). For T S < T D the delay was odeled as being proportional to T S by a factor of d (T D = dt S ), as indicated by Figure 5(b). Finally, the k ter refers to the value of F (x = ) fro Equation 8. A uniforly distributed rando wave signal with aplitude A F [N] is the external force acting on the ass. Physical paraeters chosen for the siulations are = 5[kg], F P = 49.5[N], A F = [N], ω F = 2[ rad Ns s ]. For the daping characteristic it was used c = 6[ ] for Setup and c = 2[ Ns ] for Setup 2. Block Discrete State-Space contains atrices A d, B d, C d and D d fro the nuerical odel, obtained in MATLAB. (22) Unifor Rando Nuber x(n+)=ax(n)+bu(n) y(n)=cx(n)+du(n) Discrete State-Space [] to [] Scope Unifor Rando Nuber x(n+)=ax(n)+bu(n) y(n)=cx(n)+du(n) Discrete State-Space [] to [] Scope Weight Force [kn] to [N] Weight Force [kn] to [N] Constant Constant k k Unit Delay Spring Model Spring Model Delay F [kn] F [kn] Z -d (a) Block diagra for Setup (T S > T D ) Figure 5: Block diagras used for nuerical siulations. (b) Block diagra for Setup 2 (T S < T D ) The tie delay used for the siulations was equal to the easured, T D = 6[s]. A sapling tie of T S =.5[s] for Setup was chosen, and for Setup 2, T S = 2[s]. Figures 6(a) and 6(b) show the results for Setups and 2, respectively, copared to the undelayed syste (correct signal). Deterioration due to tie delay effects happens in both setups.

7 Eduardo Moraes Coraça, Janito Vaqueiro Ferreira 25 y 2 5 Delayed - Delayed (a) Siulation result for Setup (T S > T D ) (b) Siulation result for Setup 2 (T S < T D ) Figure 6: Siulation results for the delayed systes. The delay copensation ethods were ipleented on SIMULINK. Figure 7(a) shows the Tasking Order Sequence Alteration Method, in which the state equations were written explicitly as forulated in expressions and 2. Figure 7(b) shows the Polynoial Extrapolation Method, where the copensation algorith was siply ipleented in a Interpreted MATLAB Function, which was then called each tie step fro the SIMULINK siulation. Finally, Figure 7(c) shows the Taylor Series Method, which altered the state-space equations in order to ipleent expressions 2 and 22. Unifor Rando Nuber Weight Force Bd* u Cd* u [] to [] Unifor Rando Nuber Weight Force x(n+)=ax(n)+bu(n) y(n)=cx(n)+du(n) Discrete State-Space [] to [] [kn] to [N] Ad* u [kn] to [N] Constant Polynoial Extrapolation algorith y' Constant k k Spring Model Unit Delay Spring Model Delay F [kn] F [kn] Z -d (a) Siulation block diagra for the Tasking Order Sequence Alteration Method (b) Siulation block diagra for the Polynoial Extrapolation Method D' C' Unifor Rando Nuber Bd Cd [] to [] Weight Force Z -d [kn] to [N] Constant k Spring Model Delay F [kn] Z -d (c) Siulation block diagra for the Taylor Expansion Method Figure 7: Block diagras used for nuerical siulations with delay copensation. Figures 8(a), 8(b) and 8(c) shows the siulation results for Setup using the Tasking Order Sequence Alteration, Polynoial Extrapolation and Taylor Expansion Methods, respectively, and Figure 8(d) shows the difference between all the previous copensated signals copared and the correct one. It can be seen that the Tasking Order Sequence Alteration

8 Analysis and Ipleentation of a Hardware-in-the-Loop Siulation Method provides, in siulation level, a perfect delay copensation. But it ust be noted that it only works when T S > T D and D =. Thus, it ay be ipossible to use this ethod due to sapling period liitation, since it cannot be eployed for HiL testing of rapidly changing systes. And even in situations when the sapling tie is not a liitation, it clearly lowers the overall siulation precision. For the Polynoial Extrapolation and Taylor Expansion Methods it is possible to notice that the second one achieved a good result, while the first did not. This fact indicates a liitation of the polynoial ethod related to sapling tie, while the Taylor one provides better results for low saplings. Since results for Setup 2 were too close to the correct signal, only the difference plot is shown, in Figure 9. Both ethods presents a good copensation, noting that the Taylor one shows a noisy behavior due to the error estiation odel Copensated Syste 2 Copensated Syste (a) Setup siulation results for the Tasking Order Sequence Alteration Method (b) Setup siulation results for the Polynoial Extrapolation Method Copensated Syste Difference [] Taylor Expansion Tasking Order Polynoial Extrapolation (c) Setup siulation results for the Taylor Expansion Method (d) Difference between correct and copensated signal for all ethods for Setup. Figure 8: Siulation results for Setup. EXPERIMENTAL RESULTS The ethods presented in the previous section were ipleented on the real hardware. By using the equipents listed in Experiental Setup section, the HiL test was conducted. A daping of c = 3 Ns and tie steps of.[s] and 2[s] were eployed. For T S =.[s], Figure (a) shows a coparison between copensated, uncopensated and correct signals. Due to noise in signals, the copensation ethod is not able to provide a perfect test, but it can be seen that the response was iproved by eploying the ethod. Fro Figure (b), result for the Polynoial Extrapolation Method is shown, with T S = 2[s]. The easured signal tracked the correct one alost perfectly when copared to the uncopensated response. For this case, a second-order polynoial was used. Finally, Figure (c) shows the test result when using the Taylor Expansion Method, which clearly differs fro the correct result. The copensated systes did not follow the correct one because on a real environent there is noise and, also, the tie delay ay not hold constant. For the Tasking Order Sequence Alteration Method the result was excellent, since the

9 Eduardo Moraes Coraça, Janito Vaqueiro Ferreira Taylor Expansion Tasking Order Polynoial Extrapolation Difference [] Figure 9: Difference between correct and copensated signal for all ethods for Setup Tasking Order Uncopensated Polynoial Extrapolation Uncopensated (a) Tasking Order Sequence Alteration Method (b) Polynoial Extrapolation Method. Taylor Expansion Uncopensated (c) Taylor Expansion Method. Figure : Experiental results for HiL test with delay copensation ethods.

10 Analysis and Ipleentation of a Hardware-in-the-Loop Siulation response iproveent was clear. However, it can only be used when large tie steps are eployed, which ay not be possible in certain applications since this fact influences the stability of discrete systes. And even if the closed loop holds stable, a harsh tie behavior ay not be interesting for testing as can be seen, as an exaple, in ties t < [s] fro Figure (a), where abrupt changes happen and can be harful for the equipent. The Polynoial Extrapolation Method was the ost efficient because of the proxiity between correct and copensated signals. A sall steady state error can still be perceived, which ay have occurred due to the facts entioned above. The negative aspect is the sapling tie liitation. Although it was not investigated in this paper, a liit for the T S /T D relationship ay exist in order to aintain stability and accuracy, and it should be investigated in future works. Finally, the Taylor Expansion Method presented a very low perforance copared to its excellent siulation behavior. This ay have happened ainly due to the error estiation ε[k], which is affected by noise in the force easureent, and also due to variable tie delay. This ethod should be further iproved in order to apply in HiL tests. CONLUDING REMARKS In this paper the Hardware-in-the-Loop siulation technique was presented, studied and ipleented in a assspring-daper syste, where the hardware was the spring. A tie delay was identified and its effects on the closedloop behavior were analyed. It was found the sapling rate of the discrete HiL syste influences stability and the relation between delay and sapling ust be analyed prior to the test. Two delay copensation ethods, Polynoial Extrapolation Method and Tasking Order Sequence Alteration Method, were studied and ipleented. A new technique, based on Taylor series, was presented and copared. In ters of nuerical siulations of the HiL test, it was seen that the proposed ethod overcae the other two. In ters of experiental tests, the Polynoial Extrapolation Method showed better perforance. New ways for estiating the truncation error and also studies of the easureent noise influence on the ethods should be considered for future works. REFERENCES Bacic, M., 25 On hardware-in-the-loop siulation. Proceedings of the 44th IEEE Conference on Decision and Control. IEEE, p Carrillo, C. A. G., 22, Estratégias para a correção dos efeitos de atraso de sisteas Hardware In the Loop (HIL). Dissertation. Universidade Estadual de Capinas. Gawthrop, P. J., et al., 28, Eulator-based control for actuator-based hardware-in-the-loop testing. Control Engineering Practice 6.8: Hong, K., Sohn, H., and Hedrick, J., 22, Modified skyhook control of sei-active suspensions: A new odel, gain scheduling, and hardware-in-the-loop tuning. Journal of Dynaic Systes, Measureent, and Control 24. : Iserann, R., J. Schaffnit, and S. Sinsel., 999, Hardware-in-the-loop siulation for the design and testing of enginecontrol systes. Control Engineering Practice 7.5: Misselhorn, W. E., N. J. Theron, and P. S. Els., 26, Investigation of hardware-in-the-loop for use in suspension developent. Vehicle Syste Dynaics 44.: Sith, J. M., 959, A controller to overcoe dead tie. isa journal 6.2: Svenson, A. L., et al., 29, Validation of hardware in the loop (hil) siulation for use in heavy truck stability control syste effectiveness research. 2th international technical conference on the enhanced safety of vehicles-(esv), Stuttgart, Gerany (9 89). Wallace, M. I., Wagg, D. J. and Neild, S. A., 25, An adaptive polynoial based forward prediction algorith for ulti-actuator real-tie dynaic substructuring. Proceedings of the Royal Society of London A: Matheatical, Physical and Engineering Sciences. Vol. 46. No The Royal Society. RESPONSIBILITY NOTICE The authors are the only responsible for the aterial included in this paper.