Area Time Efficient Scaling Free Rotation Mode Cordic Using Circular Trajectory

Transcription

1 IOSR Journal of Electroncs and Communcaton Engneerng (IOSR-JECE) e-issn: ,p- ISSN: Volume 7, Issue 1 (Jul. - Aug. 2013), PP Area Tme Effcent Scalng Free Rotaton Mode Cordc Usng Crcular Trajectory N. Hma bndu M.Tech ( VLSI Desgn), K. Geetha M.Tech, Assoc. Professor, Dept of Electroncs and Communcaton engneerng Sr Krshna Devaraya Engneerng College Gooty, Andhra Pradesh Abstract: Ths paper presents an area-tme effcent Coordnate Rotaton Dgtal Computer (CORDIC) algorthm that completely elmnates the scale-factor. Besdes we have proposed an algorthm to reduce the number of CORDIC teratons by ncreasng the number of stages. The effcent scale factor compensaton technques are proposed whch adversely effect the latency/throughput of computaton. The proposed CORDIC algorthm provdes the flexblty to manpulate the number of teratons dependng on the accuracy, area and latency requrements. The CORDIC s an teratve arthmetc algorthm for computng generalzed vector rotatons wthout performng multplcatons. Index Terms: coordnate rotaton dgtal computer (CORDIC), cosne/sne, feld-programmable gate array (FPGA), most-sgnfcant-1, recursve archtecture, Dscrete Fourer Transform (DFT), Dscrete Cosne transform (DCT), Iteratve CORDIC, Ppelned CORDIC. I. Introducton Year 2009 marks the completon of 50 years of the nventon of CORDIC (Coordnate Rotaton Dgtal Computer) by Jack E.volder. The beauty of CORDIC les n the fact that by smple shft-add operatons, t can perform several computng tasks such as the calculaton of trgonometrc, hyperbolc and logarthmc functons, real and complex multplcatons, dvson, square-root and many others. The CORDIC s an entretransfer computer, t contans a specal arthmetc unt consstng of three shft regsters, three adder- subtractor, and specal nterconnectons. The CORDIC s appled n dverse areas such as sgnal and mage processng, communcaton systems, robotcs and 3-D graphcs etc[1]-[3]. For applcatons where the angle of rotaton s known n advance, a method to speed up the executon of the CORDIC algorthm by reducng the total number of teratons s presented. Ths s accomplshed by usng a technque called angle recodng. The proposed MVR- CORDIC algorthm (modfed vector rotatonal CORDIC) wll saves the 50% executon tme n the teratve CORDIC structure, or 50%hardwarecomplexty n the parallel CORDIC structure compared wth the conventonal CORDIC scheme [4]-[6]. The correspondng archtectures come for both rotaton and vector modes and the other only for rotaton mode to perform the scalng factor compensaton n parallel wth the classcal CORDIC teratons. For fxed pont arthmetc area and latency of the proposed mplementaton s compared wth standard CORDIC [7]-[8]. The two area - tme effcent CORDIC archtectures have been suggested n [9]. In [11] the Coordnate Rotaton Dgtal Computer (CORDIC) rotator s a well known and wdely used algorthm wthn computers due to ts way of carryng out some calculatons such as trgonometrc functons, many others. The new archtecture whch are able to reach a 35% lower latency and a 36% reducton n area and power consumpton compared to the orgnal scalng free archtectures. II. Bref Overvew Of Cordc Algorthm To evaluate trgonometrc functons we have many approaches such as 1) Polynomal Approxmatons 2) Table lookup 3) CORDIC 1) Taylor Seres The Taylor seres expanson for sne s: sn x = x x3 3! + x5 5! x7 7! + Ths method s one of the oldest and most wdely, but the problem assocated wth ths method s, to get values of hgher accuraces, hgher order factoral and power has to be calculated. Moreover to mplement ths we would at least requre a multpler, dvder, adder and a subtractor. For good accuracy t would be 12 Page

2 Area Tme Effcent Scalng Free Rotaton Mode Cordc Usng Crcular Trajectory requred to take each term n calculaton tll they become nsgnfcant. Thus ths approach has a lot of hardware requrements as well as t s slow. 2) Look up Table The Lookup table approach nvolves storng values of sne and cosne at dfferent angles. Based on the number of values stored, the lookup table can be bg or small, but clearly, the smaller the lookup table, more s the error nvolved. The problem wth a bgger lookup table s that t requres more memory and memory s expensve. Moreover the sze of the Lookup table ncreases exponentally wth the ncrease n the precson of the angle. Though ths approach provdes fast results t s very expensve to mplement. 3) Cordc Algorthm CORDIC s an acronym for Coordnate Rotaton Dgtal Computer ntroduced by Jack E. Volder. It s an teratve algorthm capable of calculatng trgonometrc and varous other functons. In ths algorthm wth the help of an adder/subtractor, a small look up table and a shfter the trgonometrc functons can be calculated very easly. The advantage that Cordc offers over other algorthms are that t does not requre multplcaton or dvson blocks, nstead t works only wth a shfter, adder/subtractor and a small lookup table. Ths reduces the hardware requrement drastcally and provdes reasonably good speed. Many varatons have been suggested for effcent mplementaton of CORDIC wth less number of teratons over the conventonal CORDIC algorthm [4] [11]. The number of CORDIC teratons are optmzed n [4] [6] by greedy search at the cost of addtonal area and tme for the mplementaton of varable scalefactor. In [7] and [8] effcent scale-factor compensaton technques are proposed, whch adversely affect the latency/throughput of computaton. Two area-tme effcent CORDIC archtectures have been suggested n [9], whch nvolve constant scale-factor multplcaton for adequate range of convergence (RoC). The vrtually scale-free CORDIC n [10] also requres multplcaton by constant scale-factor and relatvely more area to acheve respectable RoC. The enhanced scale-free CORDIC n [11] combnes few conventonal CORDIC teratons wth scalng-free CORDIC teratons for an effcent ppelned CORDIC mplementaton wth mproved RoC. However, f used for recursve CORDIC archtecture, combnng two dfferent types of CORDIC teratons, degrades performance. The low complexty technque for elmnatng the scale factor s the use of Taylor seres expanson. The Scalng-Free CORDIC and modfed scale-free CORDIC are technques based on Taylor seres approach. The former suffers from low range of convergence (RoC) whch renders t unsutable for practcal applcatons, whle the latter extends the RoC but ntroduces predctable but constant scale-factor of 1/ 2. The other hardware effcent archtectures requre scale-factor compensatons to extend the range of convergence to the entre coordnate space. Sequental/Iteratve CORDIC It requres Maxmum number of Clock Cycles to calculate output, Mnmum Clock Perod per teraton, Varable Shfters do not map well on certan FPGA s due to hgh Fan-n. Fg:1. Varable Shfters 13 Page

3 Area Tme Effcent Scalng Free Rotaton Mode Cordc Usng Crcular Trajectory Parallel/Cascaded CORDIC: It has Combnatonal crcut More Delay, but processng tme s reduced as compared to teratve crcut. Shfters are of fxed shft, so they can be mplemented n the wrng. Constants can be hardwred nstead of requrng storage space. Fg.2. Parallel/Cascaded CORDIC The key concept of CORDIC arthmetc s based on the smple and ancent prncples of twodmensonal geometry. But the teratve formulaton of a computatonal algorthm for ts mplementaton was frst descrbed n 1959 by Jack E. Volder for the computaton of trgonometrc functons, multplcaton and dvson. Ths year therefore marks the completon of 50 years of the CORDIC algorthm. Not only a wde varety of applcatons of CORDIC have emerged n the last 50 years, but also a lot of progress has been made n the area of algorthm desgn and development of archtectures for hgh performance and low-cost hardware solutons of those applcatons. CORDIC-based computng receved ncreased attenton n 1971, by varyng a few smple parameters; t could be used as a sngle algorthm for unfed mplementaton of a wde range of elementary transcendental functons nvolvng logarthms, exponentals, and square roots along wth those suggested by Volder. Durng the same tme, Cochran benchmarked varous algorthms, and showed that CORDIC technque s a better choce for scentfc calculator applcatons. The popularty of CORDIC was very much enhanced thereafter prmarly due to ts potental for effcent and low-cost mplementaton of a large class of applcatons whch nclude: the generaton of trgonometrc, logarthmc and transcendental elementary functons; complex number multplcaton, egen value computaton, matrx nverson, soluton of lnear systems and sngular value decomposton (SVD) for sgnal processng, mage processng, and general scentfc computaton. The name CORDIC stands for Coordnate Rotaton Dgtal Computer. Volder [Vold59] developed the underlyng method of computng the rotaton of a vector n a Cartesan coordnate system and evaluatng the length and angle of a vector. The CORDIC method was later expanded for multplcaton, dvson, logarthm, exponental and hyperbolc functons. III. Ppelned Archtecture The prncple of ppelnng has emerged as a major archtectural attrbute of most present computer systems.ppelnng s one form of mbeddng parallelsm or concurrency n a computer system. It refers to a segmentaton of a computatonal process (say, an nstructon) nto several sub processes whch are executed by dedcated autonomous unts (facltes, ppelnng segments) 14 Page

4 Area Tme Effcent Scalng Free Rotaton Mode Cordc Usng Crcular Trajectory Fg.3.Ppe lne archtecture logcal vew Parallel CORDIC can be ppelned by nsertng regsters between the adders stages. In most FPGA archtectures there are already regsters present n each logc cell, so ppelne regsters has no hardware cost. Number of stages after whch ppelne regster s nserted can be modeled, consderng clock frequency of system. When operatng at greater clock perod power consumpton n later stages reduces due to lesser swtchng actvty n each clock perod.1 IV. Proposed Algorthm For Scalng Free Cordc The proposed desgn s based on the followng key deas: 1) we use Taylor seres expanson of sne and cosne functons to avod scalng operaton and 2) suggest a generalzed sequence of mcro-rotaton to have adequate range of convergence (RoC) based on the chosen order of approxmaton of the Taylor seres. A. Taylor Seres Approxmaton of Sne and Cosne Functons The Taylor expansons of sne and cosne of an angle - are gven by sn = 3! ! 1 5 cos = 1 2! ! 1 4 We have estmated the maxmum error n the evaluaton of sne and cosne functons for dfferent order of approxmatons. Therefore, we choose thrd order of approxmaton for Taylor s expanson of sne and cosne functons. 1) Representaton of Mcro-Rotatons Usng Taylor Seres Approxmaton: Here, we study the mpact of orders of approxmaton of Taylor seres of sne and cosne functons on the mcro-rotatons to be used n CORDIC coordnate calculaton. Both theoretcal and smulaton results are dscussed to confrm the approprate selecton of the order of approxmaton. Usng dfferent orders of approxmaton of sne and cosne functons n (2), we can have x +1 = 1 α 2 x 2! α 3 y 3! y +1 = 1 α 2 y + α 3 (1a) 2! x +1 = 1 α 2 2! + α 4 x 4! α 3 3! y +1 = 1 α 2 4 y + α 3 + α 2! 4! 4 x +1 = 1 α 2 2! + α 4! x α 3 y +1 = 1 α 2 4 y + α 3 + α 2! 4! 3! x 3! x y 3! + α 5 5! + α 5 3! 5! x y (1b) (1c) 15 Page

5 Area Tme Effcent Scalng Free Rotaton Mode Cordc Usng Crcular Trajectory x +1 = 1 α 2 2! + α 4 4! α 6 x 6! α 3 3! + α 5 5! y +1 = 1 α 2 2! + α 4 4! α 6 y 6! + α 3 3! + α 5 x 5! y (1d) y +1 = 1 α 2 + α 4 α 6 2! 4! 6! x +1 = 1 α 2 2! + α 4 4! α 6 6! y + α α α 3! 5! 7! x x α α 3 3! + α 5 5! α 7 7! (1e) y We have used (1) for coordnate calculaton for evaluatng the best possble combnaton of approxmaton, whch satsfes the accuracy and RoC requrements, wth mnmum possble hardware. In Fg. 1, we have plotted the error n magntude estmated accordng to (1) (wth respect to the correspondng bult-n functons of MATLAB). Snce Errors resultng from the fve combnatons (1a) (1e) are of very small order, we prefer to use (1a) for coordnate calculaton wth mnmum complexty. 2) Expressons for Mcro-Rotatons Usng Taylor Seres Approxmaton and Factoral Approxmaton: Although, we fnd that we can use Taylor seres expanson wth thrd order of approxmaton (1a),wth desred accuracy and RoC requrement, (1a)cannot be used n the CORDIC shft-add teratons. To mplement (1a) by shft-add operatons, we need to approxmate the factoral terms by the power of 2values, replacng 3! by 2^3 n the (1a) we fnd x +1 y +1 = 1 2! 1 2. ( ) ( ) (1 2! 1. 2 ). x y (2) In Fg. 1 only, we have plotted the error n magntude usng the approxmated factoral values and exact factoral values after a CORDIC rotaton for ntal vector wth coordnates X=1 and Y=1. The maxmum percentage of error n sne and cosne values for both thrd order of approxmaton and factoral approxmaton s % and %, respectvely, wthn the permssble CORDIC elementary angles range of 0, 7π 88 dscussed. 3) Determnaton of the Basc-Shft for a Gven Order of Approxmaton of Taylor Seres Expanson: One can fnd that: 1) the order of approxmaton of Taylor seres expanson of sne and cosne functons determnes the basc-shft to be used for CORDIC teratons, and 2) the basc-shft of CORDIC mcro operaton determnes the range of convergence. The expressons for the basc-shfts, the frst elementary angle of rotaton 1 and RoCfor dfferent orders of approxmatons for dfferent word-length of mplementatons are as follows: Basc shft S= b log 2 n+1! (3a) (n+1) Where b s the word length ROC=n 1. 1 (3b) N s number of mcro rotatons 1 = 2 s (3c) The values n Table I are derved from (3). We fnd wth ncrease n the order of approxmaton, the basc-shft decreases, the frst elementary angle of rotaton ncreases and RoC s expanded. Very often ncluson of hgher order terms does not have any mpact on the accuracy for smaller word-lengths. The basc-shft for thrd order of approxmaton usng (3a), for 16-bt word-length s [2.854] Page

6 Area Tme Effcent Scalng Free Rotaton Mode Cordc Usng Crcular Trajectory TABLE I COMPARISION OF APPROXIMATION ORDERS VERSUS ROC FOR VARIOUS BIT WIDTHS BASED ON(7) Order of Approx. Basc shft Frst Elementary Angle (Radans) RoC for n 1 =4 (Radans) 16-bt 32-bt 16-bt 32-bt 16-bt 32-bt TABLE II BIT REPRESENTATION OF ELEMENTARY ANGLES AND CORRESPONDING SHIFTS Shft (s) Elementary angle(α ) Decmal 16-bt Hexa Decmal In ths paper, we propose a novel scalng-free CORDIC algorthm for area-tme effcent mplementaton of CORDIC wth adequate RoC. The proposed recursve archtecture has comparable or less area complexty wth other exstng scalng-free CORDIC algorthms. Moreover, no scale-factor multplcatons are requred for extendng the RoC to entre coordnate Space. Pseudo Code For Generatng The Mcro-Rotaton Sequence Input: angle to be rotated θ Begn M=Most sgnfcant-1locaton (θ ) If (M==15) then α=0.25 radans Shft,s = 2 and θ +1 = θ α else shft,s =16-M θ +1 = θ Wth θ [M]= 0 END V. Proposed Cordc Archtecture The block dagram for the proposed CORDIC archtecture s shown n Fg. below. It makes use of the same stage for all the teratons for the coordnate calculatons, as well as for the generaton of shft values. The structure of each stage (shown n Fg. 5) conssts of three computng blocks namely the 1) shft-value estmaton; 2) coordnate calculaton and 3) mcro-rotaton sequence generator. Fg.4. Recursve archtecture of the proposed CORDIC processor Page

7 Area Tme Effcent Scalng Free Rotaton Mode Cordc Usng Crcular Trajectory Fg. 5. Block dagram for the stage. The combnatoral crcut for generatng the mcro-rotaton sequence s shown n Fg. 4. The number of teratons requred n a CORDIC processor decdes the rollover count of the counter. The rollover count s seven for basc shft =2 and ten for basc-shft =3. Fg. 6. Combnatoral crcut for generatng the shft values. The expry of the counter sgnals the completon of a CORDIC operaton; dependng on ths sgnal, the multplexer ether loads a new data-set (rotaton angle, ntal value of and x and y ) to start a fresh CORDIC operaton, or recycles the output of the stage to begn a new teraton for the current CORDIC operaton. The nput and output regster fles act as latches for synchronzaton. Fg 7. Mcro-rotaton sequence generaton. VI. Fpga Implementaton The proposed archtecture s coded n Verlog and syntheszed usng Xlnx ISE9.2 to be mplemented n Xlnx Spartan 2E (XC2S200EPQ208-6) devce. Slce-delay-product of the proposed archtecture s compared wth the exstng CORDIC desgns n Table III; where, all desgns are syntheszed on 18 Page

8 Area Tme Effcent Scalng Free Rotaton Mode Cordc Usng Crcular Trajectory Xlnx Spartan 2E XC2S200E devce to mantan unformty. The power dsspaton of the proposed archtecture for dfferent clock frequences s estmated by Xlnx XPower tool. VII. Expermental Result And Dscusson TABLE III SLICE DELAY PRODUCT Slce-delay-product of the proposed archtecture s compared wth the exstng CORDIC desgns n Table III s suggested to reduce the number of teratons for low latency mplementaton. The proposed CORDIC processor has 17% lower slce-delay product for dentfyng the mcro-rotatons. VIII. Concluson The proposed algorthm provdes a scale-free soluton for realzng vector-rotatons usng CORDIC. The order of Taylor seres approxmaton s decded approprately by the proposed algorthm, not only to meet the accuracy requrement but also to attan adequate range of convergence. The generalzed mcro-rotaton selecton technque s suggested to reduce the number of teratons for low latency mplementaton. Moreover, a hgh speed most-sgnfcant-1 detecton scheme obvates the complex search algorthms for dentfyng the mcro-rotatons. The proposed CORDIC processor has 17% lower slce-delay product wth a penalty of about 13% ncreased slce consumpton on Xlnx Spartan 2E devce References [1] J. E. Volder, The CORDIC trgonometrc computng technque, IRE Trans. Electron. Comput. vol. EC-8, pp , Sep [2] K. Maharatna, A. S. Dhar, and S. Banerjee, A VLSI array archtecture for realzaton of DFT, DHT, DCT and DST, Sgnal Process., vol. 81, pp , [3] P. K. Meher, J.Walls, T.-B.Juang, K. Srdharan, and K. Maharatna, 50 years of CORDIC: Algorthms, archtectures and applcatons, IEEE Trans. Crcuts Syst. I, Reg. Papers, vol. 56, no. 9, pp , Sep [4] C. S. Wu and A. Y. Wu, Modfed vector rotatonal CORDIC (MVRCORDIC) algorthm and archtecture, IEEE Trans. Crcuts Syst. II, Exp. Brefs, vol. 48, no. 6, pp , Jun [5] C.-S.Wu, A.-Y.Wu, and C.-H. Ln, A hgh-performance/low-latency vector rotatonal CORDIC archtecture based on extended elementary angle set and trells-based searchng schemes, IEEE Trans. Crcuts Syst. II, Analog Dgt. Sgnal Process, vol. 50, no. 9, pp , Sep [6] Y. H. Hu and S. Naganathan, An angle recodng method for CORDIC algorthm mplementaton, IEEE Trans. Compute., vol. 42, no. 1, pp , Jan [7] M. G. B. Sumanasena, A scale factor correcton scheme for the CORDIC algorthm, IEEE Trans. Compute., vol. 57, no. 8, pp , Aug [8] J. Vllalba, T. Lang, and E. L. Zapata, Parallel compensaton of scale factor for the CORDIC algorthm, J. VLSI Sgnal Process. Syst., vol. 19, no. 3, pp , Aug [9] L. Vachhan, K. Srdharan, and P. K. Meher, Effcent CORDIC algorthms and archtectures for low area and hgh throughput mplementaton, IEEE Trans. Crcut Syst. II, Exp. Brefs, vol. 56, no. 1, pp ,Jan [10] K. Maharatna, S. Banerjee, E. Grass, M. Krstc, and A. Troya, Modfed vrtually scalng-free adaptve CORDIC rotator algorthm and archtecture, IEEE Trans. Crcuts Syst. Vdeo Technol., vol. 11, no. 11,pp , Nov [11] F. J. Jame, M. A. Sanchez, J. Hormgo, J. Vllalba, and E. L. Zapata Enhanced scalng-free CORDIC, IEEE Trans. Crcuts Syst. I, Reg. Papers, vol. 57, no. 7, pp , Jul [12] N. Takag, T. Asada, and S. Yajma, Redundant CORDIC methods wth a constant scale factor for sne and cosne computaton, IEEE Trans. on Computers, vol. 40, pp ,Sep [13] D. Tmmermann, H. Hahn, and B. Hostcka, Low latency tme CORDIC algorthms, IEEE Trans. on Computers, vol. 41, pp , Aug [14] J. Lee and T. Lang, Constant-factor redundant CORDIC for angle calculaton and rotaton, IEEE Trans. on Computers, vol. 41, pp , Aug [15] J. Duprat and J.-M. Muller, The CORDIC Algorthm: New results for Fast VLSI Implementaton, IEEE Transcaton on Computers, vol. 42, pp , Feb X. BIOGRAPHIES Logc Utlzaton Used Avalable Utlzaton Number of Slces % Number of Slce Flp Flops % Number of 4 nput LUTs % Number of bonded IOBs % Number of GCLKs % N. Hma bndu 1 receved B.Tech degree n Electroncs & Communcaton Engneerng from IFET College of engneerng, vllupuram, TN n She s now M.tech scholar n VLSI Desgn n Sr Krshna Devaraya Engneerng college, Gooty, AP Page

9 Area Tme Effcent Scalng Free Rotaton Mode Cordc Usng Crcular Trajectory K.Geetha 2 receved B.Tech, M.Tech degree n Electroncs & Communcaton Engneerng. She s havng an experence of 10 years n the feld of teachng, presently workng as Assocate Professor n Sr Krshna Devaraya Engneerng College, Gooty, AP Page