Digit-Serial Architecture For VLSI Implementation of Delayed LMS FIR Adaptive Filters

Transcription

1 Dgt-Seral Archtecture For VSI Ipleetato of Delayed MS FIR Adaptve Flters Basat Kuar Mohaty Departet of Electrocs ad Coucato Egeerg Jaypee Isttute of Egeerg ad Techology A.B.Road, Raghogarh, Gua, Madhy Pradesh-4736 INDIA Idex Ters: Dgt-seral, systolc archtecture, FIR adaptve flter Abstract I ths paper, a geeralzed dgt-seral archtecture s preseted for effcet pleetato of DMS FIR adaptve flters. The proposed dgt-seral archtecture s hghly regular, odular, cell level systolc ad above all t s bt-level ppeled. The ppele s, however, cotrbute to the adaptato ad ore severe for large dgt sze pleetatos. The dgt sze effect o the saplg rate ad adaptato of the proposed dgt-seral adaptve syste has bee studed for varous word legth-sze pleetatos. We observed that, for a gve word legth sze pleetato, the dgt-sze ad the ppele levels for the proposed archtecture ca be chose selectvely to acheve the desred saplg rate ad perforace FIR adaptve flterg at u expedture of area-te coplexty.. Itroductos Adaptve dgtal flters (ADFs) are wdely used varous sgal-processg applcatos, such as, echo cacellatos, syste detfcatos, ose cacellatos ad chael equalzato etc. [-3]. May of these applcatos requred real-te perforace adaptve flterg order to acheve attractve results. Therefore, ADFs eed pleetato a VSI array processor. Sce, systolc archtecture are hghly aeable to VSI due to ts saller ad spler processg eleets (PEs), local-tercoectos, hgh level of ppelablty, a uber of systolc archtectures have bee suggested [4-6] the last decade for hgh throughput pleetato of DMS based FIR ADFs. However, these ppele archtectures [4-6] are suffered fro adaptato, whch s of the order of M ad very large for large tapsze ADFs. I these cases, the adaptato sgfcatly degrades the perforace of the adaptve syste. Polta [7] has suggested DMS algorth a odfed for for ppele pleetato of FIR ADFs wthout ay adaptato. I the subsequet years, Douglas ad Matsubara [8-9] separately have derved systolc archtectures for DMS ADFs usg the Polta s approach. However, these structures [8-9] requred a large aout of hardware copared to ther earler structures [4-6]. Recetly, Va et.al [] have used the covetoal tree ethod for reducg the adaptato covetoal DMS ADFs wthout spedg ay extra hardware. I ther approach, they suggested a optze tree level rule for realzg a u adaptato systolc archtecture for a covetoal DMS ADF. Most of these exstg word level systolc archtectures [4-6], [8-] are fully sutable for varous real te adaptve flterg applcatos, but they requred a large aout of slco area, coucatos ad I/O p-outs. Wag [] has take soe attepts for dervg a bt-seral archtecture for pleetato of DMS FIR ADFs. A bt seral archtecture requred less hardware, coucatos ad p-outs copared to ts word level couterparts. Most portatly, a bt-seral DMS FIR adaptve syste requred a sall adaptato []. However, the throughput rate of a bt-seral syste s very slow copared to ts word level couterparts as the forer oe process oly oe bt oe clock cycle. Thus, presetly we have both word ad bt-seral archtectures, oe costra wth cost ad other wth speed. Dgt-seral archtectures are offers a better trade-off betwee speed ad hardware cost copared to ts word ad bt-level couterpart [3]. I a clock cycle, a dgt-seral archtecture process ore tha oe bt (depedg o the dgt sze). Adjustg the dgt sze the processg rate for dgt seral archtecture ca be set flexbly betwee the processg rate of a btseral ad word-level archtecture. Therefore, dgtseral archtectures are ore sutable for those applcatos for whch, bt-seral archtectures are too slow ad word level archtecture are too fast ad expesve. Dgt-seral archtectures ca be obtaed usg Hartley s foldg ad Parh s ufoldg techque[-3]. However, these archtectures always egates sub-dgt level ppelg due to the exstece of carry feedforward loop. Recetly, Aggou et.al [4-5] have suggested a dgt-seral ultpler based o

2 radx- ( s the dgt sze) arthetc, whch offers subdgt level ppelg. Keepg these facts vew, the preset work we tred to explore a dgt-seral pleetato of a DMS FIR ADFs to scale dow the costrats that exst the word ad bt-seral archtectures. The paper s orgazed as follows: Matheatcal forulatos for dgt-seral pleetato of DMS ADFs are gve Secto. The proposed dgt-seral archtecture for DMS FIR ADF s preseted Secto 3 ad ts perforace s evaluated Secto 4. The paper eds wth soe cocludg rearks Secto 5.. Matheatcal forulatos for dgtseral pleetato of DMS FIR adaptve flters The DMS algorth for updatg of a M-tap FIR adaptve flter coeffcets s gve as: h + = h + µ e -D X -D () e = d - y () y = X T h (3) where, X = [ x, x -, x -,., x M- ] T s the put vector, h = [ h, h,, h M- ] s the weght vector of the M-tap FIR flter durg the te stat, d = desred respose e = estated error µ = adaptato step-sze D = adaptato, For dgt-seral pleetato, the flter weghts h, adaptato step-sze µ, ad the saples of the sequece x, d ca be expressed dgts. Where, a dgt s of bt sze. Here we assue that s a dvsor of word legth W.e. W=. Based o radx - algorth [4], x, d ad h are expressed dgt for as: x = d = h = µ = x d = h = (4a) (4b) (4c) (4d) µ et, the product of two uber x ad h s represeted by P Thus, P = x. h, = ( + (5a) j ( x. h ) (5b) Usg the ew radx- algorth [5] equato (5b) ay be expressed as: P = ( + [ j j ( x h ) + ( x h ) ] (5c) Equato (5c), ay further be expressed by the followg recursve relatos gve eq. (5d-5g) P = k k k [( h x ) + S ] (5d) k = SD SD k S k j k j j k j = [( h x ) + ( h. x ) ] (5e) SD Further, S k = S k- j j k j +[( h. x ) SD + ( h x ) ] (5f) Where, S k = for k k x = for k < h k, = for k < The flter output of a adaptve syste ca be expressed as: y M = P, = where, P, = h,.x - (6) As requred fxed-pot pleetato, the flter outputs of the adaptve syste are quatzed to dgts by trucatg ts SDs. The quatzed verso of y are expressed as: y = y (7) + Sce, the weght creet ter volves two back-toback ultplcatos (eq.), we perfor these two ultplcatos two steps as: W+, = VD. xd () V D = µ. e D () Usg eq. (4d), eq. () ay otherwse be wrtte as: ( + j V D = [ µ e ] () The saples of the sequece V -D are also quatzed to dgt fro ts dgt sze ad the quatzed saples are expressed as:

3 + V D = VD (3) V I fxed-pot pleetato, the saples of D ca be used for coputg the weght creet ter W +, for updatg the adaptve syste. The weght creet ter ca be coputed dgt-serally usg the followg eqs: W+, = V D. x (4) D ( + W = [ V D. x ] (5), + j D The weght creet ter W +, oce aga quatzed to dgt fro ts dgt sze ad the quatzed W + saples (, ) are used for updatg the adaptve syste. Thus, + W +, = W+, (6) W +, W, + W +, = (7) 3. Dgt-seral archtecture for DMS adaptve FIR flters I ths the proposed dgt-seral archtecture s preseted for systolc VSI pleetato of DMS FIR adaptve flters. The proposed dgt-seral archtecture s show Fg. for M=4, =4 ad tree level p=. However, slar archtectures ca be derved for ay dgt sze pleetatos. The structure uses two dfferet type of processg odules: ad (µ), where uses a te-varat dgt-seral ultpler (DSM) ad (µ) a te-varat DSM. A processg odule, bascally perfor the flterg coputato. However, the propose schee, t also perfors coputato for obtag the weght creet ter ( W,) fro the teredate ter V -D ad ed put saples x -D. The weght creet ter subsequetly update the flter weghts of the. A, therefore, uses separate DSMs (DSM ad DSM) for coputg flter coputato ad weght creet ter. Both these coputatos are partaly overlapped a. For exaple: the frst clock cycles of a th terato flter coputato s overlaped wth last clock cycles of (-)th terato weght update coputato ad the last clock cycles of th terato flter coputato s overlapped wth frst clock cycles of th terato weght update coputato. Thus, the flterg ad weght updatato of the proposed dgt-seral adaptve syste s schedule to be coplete clock cycle, where the durato of a clock cycle s the u crtcal perod of the DSM, whch s equal to the propagato of a -bt CA adder. The ppele s of the archtecture always result a large adaptato a dgt-seral adaptve syste, whch s early equal to the adaptato s of the exstg covesoal word-level archtectures [4-6]. Overcog the above dffcutes dgt-seral pleetato, we appled the recetly suggested optzed tree rule of Va et.al [] for dervg a dgt-seral archtecture wth low crtcal perod ad adaptato. Based o the optsed tree-rule, the tree level (p) s chose to be p= for a 4 tap-fir ADF. Thus, a 4-tap dgt-seral FIR ADF structure oly uses four, where a cotas four fter weghts (h,p +j, where =,,.M -, j =,,,..,P -, P=p ad M =M/P). Ppele latches ca be placed uforly across each tree-levels a ad betwee the s of the structure to achve u clock durato (T), whch ca be ade equals to the crtcal perod of the DSM. The output of the last s fed to (µ) for coputg the error sequece ad the teredate weght creet ter V -D. I a fxed-pot pleetato the flter output sequece y, teredate ter V -D ad the weght creet ter ( W,) are quatzed to dgts before they beg used by the coputg structure. 4. Throughput rate ad perforace easure Throughput rate: The proposed dgt-seral adaptve FIR syste (DS- ADF) s fully ppeled at bt-level ad ts crtcal perod s lted wth the propagato of a -bt CA adder (for 4 ), where s the dgt sze. The axu saplg rate that ca be supported by the proposed DS-ADF s, therefore, gve by F s =[/T], where T s the clock durato, whch s equal to the propagato of a -bt CA adder. The saplg rates (F s ) of the proposed dgt-seral syste are evaluated for varous dgt-sze (=,4,8,6) ad wordlegth sze (W =8,6,3,64) pleetatos to study the effect of word-legth ad dgt sze o ts throughput rate. I our evaluato schee, we have assued the propagato of a -bt FA, -put XOR gate, -put NAND gate, -bt CA adder, 4-bt CA adder, 8-bt CA adder, 6-bt CA adder, respectvely, (.6,.8,.34,.88, 3., 4.8, 6.4) s. Note that these are oly approxate values ad ot the 3

4 D x T CR TR [h,j ] Frst [h,4+j ] Secod [h,6+j ] (M -)th [h,+j ] M th [µ] V -α- e -α- Fg.: Systolc archtecture for dgt-seral pleetato of DMS FIR adaptve flters (For M=4,=4, p=) y -α d -α- actual oes. The actual value depeds o the choce of CMOS of techology. The saplg rates of the proposed DS-ADF are plotted agast dgt sze ad are show Fg. Adaptato : A DMS adaptve FIR syste s perforace always affected wth adaptato ad the aout of degradato s argal for sall adaptato. The proposed DS-ADF requres a sall adaptato ( 3( + δ ) + D + D = t ),where,δ ( < δ ), represets the ppele levels for processg a dgt of sze a DSM ad D t represet the s troduced for ppelg the tree levels a.the adaptato for the DS-ADF are evaluated for varous dgt sze (=,4,8,6) ad word-legth sze (W =8,6,3,64) pleetatos to study ts perforace behavor. The adaptato s are evaluated for a 4-tap FIR adaptve syste wth tree level p= ad the bt-ppele levels ( δ =,4,4,6), respectvely, for dgt sze (=,4,8,6). The values are plotted agast ad show Fg.3 Area-Te coplexty: The area-te (AT) coplexty also has bee evaluated for the proposed DS-ADF to easure ts VSI perforace. I our evaluato schee, we assue the VSI area as the hardware requred ( ters of CMOS trasstors) by the proposed structure ad the te (T) s ts u clockg perod. Here we assue the approxate CMOS trasstor cout for varous basc eleets are (-put AND, -put NAND, -put XOR, -bt FA, -bt latch, -bt eory, -bt NOT, - bt swtch, -bt CA, 4-bt CA, 8-bt CA, 6-bt CA), respectvely, (6,6,6,4,8,,,6,3,6,9.). Wth ths assupto, the approxate trasstor couts for a 4-tap DS-ADF are evaluated for varous dgt sze (=,4,8,6) ad word-legth sze (W =8,6,3,64) pleetatos. The correspodg AT paraeter are evaluated ad plotted agast (Fg.4). The curves show Fgs., 3, ad 4 ca be used for selectg the ost approprate dgt sze for the proposed DS- ADF to acheve the desred saplg rate at u adaptato wth lowest AT paraeter easure. The proposed DS-ADF s, therefore, provdes a batter trade-off betwee saplg rate, AT paraeter ad ts covergece rate copared to the exstg bt ad word-level ppele archtectures [] ad []. 5. Coclusos A geeralzed dgt-seral archtecture has bee preseted for systolc pleetato of DMS FIR adaptve flters. The proposed dgt-seral archtecture s bt-level ppeled, hghly regular, odular ad cell level systolc. Due to bt-level ppelg, the proposed oe requres a sall clockg perod ad offers a hgh throughput rate MHz order. The throughput rate of the proposed dgt-seral archtecture creases learly wth dgt. However, the adaptato also creases wth crease dgt sze. The effect of dgt sze o the adaptato ad saplg rate are also studed ad estated for varous word-legth sze pleetatos. The saplg rate ad adaptato of the extg bt-seral archtecture [] has bee evaluated for coparso purpose ad foud to be (3., 5.6, 7.8, 3.9) MHz, respectvely, for wordlegth sze (, 6, 3, 64). However, the adaptato alost reas sae ad t equal to 3. I the proposed case, saplg rate ca be acheved fro 6 to MHz wth adaptato varyg fro 3 to 6 (Fg ad 3) for varous dgt sze pleetatos. The curves show Fg,-5 are ca be used as characterstc curves for selectg ore approprate dgt sze for the proposed dgt-seral archtecture to acheve the desred saplg rate ad perforace adaptve flterg applcato at u expedture of AT paraeter. 4

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