Low Power Modulo 2 n +1 Adder Based on Carry Save Diminished-One Number System

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1 Amerca Joural of Appled Sceces 5 (4: 3-39, 8 ISSN Scece Publcatos Low Power Modulo + Adder Based o Carry Save Dmshed-Oe Number System Somayeh Tmarch, Omd Kavehe, ad Keva Nav Departmet of Electrcal ad Computer Egeerg, Shahd Behesht Uversty, Tehra, Ira Abstract: Modulo + adders fd great applcablty several applcatos cludg RNS mplemetatos. Ths paper presets a ew umber system called Carry Save Dmshed-oe for modulo + addto ad a ovel addto algorthm for ts operads. I ths paper, we also preset a ovel archtectures for desgg modulo + adders, based o parallel-prefx carry computato uts. CMOS mplemetatos reveal the superorty of the resultg adders agast prevously reported solutos terms of mplemetato area ad delay. Keywords: Modulo + addto, carry save dmshed-oe umber system, parallel-prefx adders, resdue umber system, computer arthmetc, VLSI crcuts. INTRODUCTION The Resdue Number System (RNS s a oweghted umber system [] that ca map large umbers to smaller resdues, wth ay eed for carry propagatos []. Arthmetc operatos lke addto, subtracto ad multplcato ca be performed o resdue dgts cocurretly ad depedetly. Thus, usg resdue arthmetc, would prcple, crease the speed of computatos [3, 4, 5]. RNS has show hgh effcecy realzg [6, 7, 8, specal purpose applcatos such as dgtal flters 9], mage processg [], RSA cryptography [] ad specfc applcatos for whch oly addtos, subtractos ad multplcatos are used ad the umber dyamc rage s specfc. Specal modul sets have bee used extesvely to reduce the hardware complexty the mplemetato of coverters ad arthmetc operatos [, 3]. Amog whch the trple modul set {,, + } have some beefts [4]. Because of operad legths of these modul, the operato delay s determed by the modulo + chael. Therefore, the desg of effcet modulo + adders s crtcal [5]. Modulo + operatos are used may applcatos such as DSP algorthms [6], Fermat Number Trasform for elmato of roud off errors covoluto computatos [7, 8, 9], cryptography [] ad pseudoradom umber geerato []. Modulo + adders are also utlzed as the last stage adder of modulo + multplers. I the last few years, several algorthms ad archtectures have bee proposed for desgg modulo + adders. These algorthms are based o two umber systems : To overcome the problem of (+-bt wde crcuts for the modulo + chael, the dmshed-oe umber system [7] has bee proposed. I ths [4, - system, effcet adders have bee reported 5]. But these adders eed a specal treatmet for zero operads. For ths problem, a ew umber represetato called Carry Save Dmshed-oe (CSD- s proposed ths paper. Wth ths system, the addto wth zero operad does t eed a specal treatmet, whch reduces the adder chp area. Modulo + adders ca be desged as a specal case of geeral modulo m adders. The most effcet crcuts for geeralzed modulo adders are reported [5, 6-8]. I [5], the proposed adder s more effcet tha the oes proposed by [6-8]. However, the correspodg structure [5] uses a 3- operad adder whch s elmated our method. I the paper, we derve a ew methodology for modulo + adder that leads to a parallel-prefx adder archtecture. Usg mplemetato a CMOS techology, we show that the proposed parallel-prefx desg methodology uses cosderably less chp area tha that reported [3] (dmshed-oe umber system ad less chp area ad propagato delay tha the approach reported [5] (ormal umber system. FOUNDATION Modulo + Reducto Bascs : Let A be a bt word ad A h (resp. A l the correspodg hgh (resp. low bt words: Correspodg Author: Somayeh Tmarch, Faculty of Electrcal ad Computer Egeerg, Shahd Behesht Uversty, Tehra, Ira, Tel: , Fax: , E-mal: s_tmarch@sbu.ac.r 3

2 A = A h + A l. A mod ( + = (A h + A l mod ( + = (A l -A h mod ( +. Therefore, the reducto modulo + s computed by subtractg the hgh -bt word from the low -bt word ad the codtoally addg + f the subtracto yelds a egatve result. Dmshed-Oe Number System: I the dmshedoe umber system, the umber A s represeted by A = A ad the value zero s treated separately,.e., t requres a addtoal zero dcato bt. I ths system, the ordary addto ca be mplemeted by a ed-aroud-carry parallel-prefx adder wth c = c [7, 5] : S' = (S- = (B- mod ( + = [(A'+ + (B'+ - ] mod ( + = (A' + B' + mod ( + = (A' + B' + c mod ( Algorthm : (Modulo + addeto dmshed- umber system: A umber dmshed-oe s represeted by + bts whch the (+ th bt s used to dcate. I [7], the modulo + addto algorthm has bee preseted for zero ad o zero operads: If the most sgfcat bt of oe added s, hbt the addto ad the other added s the sum (Fg.. If the msb of both addeds are, gore the msb, add the lsb s, complemet the carry ad add t to the lsb s of the sum. The modulo + adder Fg. ca be desged dfferet ways. To crease the modulo addto speed, the delay of carry computato should be mmzed. I may papers, parallel-prefx adders have bee proposed for ths purpose. Fg. : A( B( B (, A(, O( Modulo ( + Adder Am. J. Appled Sc., 5 (4: 3-39, 8 B(, A(, O (, O(, S(, A( The geeral desg of dmshed-oe modulo adder 33 Parallel-Prefx Adders: Parallel-prefx adders are usually used papers for speedg up the addto operato. They mmze the carry computato tme. I the prefx techque, puts x... x - x - ad a arbtrary assocatve operator are used to compute puts y = x o x o L o x for =, -. Thus, each put y depeds o all puts x j of same or lower rage (j=. I a bary addto, the carry propagato s a prefx problem. Prefx structures ca be represeted by usg a drect acyclc graph. The o operator o a par of ( g, p terms s usually represeted by a ode ad a carry computato ut s represeted as a tree structured tercoecto of such odes. Several tree structures have bee proposed [9, 3]. THE NEW CSD- NUMBER S STEM AND ITS MODULO + ADDITION ALGORITHM CSD- Number System: I the proposed method, we try to mprove the performace of modulo + arthmetc uts by usg a carry save codg. Table shows the ew represetato of umbers. Table : The CSD- codg for modulo + Rage Bt Represetato [, ]... As show table, ths represetato s composed of postos (dgts, wth two bts the frst posto ad - bts other oes. A umber X s represeted as below: X = x -... x x x' x? We call ths system carry save dmshed-oe. If X ( X = the x = ( x =. Whe we elmate ths bt from represetato, the remag bts are equal to dmshed-oe represetato of X. Also there are two bts the frst posto; therefore we have a carry save represetato. So we call ths system Carry Save Dmshed-oe (CSD-. The dfferece betwee CSD- ad dmshed-oe represetatos s that CSD-, the value of represeted umber s exactly equal to ts real value. I the dmshed-oe, each umber X s represeted by X = X. As show later, CSD- has a advatage over dmshed-oe that leads to a uque crcut for zero ad o zero operads. Therefore, the frst step of the dmshed-oe addto Algorthm o loger exsts wth CSD-. Aother beeft s that CSD-

3 s extedable to ay other modulo whe dmshedoe s oly defed for modulo +. CSD- Addto Algorthm: I ths secto, we preset the CSD- addto algorthm for modulo + (Algorthm. Algorthm : (CSD- addto: Ths algorthm s decomposed to steps. Step. The frst step s based o the followg theorem: Theorem : Let A ad B be two CSD- umb ers the rage [, +]. The, A + B + f A + B < A + B = + B otherwse Proof: A + B + B = B ( B ( + + = ( B f f B < otherwse Am. J. Appled Sc., 5 (4: 3-39, 8 + B < otherwse ( Whe A + B < the A B + = A + B + (3 ( + The maxmal value of (3 s. I CSD-, ths value ca be represeted by (+ bts postos. I other words, the put carry resultg from B + s. Thus, the term (3 s trasformed to: A + B + = A + B + Sce A, B [, ], the secod case of equato ( leads to the followg equaltes: A + B + < So, B = B = B Therefore, from ( we get: B + f B < A + B = + (4 B otherwse The equato (4 les the mpact of the put carry of (B-. I the CSD- umber system, ths carry s produced whe the sum s larger tha. The carry geerato dcates that the sum s equal or greater tha the modulo. Let assume C s the put carry of (B-. Thus the carry of (B- wll be geerated whe: 34 ( c = '' B + A + B + B > + (5 Thus, f the sum of two umbers s greater tha the modulo, the put carry of (B- s ad the sum s correct accordg to theorem : there s o eed to cremet the result. The put carry s zero the followg cases: c = '' B < + ( ( ( (6 B < + A + B + A + B = + I codto (, sce B s less tha the modulo, the put carry of (B- s. Accordg to equato (4, the sum should be cremeted the secod stage. Therefore from (4, (5 ad ( we have: f B < + or B > + the: S = B mod + = B + c (7 ( ( ( But codto ( of equato (6, whe B = +, equato (7 leads to S =, whch s ot true. To correct ths case, we troduce step of Algorthm that wll be preseted later. I our method, (B- s computed wth ay extra hardware ad oly by gorg a above sum. As metoed earler, f A thea = ; thus (B- wll be acheved by elmatg a. If A = the B wll be computed by removg a. I ths case, we have always c = '' ad the sum wll be cremeted accordg to equato (7. But cremetg should t be doe to obta the correct result. The frst step of Algorthm reveals that a twostage combatoal crcut s requred for modulo addto (adder ad cremeter. The frst stage computes a termedate sum M. M = B f A a = ( ( M = B f A= a = Therefore, we adjust equato (7 as below: B mod + = M + c + a (8 ( ( M equato (8 s acheved by addto of A ad B excludg a. The rage of M s gve by theorem. Theorem : (The rage of M: M has a (+-dgt bary represetato CSD-,.e., M [, + ]. (Note that m = C ths theorem.

4 Am. J. Appled Sc., 5 (4: 3-39, 8 Proof: If A= the M=B=B. Sce B [, ] the the theorem s establshed. The stuato s the same f B=. If A ad B? the M = B. Sce AB, < +, A> ad B > the, + < A + B < ( + + ( + < M (9 The maxmal value of M s + whch ca be preseted by + bts or + dgts CSD- (for ths maxmal value, all bts are. I the secod stage, the least posbts of M s cremeted accordg to (8. Step : As descrbed before, f B + the theorem leads to equato (8. But f B = + the the correct put of S= should be produced. I ths case, A ad B are o zero ad M = B =. Accordg to theorem ad equato (8, f the msb of M, m = (C = the M should be cremeted the secod stage. Thus the fal put s +. I CSD-, each umb er s the rage of [, ] ad ca be represeted by dgts. Therefore the put carry ca be gored ad the put sum s that ca be corrected by vertg s. I the secod step of Algorthm, we troduce two methods to detect zero put ad to correct t. a The correct put zero occurs whe two puts are complemetary,.e. ther sum s equal to modulo +. Oe method to recogze complemetary umbers s the logcal AND of the puts of a XOR b (for ay except =. A smlar method has bee metoed [3]. b Aother method s based o the followg theorem. Theorem 3: (Complemetary of two puts: Two puts are complemetary whe (ad oly whe the put ad put carres of the cremeter are. Proof: o Frst, we prove that f A ad B are complemetary umbers, the put ad put carres of the cremeter are. Whe A ad B are complemetary, both of them are o zero. Therefore, M = B = ( + =. I CSD-, has dgts. Thus, c = c =. The put carry of the cremeter s c = c a =.. o The put carry of the cremeter s equvalet to the put carry of the followg addto: S = A + B + = A + B = + ( Obvously, the put carry s. Now we prove that f put ad put carres of the cremeter are the A ad B are complemetary umbers. If c = the( c. a =. Therefore A adc =. I other words, M = B ad we have: M = B B + ( The put carry of the cremeter s whe the sum s equal or more tha +. That s: B + + A + B + ( ( Equatos ( ad ( are smultaeous verfed whe B = +, whch shows that A ad B are complemetary. Method (a has bee used [3]. However the method (b for zero detecto ad correcto cosumes less area tha method (a. The, we mplemeted method (b. As descrbed earler ad accordg to example, s ca be trasformed to the codto of zero detecto. THE PROPOSEH CSD- PARALLEL-PREFIX ADDER (CSD-PP Oe way for mplemetg the CSD-PP adder s based o the adder archtecture of Fg.. But stead of havg a dedcated sgle stage for reeterg the carry, [3] has proposed to perform carry recrculato at each exstg prefx level. The, there s o eed for the extra carry cremet stage. As a result, a dedcated CSD-PP adder archtecture s derved wth oe less prefx level compared to those derved from Fg. archtecture. I the CSD- system, t requres several modfcatos. These modfcatos wll be troduced by the 3 followg theorems. Theorem 4: Let assume that ( GP, = ( P ab, G, ad G ad P a, b, wth a > b, are respectvely the group geerate ad propagate sgals for the group a, a-, a-,..., b-, b, computed by: ( G P = ( g, p o ( g, p o L ( g, p a, b, a, b a a a a o b b 35

5 Am. J. Appled Sc., 5 (4: 3-39, 8 I our case, whch the reeterg carry s gve by the expresso a G, the carres addto modulo + are equal to G, where c of the G s computed by the prefx equatos: ( G, P = ( G, P = ( G, P o ( a G,, P, f Proof: ( G, P = ( G, P o ( G a, P = ( G + P ( G, + P, G a, P = ( G + P G, ( P, + G a, P = ( G + P G, P, a + P G, G a, P = ( G + P G, a + P G, G a, P = ( G + P G, a, P P, = ( G + P G, a, P, = ( G, P o ( G a, P,, Theorem 5 wll derve expressos leadg to faster crcuts. Theorem 5: Defg p = p a leads to ( G, P = ( g, p o L o ( g, p o ( G,, P, Proof: ( G, P = ( g, p o L o ( g, p o ( G, a, P, ( g + p g + L + p p L p p G, a =, ( p p L p p P Whe computg, G, oly the last term cludes p ad a. Therefore, we ca defe p = p a ad replace p by ( G, P = ( g, p o L o ( g, p o ( G,, P, ( g ( p g L p p L p pg, =, p p L p pp, The fal P are ever used ad the termedate p ( do t have p. The above equatos are thus correct. P I several cases, the equatos ( requre more tha log prefx levels for ther mplemetato. These equatos ca be trasformed to equvalet oes that ca be mplemeted wth log prefx levels. The requred trasformato uses Theorem of [3], as well as the Theorem 6 that wll be troduced below. Theorem of [3] says that, ( g, p o ( G, P = ( p, g, ( G, P Ths mples that a carry equal to the geerate term whch s expressed by a prefx equato of the form g, p o GP, s also equal to the geerate term of a ( ( equato of the form ( pg,,( GP,. The above formula s true whe g p = p. The followg theorem s also requred to derve the term that has the form ( ( ( prefx otato: g p o G, P ( p, g, G, P, = Theorem 6: If ( G, P ( g, p ( GP, x x = o ad ( Gy, Py = ( p, g,( GP, theg x = G y. Proof: Frst, we proof the followg expresso: g p = ( g + p = a + ( a + a ( a + a = a + a = p = a + Usg ths formula, we get: g + p G = ( g + p G = ( g ( p + G (3 = ( g p + g G = ( p + g G The carry equatos resultg from theorem of [3] ad theorem 6 ca be mplemeted by a prefx structure that has log levels. As metoed earler, we use the modfcatos troduced by theorems 4 to 6. Our proposed adder s smlar to [3] modulo adder archtecture but ts frst cells of preprocessg ad post processg stages are desged dfferetly. I the CSD- umber system, f x = the x =. Ths s a specal property of CSD-. Usg ths property to smplfy truth tables of these two cells leads to the followg equatos: s = a + a = a ( b p = p a = a b + a b g = a b s = s c + s s c 36

6 Am. J. Appled Sc., 5 (4: 3-39, 8 Theorem 3 s used for the detecto ad geerato of a correct zero. The term r dcates the codto of theorem 3: G. a c = = c = r h. c + g = ( G. a (. h c g = c. c =. + RESULTS AND COMPARISONS I ths secto, we compare the proposed CSD-PP adder to those proposed [5] ad [3]. As prevously metoed, the archtecture proposed [3] performs those preseted [4] ad [5], ad the archtecture proposed [5] performs those preseted [6-8] terms of mplemetato area ad executo delay. Thus, the archtecture of [3] s the best dmshed-oe archtecture, ad the archtecture of [5] s the best archtecture usg ormal bary represetato. All archtectures were descrbed HSPICE ad mapped to the.8 mplemetato techology (.8 µm, Vdd=.8 v. We use VLSI mplemetatos ad a smple model to compare the proposed adder archtectures to those proposed [5] ad [3]. We use the otato PPREF for the dmshed-oe modulo 8 + adder proposed [3] ad TPP for the ormal bary oe [5]. The CSD-PP mplemetato for the modulo + adder s gve Fg.. Aalytcal Comparsos ad Results: Frst, we use the aalytcal model used [5] ad [3], uder the otato ut-gate model. Ths model assumes that each gate, except the exclusve-or gate, cs as oe elemetary gate for both area ad delay. A exclusve- OR gate cs for two elemetary gates for both area ad delay. Accordg ths model, the lateces of the modulo ad modulo - adders are equal to log + 3. The PPREF modulo adder has a executo latecy of log + 3. However, accordg to Fg., the overall delay of PPREF s the modulo adder latecy plus the multplexer delay. The multplexer s a -level crcut ut -gate model. The overall delay s log + 5. The TPP adder has a latecy equal to log + 6 ad the proposed CSD-PP adder has a latecy equal to log + 4. The CSD-PP archtecture s faster tha PPREF ad TPP. Therefore, the CSD-PP adder offers the fastest desgs reported the ope lterature. The CSD-PP adder has also the same prefx levels as the PPREF adder, wth requrg ay crcuts for treatg zero operads as show Fg., whch reduce both the executo tme ad the mplemetato area. Therefore, the proposed CSD-PP adders are more effcet tha the fastest modulo + adder whch hadle operads dmshed-oe represetato. The ormal bary system ca be easly coverted to the ormal bary RNS. The represetato of odd umbers CSD-PP adders s the same as TPP adders. Accordg to the ut-gate model, the hardware overheads of the fastest reported modulo ad modulo - adders are respectvely equal to.5 log + 5 ad 3 log + 5. The PPREF modulo adder has a area of 4.5 log However, accordg to Fg., the fal area of PPREF cludes the modulo adder area ad the area of crcut for the treatmet of zero operads. The zero operad crcut area s +5. Thus, the fal area s 4.5 log The area of the TPP adder s equal to 4.5 log ad the proposed CSD-PP adder area s equal to 4.5 log Real Comparsos ad Results: For evaluatg the speed, area ad power cosumpto effceces of each archtecture, every adder s mplemeted by CMOS techology. The obtaed results are lsted Table. As we ca see proposed archtecture leads to far faster mplemetatos tha that of [5] ad [3]. Ths s due to the fact that the archtecture of [5] requres a delay of oe CSA ut ad the desg of PPREF [3] uses some multplexers to treat zero operads. The proposed archtecture, o the other had, reles o a -operad addto ( adverse of TPP that adds two puts ad - ad requres uque crcut for zero ad o zero operads based o CSD- umber system. 37

7 Am. J. Appled Sc., 5 (4: 3-39, 8 b 7 a 7 b 6 a 6 b 5 a 5 b 4 a 4 b 3 a 3 b a b a bbaa s c 6 c 5 c 4 c 3 c c c c s 7 s 6 s 5 s 4 s 3 s s s a a s, s c s ( g, p ( p, g s s Fg. : Proposed modulo + parallel-prefx carry save dmshed-oe adder Table : Real Comparso Results Adder Archtecture Trasstor C Average Power Cosumpto (µw Delay (ps Power Delay Product (fj PPREF [3] TPP [5] CSD-PP Improvemet CSD-PP vs. PREF Improvemet CSD-PP vs. TPP > 9% < 7% > 45% > 6% >.7% > 3% > 58% > 67% Fally, we study power cosumpto of compared archtectures. The smulato results are show Table. It s obvous that the proposed CSD-PP adder has the lowest cosumpto of all. It mproves TPP ad PPREF power cosumptos above 3% ad 6% respectvely. CONCLUSIONS I ths paper, a ew umber system has bee preseted. Ths paper also presets a ew archtecture for modulo + adders that uses parallel-perfx carry computato uts based o metoed umber system. The proposed archtecture has better performace tha 38 the covetoal modulo + adders. The ma pots of the paper are summarzed below:. The specal treatmet requred for zero operads the dmshed-oe umber system has bee removed.. The proposed archtecture removes the 3-operad adder ssue the fastest modulo + adders wth the ormal bary system. 3. The proposed archtecture leads to the fastest reported modulo + adders, wth executo lateces close to the executo latecy of the fastest modulo ad modulo + adders, whch meas that the proposed archtecture s sutable for RNS applcatos.

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