FPGA Implementation of Sine and Cosine Generators Using the CORDIC Algorithm

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1 FPGA Implemetato of Se ad Cose Geerators Usg the CORDIC Algorthm Taya Vladmrova ad Has Tggeler Surrey Space Cetre Uversty of Surrey, Guldford, Surrey, GU 5XH Tel: +44() Fax: +44() Abstract: Ths paper s cocered wth FPGA mplemetato of CORDIC schemes for fast ad slco area effcet computato of the se ad cose fuctos. The results of theoretcal vestgato to redudat CORDIC are preseted. Summary of CORDIC sythess results based o Actel ad XILINX FPGAs s gve. Fally applcatos of CORDIC se ad cose geerators small satelltes are dscussed. Keywords: CORDIC, se, cose, FPGA, sythess, redudat sged-dgt system. 1. Itroducto The ame CORDIC stads for Coordate Rotato Dgtal Computer. Volder [Vold59] developed the uderlyg method of computg the rotato of a vector a Cartesa coordate system ad evaluatg the legth ad agle of a vector. The CORDIC method was later expaded for multplcato, dvso, logarthm, expoetal ad hyperbolc fuctos. The varous fucto computatos were summarsed to a ufed techque [Walt71]. The resultg vector z of the rotato of a vector [ x y ] T, by a agle θ Cartesa coordates ca be computed by the followg matrx operato [Prs98]: x cosθ sθ x = (1) y sθ cosθ y Usg the detty: cos θ = ta θ ad factorg out cos θ equato (1) ca be modfed as follows: x 1 1 taθ x = () y 1+ ta θ taθ 1 y I the CORDIC method, the rotato by a agle θ s mplemeted as a teratve process, cosstg of mcro-rotatos durg whch the tal vector s rotated by predetermed step agles α. Ay agle θ ca be represeted to a certa accuracy by a set of step agles α. Specfyg a drecto of rotato or sg σ, the sum of the step agles α approxmates a gve agle θ as follows: = = 1 θ, { 1,1 } σ α σ (3) 1

2 The sg of the dfferece betwee the agle θ ad the partal sum of step agles 1 θ σ α cotrols the sg j j σ of the step agles α. A auxlary varable z s j = troduced that cotas the accumulated partal sum of step agles ad s used to determe the sg of the ext mcro-rotato. To smplfy the computato of the matrx product gve by (), the step agles α are chose such that ta α represets a seres of powers of : ta = α, =, 1,,..., 1 (4) The CORDIC method ca be employed two dfferet modes, kow as the rotato mode ad the vectorg mode. I the rotato mode, the co-ordate compoets of a vector ad a agle of rotato are gve ad the co-ordate compoets of the orgal vector, after rotato through a gve agle, are computed. I the vectorg mode, the co-ordate compoets of a vector are gve ad the magtude ad agular argumet of the orgal vector are computed [Vold59]. The rotato mode of the CORDIC algorthm has three puts that are talsed to the co-ordate compoets of the vector x, y ad the agle of rotato z = θ ad s descrbed by the followg terato equatos: x + 1 = x yσ + 1 = y + xσ (5) + 1 = σ arcta y z z 1 f z < where σ = ad =,1,,..., 1 (6) + 1 f z The outputs of the rotato mode x, y ad z are gve by the followg expressos, x ad y beg the co-ordates of the rotated (by the agle θ ) vector: x = K x cos z y s ) y ( z = K ( y cos z + x s z z = 1 ) where K = 1+ (7) = A CORDIC mcro-rotato s ot a pure rotato but a rotato-exteso. The costat K, gve by (7), s referred to as a scale factor, ad represets the crease magtude of the vector durg the rotato process. Whe the umber of teratos/mcro-rotatos s fxed the scale factor s a costat approachg the value of as the umber of teratos goes to fty. The elemetary fuctos se ad cose ca be computed usg the rotato mode of the CORDIC algorthm f the tal vector s of ut legth ad s alged wth the abscssa. The computato of s θ ad cos θ s based o equatos (5) ad (6) wth put values x =, y ad z = θ. The outputs after teratos are as follows: 1 =

3 x = K x cosθ y sθ ) = K cosθ (8) ( ( y cosθ + x sθ ) K y = K = z = sθ A addtoal operato of dvso s requred to obta the values of s θ ad cosθ from (8) as a result of the crease magtude of the vector by the factor K durg rotato. However, sce the scale factor s a costat for a gve umber of teratos, the operato of dvso ca be elmated by settg the magtude of the tal vector to the recprocal value of the scale factor,.e. x = 1 K. I ths paper we cosder computato of se ad cose of a agle θ (rad), where θ s a -bt bary fracto ad satsfes θ π. We compute s θ ad cosθ dow to the -th bary posto. I secto dfferet approaches to CORDIC mplemetato are summarsed. Secto 3 s dedcated to fast CORDIC methods. Secto 4 dscusses a redudat adder for fast CORDIC mplemetato ad ts realsato XILINX XC4. Secto 5 presets CORDIC sythess results targetg Actel ad XILINX FPGAs ad usg dfferet sythess tools. Secto 6 dscusses two satellte applcatos of CORDIC se ad cose geerators. Fally secto 7 cotas cocludg remarks.. Approaches to CORDIC Hardware Implemetato The CORDIC algorthm ca be mplemeted hardware usg three approaches: a sequetal approach - the structure s ufolded tme, a parallel approach - the structure s ufolded space or a combato of the two. These three approaches ad the resultg structures are also referred to the lterature as teratve, cascaded ad cascaded fuso, respectvely. A sequetal CORDIC desg performs oe terato per clock cycle ad cossts of three -bt adders/subtractors, two sg extedg shfters, a look-up table (LUT) for the step agle costats ad a fte state mache. A parallel CORDIC desg s smlar to a array multpler structure cosstg of rows of adders/subtractors, wth hardwred shfts ad costats. Parallel CORDIC ca be mplemeted the form of purely combatoal arrays or ca be ppeled depedg o the sze of the desg ad the requested data rate. A combed CORDIC desg s based o a sequetal structure where the logc for several successve teratos s cascaded ad s executed wth oe clock cycle [Wag95]. The umber of fused successve terato stages determes the order of a combed CORDIC desg. Fgure 1 summarses the structures used hardware mplemetato of the CORDIC algorthm. Sce algebrac addto s the ma operato the CORDIC algorthm, the effcecy of the hardware mplemetato of the algorthm depeds sgfcatly o the type of adder used. Adders based o the covetoal two-dgt bary system have tme delay depedet o the bt legth ad the best case of fast herarchcal adder structures the tme delay for executo of oe terato s of logarthmc order O (log ) [Prs98]. The tme delay of the operato of addto ca be made depedet o the bt legth by usg redudat adders that accept operads 3

4 represeted redudat sged-dgt (RSD) bary system. Numbers RSD system are represeted usg a three-dgt set {, 1, 1} ad may have several RDS represetatos, hece the ame redudat. Fgure 1. CORDIC hardware mplemetatos Bt-seral ad bary adders have bee used sequetal CORDIC mplemetatos [Adr98], all types of adders have bee tred cascaded CORDIC desgs bt-seral adders, carry-save adders, bary adders, redudat adders, combatos of both bary ad redudat adders [Adr98, Tmm9]. Obvously, a combato of sequetal approach ad bt-seral adders wll result the slowest desg wth mmal area, parallel approach ad redudat adders the fastest desg wth maxmal area. A trade-off betwee area ad speed would determe the rght mplemetato approach for a gve applcato. 3. Redudat CORDIC Schemes The troducto of the RSD system to the teral computato of the CORDIC method s cosdered to be oe of the most effectve ways to accelerate the algorthm [Erce87, Taka91, Tmm9, Bake76]. Cascaded desgs of redudat CORDIC schemes have outperformed array mplemetatos of CORDIC based o carry-save adders accordg to a comparatve study of these methods [Tmm9]. However, the straghtforward applcato of the RSD represetato to the CORDIC algorthm gves rse to problems that compromse the effcecy of the algorthm, as follows: Coverters from s complemet represetato to RSD ad vce versa are requred. The coverso from s complemet to RSD s straghtforward, however the coverso from RSD to s complemet requres a extra addto operato over -bt. 4

5 The value of the drecto operator 1,, 1 sce t depeds o the sg of z that s represeted as a redudat. The sg evaluato of a redudat umber requres detecto of the sg of the most sgfcat ozero bary dgt ad the worst case eeds specto of all dgts whch s a very slow procedure. I redudat CORDIC o rotato-exteso takes place for some step agles sce zero s a vald choce for the drecto operator σ. Ths makes the scale σ s selected from the dgt set { } factor K operad depedet ad ot a costat value ay more. Two approaches have bee proposed to elmate the vared scale factor effect: the scale factor s calculated durg computato ad the fucto values are corrected wth t at the ed of the rotato process [Erce87] or the scale factor s compesated durg the terato process va troducto of specal teratos [Taka91, Tmm9]. A alteratve approach to evaluato of rotato operators σ s to predct ther values by decomposg the agle of rotato advace [Bake76]. A comparso of the latecy of covetoal CORDIC ad dfferet modfcatos of redudat CORDIC has bee carred out wth all desgs beg of array type [Marx99]. The latecy of the desgs expressed as a fucto of the bt-legth s gve Table 1 [Marx99], where τ - delay of a full adder; τ (log ) - the upper boud of a -bt o-redudat fast addto; δ - delay of a redudat adder, depedet of the bt-legth; m - a arbtrary teger the correctg method [Taka91] where a correcto terato s performed every m -th step. The termato algorthm orgally proposed by [Che7] allows quttg the terato process as early as possble, modfed Booth ecodg ca be used for the same purpose [Tmm9]. Table 1. Latecy expressos of CORDIC mplemetatos Name No-redudat method Double rotato method [Taka91] Correctg method [Taka91] Predcto method [Tmm9] Predcto wth termato method [Tmm9] Latecy expresso as a fucto of the bt legth τ log τ + δ + τ log ( ( + 1) m )( τ + δ ) + ( ( + 1) m + log ) ( τ + δ ) log3 1 log τ log δ + τ + log3(( + 1) 1 log + τ log δ log( ) δ ( + 1) + τ + Fgure [Marx99] shows graphcally the latecy of the CORDIC mplemetatos usg estmated delays for XC4XL ad a rato r δ τ =. It suggests that a predcto techque combed wth a termato method [Tmm9] mght lead to a fastest FPGA mplemetato. 5

6 Fgure. Estmated latecy of CORDIC mplemetatos XC4XL 4. Redudat Adder Implemetato I RSD represetato, a umber Y ca be vewed as the dfferece betwee two * ** postve bary umbers Y ad Y as follows: * ** Y = y = ( y y ) = = * ** wth, { 1, } y (9) y The covetoal oe-bt full adder assumes postve weghts to all of ts three bary puts ad two bary outputs. Such adders ca be geeralsed to four types of adder cells by mposg postve ad egatve weghts to the bary put/output termals [Hwa79]. The addto of two redudat sged-dgt umbers Y ad Z ca be performed by cascadg two levels of geeralsed full adders of types 1 ad as show Fgure 3. The ma drawback of ths computato scheme wth two umbers redudat form s the amout of hardware, whch s twce that the carry-save case [Vad9]. Fgure 3. Redudat sged dgt adder [Vad9] 6

7 The rpple-carry adder ad the redudat sg-dgt adder have bee mplemeted XILINX 41XL ad compared terms of speed ad area [Marx99]. The rpplecarry adder uses the XILINX dedcated carry logc ad takes.5 cofgurable logc blocks (CLBs) per bt. The smallest redudat adder that has bee acheved XILINX 41XL requres two CLBs per bt. Fgure 4 [Marx99] llustrates the mappg for the mmal area redudat adder, where S1_geerator comprses the * logc that geerates the S output ad Sa_geerator comprses the logc that 1 ( + 1) Fgure 4. A mmum-area mappg of a redudat adder oto XC41XL ** geerates the S output. The latecy results are show Fgure 5 [Marx99], where the rpple-carry adder s referred to as RCA ad the redudat adder s referred to as ISDA. As ca be see from Fgure 5, the delay of the rpple-carry adder s early equvalet to the delay of the redudat adder for bt-legths below 16 bts, however, for bt-legth above 3 bts the redudat adder gves sgfcat ga performace. Fgure 5. Latecy comparso betwee a rpple-carry adder ad a redudat adder XILINX 41XL. 7

8 5. Expermetal Results We have mplemeted teratve ad cascaded se ad cose CORDIC-based geerators Actel ad XILINX FPGAs usg fast bary adders. The umber of the teratos all desgs was equal to the bt-legth. The bt-legths used were 1, 14, 16, 4 ad 3 bt for the teratve desgs ad 1, 14 ad 16 bt for the cascaded desgs. All of the cascaded desgs were o-ppeled. Redudat CORDIC desgs have ot bee attempted vew of the fdgs about fourfold area crease ad o sgfcat performace ga for bt-legths below 3 bts secto 4 above. Sythess results terms of module cout ad speed are summarsed Table 3 ad 4 where results for both area ad delay optmsed desgs are preseted. Four dfferet sythess tools have bee used Actmap 3.5.4, Syplfy 5.1.4, Spectrum 5.69 ad XILINX Foudato Seres Express 1.5. The speed estmates the two rghtmost colums of the tables are based o back-aotated delays ad dcate the value of the maxmal data rate acheved ad the maxmal clock frequecy. The expermetal results show that module cout ad operatg speed deped sgfcatly o the used sythess tool. The Actel-based desgs are faster tha the XILINX-based oes, however the Actel FPGAs are ot dese eough to accommodate cascaded desgs wth bt-legths hgher tha 16 bts. A 3-bt 1.9 Msps teratve se/cose geerator ca be mplemeted a small FPGA (Actel SX16-3). The most area-cosumg compoet of the teratve desgs s the sg extedg Barrel shfter, shftg over programmable shft-wdth, further optmsato should focus o more area-ecoomcal Barrel shfter desg. A 16-bt cascaded desg s ot possble to be ftted a XC41XL devce, ths s ot surprsg, the parallel mplemetato approach s a trade-off of area for speed where the area crease s of quadratc order wth respect to the bt-legth O ( ). A 1-bt o-ppeled cascaded CORDIC rus at.3 Msps (Actel SX16-3) - ths performace s comparable wth the performace of a 1-bt look-up table accordg to our LUT sythess results preseted Table 5. Table 3. Summary of CORDIC sythess results based o ACTEL FPGAs. Desgs A54SX16-3 Legth Actmap bts Area/Delay 4 Syplfy Area/Delay 4 Spectrum Area/Delay 4 Speed Data rate Frequecy s Msps MHz Iteratve 1 4/574 37/ / Iteratve / /414 48/ Iteratve /958 44/46 51/ Iteratve 4 117/ /77 995/ Iteratve / /1 1419/ Cascaded / / / Cascaded / / / Cascaded / / /

9 Table 4. Summary of CORDIC sythess results based o XILINX FPGAs Desg Legth Foudato 7 bts Express 1.5 Area/Delay Target Devce Speed Data rate Frequecy s Msps MHz Iteratve 1 16/139 XC41XL Iteratve /145 XC41XL Iteratve 16 16/178 XC41XL Iteratve 4 317/376 XC46XL Iteratve 3 56/66 XC46XL Cascaded 1 1/1 XC41XL Cascaded 14 88/88 XC41XL Cascaded /378 XC46XL Table 5. LUT sythess results Desg A54SX16-3 Legth Actmap bts Area/Delay 4 Syplfy Area/Delay 4 Speed s Frequecy MHz LUT 1 513/ / LUT / / Note 1: All sythess tools operated a "push-butto" fasho wth maxmum optmsato eabled were avalable. Note : Speed estmate based o Vtal smulato usg typcal operatg codtos. Note 3: Estmate frequecy gve by Syplfy Note 4: All module cout gve by Place ad Route software. Note 5: Actel Netlst Selected Note 6: Syplfy Netlst Selected Note 7: Foudato Express buld Note 8: ---- Sythess results ot avalable 6. Applcato Two applcatos of CORDIC se/cose geerators satellte data processg systems have bee vestgated atttude determato ad drect dgtal sythess. The Earth s Magetc Feld s a very computatoally tesve procedure satellte atttude determato ad s usually mplemeted software. A hardware structure based o CORDIC modules has bee proposed [Vlac99] for the calculato of the Legedre polyomals - the frst step of the teratoal geomagetc referece feld (IGRF) model [Wert85]. It cossts of four blocks comprsg CORDIC modules for se/cose as well as other fuctos ad a cotrol block. The delay of the hardware structure was estmated based o a 3-bt teratve CORDIC module mplemeted XC485XL. It was compared wth the delay of a C-program rug o a Petum 333 MHz computer for fve dfferet values of the costats m ad l. The 9

10 mprovemet speed was 44% for m = l = 1, 37% for m = l = 15, 3% for m = l =, 8% for m = l = 5 ad 3% for m = l = 36 [Vlac99]. Drect dgtal sythess (DDS) geerates a ew frequecy based upo a orgal referece frequecy. Vrtually all DDS archtectures clude a lookup table that performs a se computato fucto for geeratg susodal output sgals. For comparso purposes we have desged ad sythessed a LUT that s a mproved verso of the modfed Sutherlad archtecture [Vak96] (Table 5). It ca be see that a 1-bt cascaded o-ppeled CORDIC (Table 3) acheves the same data rate of Msps as the 1-bt mproved LUT desg. However, addto to that the CORDIC desg provdes both fuctos se ad cose at the same tme ad also ts speed ca be accelerated further f ppelg s troduced to reach a data rate of about 5 Msps. 7. Coclusos Ths paper presets theoretcal ad practcal aspects of mplemetg se/cose CORDIC-based geerators FPGAs. The ma results ca be summarsed as follows: A trade-off speed/area wll determe the rght structural approach to CORDIC FPGA mplemetato for a applcato. A 3-bt 1.9 Msps teratve CORDIC ca be mplemeted a small FPGA (Actel SX16-3). A 1-bt o-ppeled cascaded CORDIC rus at.3 Msps (Actel SX16-3) that s comparable to a LUT. Module cout ad operatg speed deped sgfcatly o the used sythess tool. Curret rad-tolerat FPGAs are ot dese eough for the cascaded ad redudat approaches. Smulato has show that the redudat adder ca mprove the effcecy of CORDIC FPGA mplemetatos for bt-legths hgher tha 3-bt. 8. Refereces [Adr98] R.Adraka. A Survey of CORDIC Algorthms for FPGA Based Computers Proc. Of the 1998 CM/SIGDA Sxth Iteratoal Symposum o FPGAs, February 1998, Moterey, CA, pp [Bake76] P.W.Baker. Suggesto for a Bary Cose Geerator, IEEE Trasactos o Computers, February, 1975, pp [Che7] T.C.Che. Automatc Computato of Expoetals, Logarthms, Ratos ad Square Roots, IBM J. Res.Developmet, July, 1997, pp [Erce87] M.D.Ercegovac, T.Lag. Fast Cose/Se Implemetato Usg CORDIC Iteratos, IEEE Tras. O Comput., vol.4, 9, 1987, pp. -6 1

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