New Arithmetic Residue to Binary Converters
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1 IJCSES Iteratoal Joural of Computer Sceces ad Egeerg Systems, Vol., No.4, October 007 CSES Iteratoal c007 ISSN New Arthmetc Resdue to Bary Coerters Amr Sabbagh MOLAHOSSEINI ad Kea NAVI Departmet of Computer Egeerg, Islamc Azad Uersty, Scece ad Research Brach Tehra, Ira E-mal: Faculty of Electrcal ad Computer Egeerg, Shahd Behesht Uersty Tehra, Ira E-mal: Abstract The resdue umber system (RNS) s a carry-free umber system whch ca support hgh-speed ad parallel arthmetc. Two major ssues effcet desg of RNS systems are the modul set selecto ad the resdue to bary coerso. I ths paper, we preset two effcet resdue to bary coerters for the ew three-modul set {, +, }. Ths modul set cossts of parwse relately prme ad balaced modul, whch ca offer fast teral RNS processg ad effcet mplemeatato of the resdue to bary coerter. The proposed resdue to bary coerters are memoryless ad cosst of adders. I comparso wth other resdue to bary coerters for a three-modul set, the proposed coerters hae better area-tme complexty. Key words: Resdue to bary coerter, reerse coerter, resdue umber system (RNS), computer arthmetc.. Itroducto The resdue umber system (RNS) s a o-weghted umber system whch speeds up arthmetc operatos by ddg them to smaller parallel operatos. Sce the arthmetc operatos each modul are depedet of the others, there s o carry propagato amog them ad so RNS leads to carry-free addto, multplcato ad borrow-free subtracto []. RNS s oe of the most effecte techques for reducg the power dsspato VLSI systems desg []. Also RNS ca be effcetly realzed multple-alued logc (MVL) [3,4]. Some applcatos of the RNS are dgtal sgal processg (DS) [5,6], the RSA ecodg algorthm [7] ad dgtal commucato [8]. The archtecture of the RNS s aturally fault tolerat ad cosequetly, t s used for error detecto, error correcto ad fault tolerace [9,0]. The complexty as well as the effcecy of resdue to bary coerter s prmarly based o the proper selecto of the modul set ad the coerso algorthm. May dfferet modul sets hae bee suggested. Amog these, three-modul sets hae bee extesely estgated, such as {,, + }[,], {,, }[3,4], {,, }[5], { +, +, } [6] ad {,, + } [7]. The algorthms of resdue to bary coerso are maly based o Chese remader theorem (CRT) [], mxed-radx coerso (MRC) [] ad ew Chese remader theorems (New CRTs) [8]. I addto to these, oel coerso algorthms [9] whch are desged for some specal modul sets hae bee proposed. Amog these, New CRTs algorthms hae smple computatos whch ca be effcetly realzed hardware. I ths paper, frstly we proposed the ew three-modul set {, +, }. Ths modul set cotas balaced ad well-formed modul whch ca result effcet mplemetato of the resdue to bary coerter. The, we preset two effcet desgs of the resdue to bary coerter for these three-modul set based o New CRT. The proposed coerters hae better performace, compared to the other resdue to bary coerters for a three-modul set wth smlar dyamc rage, where the dyamc rage s defed terms of product of the modul. The rest of paper s orgazed as follows. I secto we troduce the ecessary backgroud. The resdue to bary coerters s preseted secto 3. Secto 4 makes comparsos ad secto 5 s cocluso.. Backgroud A resdue umber sytem s defed terms of a relately-prme modul set {,,, } that s gcd(, j )= for j. A weghted bary umber X ca be represeted as X=(x,x,,x ), where x = X mod = X, 0 x < () Such a represetato s uque for ay teger X the rage [0, M-], where M= s the dyamc rage of the modul set {, } []. Addto, subtracto ad multplcato o resdues ca be performed parallel wthout carry propagato. Hece, Mauscrpt receed July 5, 007. Mauscrpt resed September 30, 007.
2 96 IJCSES Iteratoal Joural of Computer Sceces ad Egeerg Systems, Vol. No.4, October 007 by coertg the arthmetc of large umbers to a set of the parallel arthmetc of smaller umbers, RNS represetato yelds sgfcat speed up. Bary to resdue coerso [0] s ery smple ad ca be mplemeted wth modular adders. Whe bary to resdue coerso of the eeded operads had fshed, arthmetc operatos o RNS umbers are performed parallel wthout carry-propagato betwee resdue dgts. Hece, RNS leads to carry-free, parallel ad hgh-speed arthmetc. It should be oted that each modulo of the modul set has ts ow arthmetc processor whch s cossts of a modulo adder, a modulo subtractor ad a modulo multpler. I order to use the result of arthmetc operatos outsde of RNS, the resulted RNS umber must be coerted to ts equalet weghted bary umber. The algorthms of resdue to bary coerso are maly based o CRT, MRC ad New CRTs. By CRT, the umber X s calculated from resdues by X = x N M = M M = M ad M () N = s the multplcate erse of M modulo. Usg the MRC, the umber X ca be computed by the equato X = a a + a + a (3) = 3 where a s are called the mxed-radx coeffcets ad they ca be obtaed from the resdues by a ((( x a ) a ) a ) = (4) > ad a =x.the MRC s a sequetal approach ad CRT requres large modulo operatos whch s ot sutable for effcet hardware mplemetato. By New CRT-I [], the umber X s calculated by k( x x ) + k ( x3 x) + X = x + (5) + k ( x x ) k = 3 k = k (6) = For a three-modul set {,, 3 }, the umber X ca be coerted from ts resdue represetato (x, x, x 3 ) by New CRT-I as follow X = x + k x x ) + k ( x x ) (7) ( 3 k (8) = k (9) = 3. Resdue to Bary Coerter I ths secto, New CRT-I s appled to dere a effcet resdue to bary coerso algorthm for the ew modul-set {, +, }. Frst, we must proe that ths modul set cludes parwse relately prme umbers. Theorem : The umbers, +, are parwse relately prme. roof: Baesd o Eucld's Theorem, we hae gcd(a,b)=gcd(b,a mod b) (0) where gcd(a,b) deotes the greatest commo dsor of a ad b. So we hae, gcd ( +, )= gcd (, )= () gcd (, )= gcd (, )= () gcd ( +, )= gcd (, )= (3) sce all the greatest commo dsors are equal to, these three umbers are parwse relately prme. roposto : The multplcate erse of modulo ( ) s k =. roof: by substtutg alues (8), we hae k = ( + )( ) = = (4) roposto : The multplcate erse of ( +) modulo ( ) s k =. roof: Sce +, by substtutg alues (9), we hae k = = ( ( + ) = = + ) = (5) Theorem : I the RNS defed by the three-modul set {, +, }, the weghted bary umber X ca be calculated from ts correspodg resdues (x, x, x 3 ) by X = x + ( x x ) + ( + )( x3 x ) (6) roof: By lettg =, = +, 3 = ad the alues of k, k from ropostos ad to (7), we hae X = x + ( x x) + ( + )( x3 x ) Example: Ge the modul set {, +, } where =3, the resdue umber (x, x, x 3 )=(,5,7) s coerted to ts equalet weghted umber as follows, by substtutg the resdues ad =3 to (6), we hae
3 New Arthmetc Resdue to Bary Coerters 97 X = + 83(3) + 6(7)() = By usg the followg propertes, Theorem s smplfed to reduce the hardware complexty. roperty : Modulo ( p ) multplcato of a resdue umber by k, where p ad k are poste tegers, s equalet to k bt crcular left shftg []. roperty : Modulo ( p ) of a egate umber s accomplshed by subtractg ths umber from ( p ). Ths s equalet to takg the oe's complemet of the umber []. Suppose that the resdues x, x ad x 3 hae bary represetato as follow x = ( x, x, x, x, 0 ) (7) x = ( x + x x 0 ) (8),,,x, 3 x3, x3, x3,x3, x = ( 0 ) (9) Equato (6) ca be rewrtte as X x Y (0) Y + + () = 3 = x = ( ) x 3 = ( + ) x3 Wth respect to the ropertes ad, we hae = x = x, x, x, = ( x, x, x, ) Sce =, equato (3) ca be rewrtte as = ( ) x = + where = x = x x,,,0 443 = x 0 00x 4 3 (03 00x x 4, = x = x = 3 x 4, x 4, x,0 443 Ad 3 s calculated by x,,, ) () (3) (4) (5) (6) (7) (8) 3 = ( = + ( x3, x3, x3, x3, ) = x3, x3, x3, x3, ) x 3 = ( + ) x 3 (9) Sce both least sgfcat () bts of (5) ad most sgfcat bts of (8) are 's, we ca use the followg ectors stead of ad = x, x, x,0 x, x,x,0 (30) = 33 (3) we kow that, + = 3 = = 0 (3) So, Y () ca be calculated by Y = (33) Hardware mplemetato of the proposed resdue to bary coerters for the modul set {, - +, - } are based o (0) ad (30) ad cosst of oe ()-bt carry sae adder (CSA) wth ed aroud carry (EAC) ad a modulo ( ) adder. Modulo ( ) adder ca be mplemeted wth dfferet methods. By usg a ()- bt oe's complemet adder for performg modulo ( ) addto, we obta a cost-effcet (CE) coerter. Oe's complemet adder s a carry propagate adder (CA) wth EAC. Istead of usg a oe's complemet adder, we ca use the method of [3]. I ths method, two ()-bt regular CA's are work parallel, oe wth a zero carry ad the other wth a oe carry-. The correct result s selected by a multplexer (MUX) based o the carry-out of the adder wth zero carry-. I ths case, we obta a speed-effcet (SE) coerter. It should be oted that, Sce x s a -bt umber, o computatoal hardware s eeded to compute x + Y (0). The desred result s the result of cocateatg x wth Y. The proposed mplemetatos of the resdue to bary coerter are show Fg.,.
4 98 IJCSES Iteratoal Joural of Computer Sceces ad Egeerg Systems, Vol. No.4, October 007 Fg. The proposed cost-effcet resdue to bary coerter Y + x 443 X Fg. The proposed speed-effcet resdue to bary coerter 4. Comparsos 3 ()-bt CSA wth EAC ()-bt oe's complemet adder ()-bt CA Y x Y + x 443 X 3 ()-bt CSA wth EAC 0 ()-bt CA 0 MUX Y x I ths secto, we ealuate the performace of the proposed resdue to bary coerters terms of hardware cost ad coerso delay. I (33), the three operads are added usg a ()-bt CSA wth EAC ad a modulo ( ) adder. Calculato of (7), (9) ad (30) rely o smply mapulatg the routg of the bts of the resdues ad oly () erter are used for perfomg the ersos of (30). Sce (7) has bts of 0's, of the full adders (FA's) CSA are reduced to half adders (HA's). Hece, the CSA wth EAC s cossts of () FA's ad HA's. The ()-bt oe's complemet adder has complexty of () FA's ad the delay of (44)t FA, where t FA deotes the delay of oe FA. Therefore, the total cost of the proposed cost-effcet resdue to bary coerter s +=(34) FA's ad HA's. The delay of a CSA s the same as that of a FA. So, the proposed cost-effcet coerter has a total delay of +44=(45)t FA. The proposed speed-effcet resdue to bary coerter used two ()-bt CA that work parallel. Therefore, the total cost of ths coerter s +44=(56) FA's ad HA's. Also t has the delay of +=(3)t FA. To erfy the performace of the proposed coerters, they hae to be compared wth other resdue to bary coerters for a three-modul set wth smlar dyamc rage. The closest three-modul set to the proposed modul set s the modul set {,, }. Three resdue to bary coerters for ths modul set hae bee preseted [5]. The frst oe s based o MRC ad the secod s based o CRT, both are adder based. But the thrd coerter uses ROM. Table shows the hardware requremets ad coerso delays of these coerters ad also the proposed coerters. It s clear from Table that the proposed speed-effcet coerter s faster tha all the coerters of [5] whle t requres less hardware tha the coerters [5]-CII ad [5]-CIII. Also the proposed cost-effcet coerter utlzes lower hardware tha the coerters of [5] ad also t s faster tha the coerter [5]-CI. It should be oted that for a same alue of, the proposed resdue to bary coerters support larger dyamc rage tha the resdue to bary coerters of [5]. 5. Coclusos I ths work, we troduced a ew three-modul set for RNS whch ca results effcet resdue to bary coerso. Also effcet resdue to bary coerters for the proposed modul set based o New CRT-I s preseted. Comparso wth other resdue to bary coerters show that the proposed coerters hae better performace. Table. Hardware requremets ad coerso delays of the resdue to bary coerters Coerter [5]-CI [5]-CII [5]-CIII roposed-ce roposed-se FA HA 3 OR/NOT XNOR Multplexer ROM Delay (65)t FA (7)t FA + t MUX (7)t FA + t MUX (45)t FA (3)t FA + t MUX
5 New Arthmetc Resdue to Bary Coerters 99 Refereces [] B. arham, Computer Arthmetc: Algorthms ad Hardware Desg, Oxford Uersty ress, 000. [] T. Stouratts ad V. alouras, Cosderg the alterates lowpower desg, IEEE Crcuts ad Deces, 00, pp [3] M. Hossezadeh, K. Na, S. Gorg, A New Modul Set for Resdue Number System: {r-, r-, r}, IEEE Iteratoal Coferece o Electrcal Egeerg, 007, pp. -6. [4] M. Hossezadeh ad K. Na, A New Modul Set for Resdue Number System Terary Valued Logc, Joural of Appled Sceces, ol. 7, o. 3, pp , 007. [5] R. Coway ad J. Nelso, Improed RNS FIR Flter Archtectures, IEEE Trasactos O Crcuts ad Systems II, ol. 5, o., 004, pp [6]. G. Feradez, et al., A RNS-Based Matrx-Vector- Multply FCT Archtecture for DCT Computato, IEEE Mdwest Symposum o Crcuts ad Systems, 000, pp [7] S. Ye, S. Km, S. Lm ad S. Moo, RSA Speedup wth Chese Remader Theorem Immue agast Hardware Fault Cryptaalyss, IEEE Trasactos O Computers, ol. 5, o. 4, 003, pp [8] J. Ramrez, et al., Fast RNS FL-Based Commucatos Receer Desg ad Implemetato", th It l Cof. Feld rogrammable Logc, 00, pp [9] E. Koshta ad K. Lee, A Resdue Arthmetc Exteso for Relable Scetfc Computato, IEEE Trasactos O Computers, ol. 46, o., pp. 9-38, 997. [0] L. L. Yag, ad L. Hazo, Redudat Resdue Number System Based Error Correcto Codes, IEEE Vehcular Techology Coferece, 00, ol. 3, pp [] W. K. Jeks ad B. J. Leo, The use of resdue umber systems the desg of fte mpulse respose dgtal flters, IEEE Tras. Crcuts Syst., ol. CAS-4, 977, pp [] Y. Wag, X. Sog, M. Aboulhamd ad H. She, Adder based resdue to bary umbers coerters for (-,, ), IEEE Tras. Sgal rocessg, ol. 50, o. 7, 00, pp [3] A. Hasat ad H. S. Abdel-Aty-Zohdy, Resdue-to-bary arthmetc coerter for the modul set (k, k-, k--), IEEE Tras. Crcuts Syst., ol. 45, 998, pp [4] W.Wag, M. N. S. Swamy, M. O. Ahmad, ad Y.Wag, A hgh-speed resdue-to-bary coerter ad a scheme of ts VLSI mplemetato, IEEE Tras. Crcuts Syst. II, ol. 47, 000, pp [5]. V. A. Moha, RNS-To-Bary Coerter for a New Three-Modul Set {,, }, IEEE Tras. Crcuts Syst.-II, ol. 54, o. 9, 007, pp [6] F. ourbgharaz ad H. M. Yasse, A sged-dgt archtecture for resdue to bary trasformato, IEEE Tras. Comput., ol. 46, 997, pp [7] A. Harr, K. Na, R. Rastegar, A ew hgh dyamc rage modul set wth effcet reerse coerter, Iteratoal Elseer Joural of Computers ad Mathematcs wth Applcatos, do:0.06/j.camwa , 007. [8] Y. Wag, Resdue-to-Bary Coerters Based o New Chese remader theorems, IEEE Tras. Crcuts Syst.- II, ol. 47, o. 3, 000, pp [9] M. Hossezadeh, A. Sabbagh, K. Na, A Fully arallel Reerse Coerter, Iteratoal Joural of Electrcal, Computer, ad Systems Egeerg, ol., o. 3, 007, pp [0] B. Gua ad E.V. Joes, Fast coerso betwee bary ad resdue umbers, Electrocs Letters, ol. 4, o. 9, 988, pp [] B. Cao, C. H. Chag ad T. Srkatha, A Effcet Reerse Coerter for the 4-Modul Set {-,,, } Based o the New Chese Remader Theorem, IEEE Tras. Crcuts Syst. I, ol. 50, o. 0, 003, pp [] A. A. Hasat, VLSI mplemetato of New Arthmetc Resdue to Bary decoders, IEEE Tras. VLSI Systems, ol.3, 005, pp [3] J. Mathew, D. Radhakrsha, T. Srkatha, Fast resdueto-bary coerter archtectures, IEEE, 4d Mdwest Symposum o Crcuts ad Systems, 000, pp [4] A. Harr, K. Na, R. Rastegar, A Smplfed Modulo Squarg Scheme for Resdue Number System, IEEE Iteratoal Coferece o Computer as a tool, 005, ol., pp [5] S. J. estrak, Desg of resdue geerators ad multoperad modular adders usg carry-sae adders, IEEE Tras. Comput., ol. 43, o., 994, pp [6] B. Cao, C. H. Chag ad T. Srkatha, Adder Based Resdue to Bary Coerters for a New Balaced 4-Mdul Set, 3rd Iteratoal Symposum o Image ad Sgal rocessg ad Aalyss, ol, pp , 003. [7] A. Sabbagh, K. Na, A Improed Resdue to Bary Coerter for the RNS wth ars of Cojugate Modul, Iteratoal Coferece o Electrcal Egeerg ad Iformatcs, 007, ol., pp [8] S. Tmarch, K. Na ad M. Hossezadeh, New Desg of RNS Subtractor for modulo, th IEEE Iteratoal Coferece o Iformato & Commucato Techologes: From Theory To Applcatos, 006.
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