A Novel Low Complexity Combinational RNS Multiplier Using Parallel Prefix Adder

Transcription

1 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): A Novel Low Complexty Combatoal RNS Multpler Usg Parallel Prex Adder Mohammad R. Reshadezhad, Farshad Kabr Sama Departmet o Computer egeerg, Uversty o Isaha, Isaha, Isaha , Ira Departmet o Electrcal ad Computer egeerg, Leja Brach, Islamc Azad Uversty, Isaha, Ira Abstract Modular multplcato plays a mportat role ecrypto. Oe o the ecrypto methods whch eed ast modular multplcato s RSA where large umbers are eeded to empower large modules. I such methods, order to show umbers, RNS s usually used wth multplcato as the core. Modulo + multplers are the prmtve computatoal logc compoets wdely used resdue arthmetc, dgtal sgal processg, aulttolerat ad cryptography. Here, two resdue umber system multplers are troduced, both based o classcatos o couples or trplets o put operads, whch results a low complexty RNS multpler. The rst modular multpler s a combatoal crcut whch eables parallel prex adder applcato modulo +. The secod modulo + multpler uses + partal product, each wth $$ bt wdth, costructed by utlzg a verted ed-aroud-carry, carry save adder (CSA) tree ad a parallel adder at the ed. The perormace ad ecetly o the proposed multplers are evaluated ad compared wth that o the earler astest modulo + multplers. The proposed multplers are cosderably aster ad more compact tha that o the hardware mplemetatos, whch make them a vable opto or ecet desgs. Keywords: Modular multpler, resdue umber systems (RNS), modulo + multpler, parallel prex adders, low complexty RNS multpler.. Itroducto A Resdue umber system s a o-weght umerc system [] whch has gaed mportace durg the last decade, because some o the mathematcal operatos ca be dvded to categores o sub-operatos based o RNS []. Addto, subtracto ad multplcato are perormed parallel o the resdues dstct desg uts (ote called chaels), avodg carry propagato amog resdues [3]. Thereore, arthmetc operatos such as, addto, subtracto ad multplcato ca be carred out more ecetly RNS tha covetoal twos complemet systems. That makes RNS a good caddate or mplemetg varety o applcatos [4] such as: dgtal Sgal Processg (DSP) or lterg, covolutos, FFT computato [5] [6], ault-tolerat computer systems [] [6] [7], commucato [8] ad cryptography [9]. A resdue umber system s a represeted by k teger modules m k-,, m m 0. A teger ecrypts a umber a remaders set wth respect to the prme umbers module. A teger varable x, s uquely represeted by (x k-,,x,x 0 ) where, x =x mod m or 0 k-, ad [α,β] s the dyamc rage o resdue umber, the cardalty o whch s M=β-α+. The modules are chose to be par-wse prme to each other order to maxmze the cardalty, such that M= m k-,,m,m 0. I RNS, mathematcal operatos are perormed o some small tegers cocurretly. Here a obvous advatage s that the carry does ot pass through modules. To compute a mathematcal operato o x ad y resdue umber system, we use a otato x y, where could be oe o the operatos lke, addto, subtracto or multplcato represeted by Eq. (): x y (x,,x, x ) (y,,y, y ) k 0 k 0 () z (z,,z, z ) ad, z (x y ) k 0 m Oe o the easest ways to perorm resdue multplcato s to use a pure table look-up structure where, each modulo m multpler ca be mplemeted through ROMs. Desgs adoptg ROM approaches are based o look up table, whch are excellet or smaller modules multplers; however, they occupy vast area as the umber o bts gets larger, thereore, the ROM sze creases expoetally as the umber o bts each operad creases [0] [] [] [3]. Aother approach desgg RNS multplers s to use adder-based multpler archtectures, whch have bee Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.

2 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): proposed [4] [5] [6] [7]. Hasat troduced a ecet modular multpler whch s sutable or deret module szes, medum ad large sze module partcularly [4]. DClaudo et al. preseted the pseudo-rns represetato [5]. Wrzyszcz et al. have troduced a archtecture talored to xed coecet [6]. Stourats et al. [7] preseted ull adder based sgle modulus archtecture or RNS multpler ad accumulator. The multplers preseted by Zmmerma [4] allow the use o Wallac-tree addto ad Booth recodg o partal products or speed-up. They also used parallel prex adders to mplemet ther ast ad smple ed-aroud carry adder or modulo ±. The dmshed- modulo + multpler proposed by Estathou et al. [5] uses a partal-product array together wth a CSA tree. They eeded +3 partal products ad treatmet o zero operads was ot dscussed. Vergos et al. [6] troduced a ew modulo + multpler archtecture or operads weghted represetato. Ther proposed multpler utlzes a total o + partal product. They used a verted ed-aroud-carry (ECA), carry-save adder tree ad a al parallel adder. I 007 aother RNS multpler by Vergos et al. was troduced. The aalytcal ad expermetal results preseted [7] show that the multplers proposed, outperorm the earler solutos o [4] [5] [6]. I ths artcle a backgroud o RNS multplers s revewed secto. I secto 3, the bases o RNS adders used RNS multpler archtecture are dscussed [3] [4] [5] [6] [7] [8]. The proposed multpler archtectures are preseted secto 4. Subsequetly, secto 5, the obtaed operatoal result s compared to the avalable results, ad ally the coclusos are draw secto 6.. Backgroud o RNS Multplers As metoed the troducto, a varety o RNS multplers are desged, lke table look-up multplers, dex trasorm multplers, quarter square multplers, ad array multplers. Each modulo m multpler ca be mplemeted by ROMs, whch employs look-up table ad s excellet or smaller modulo multpler, or a array o ull adders cells s used to mplemet the multpler, whch has a lear delay respect to the umber o bts each operad. The cocepts o RNS multplcato s to evaluate x y m ad elmate the subscrpt the aalyss ad terpret each resdue bt ts bary orm, through expressos or X ad Y as equatos: X x ad, Y y () The modular multplcato o umbers X ad Y ca be carred out through equato (3). where, X, Y, ad R are -bt resdues modulo M, ad x,y j {0,} represets the th ad j th bt o X ad Y, respectvely. I ths artcle a ovel VLSI mplemetato or calculato o resdue multplcato s troduced that allow the computato o the result by equato (4). R X Y m (4) Modular multplcatos are categorzed to two methods. I the Frst method, the multplcato o operads takes place completely ad the a reducto takes place o the al result. Ths method s called Reducto ater multplcato (RAM). I the secod method, the reducto s appled durg the multplcato steps, ad s called Reducto Durg Multplcato (RDM). Both methods ca be dvded to three deret classes based o the hardware mplemetato method used. Class Oe: these methods use some popular modules lke:, +, or - where s ether small or bg. To mplemet these kds o methods, logcal crcuts are ote used stead o ROMs. As a result, these methods are lmted to specc modules [3] [] [4] [9]. Class Two: these kds o Implemetatos are capable o workg wth ay modules but there backboe structure s based o ROM ad usually the logcal crcuts are ot appled such methods. The memory sze creases rapdly wth a crease. Cosequetly, ths method s ot a good choce or large modules [0] [] [3]. Class three: these types o archtectures are employed or average ad large modules, whch are usually hybrd ad use bary adders ad multplers together wth some ROMs small sze ad logcal elemets [4]. I ths artcle, we ocus o class oe ad chose modulo + to do the multplcato ad reducto. The multpler puts are categorzed as that o the Vassls et al. paper []. To get the al result we use adder troduced [8] order to optmze tme ad area.. Vassls s Multpler ( ) j M j M M R x y x y The orgazato o ths part s based o the resdue computg uts o the prevous reports [] [7] [0] []. Let us cosder a modulo-5 multpler wth the bt legth o 3 usg equato (3). Accordg to the sources above, the rst stage o the resdue multpler represets the ested addto o equato (3), whereas the secod ad the thrd part, s the reducto whch takes place o the (3) Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.

3 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): outer module o the rght sde o equato (3). Speccally, the secod stage alteratvely coverts ts put to a umber wth a resdue the same as modulo, m, that o 5, ad word legth o =3. Fally, the last stage, maps ts puts to d resdue va a codtoal addto; thereore, the thrd stage s mplemeted through equato (5): Y Y m Y = (5) Y m Y m The rst ma codto each step ca be preseted wth a set o Z k, rom put bts whch partcpate the th output bt o a stage or o the cascaded part o the stage, called recursos []. Here, k=0 shows that the set Z k=0, s related to the rst stage o equato (3), whle 0< k r pots to the k th recurso o the secod stage as s evdet by (3). The outputs bts whch are the result o multplcato o x ad y j ca be deted by wrtg j 5 bary ormat as t s show by (3). For stace, or = ad j=, we have: j (0) As dcated [], x mples that x s a bary umber, ad thereore, because o equato (6), the bt multplcato o x y pots to the output bts o weghted postos ad 0, as show equato (7). x y x y x y j 0 5 Cosequetly, t ca be stated that x y are elemets o, Z 0,0, ad Z 0,. Ths techque s used to compute all Z k, or each o recursos the secod stage. Aother way to descrbe each recurso multplcato s the use o lag bt cha (q,j,k ), where, q,j,k є{0,}, ad each q,j,k express whether the j th put bt partcpates the result o th bt or ot durg the k th recurso []. The, Z k,, based descrpto s detcal to a lag bt sequece, sce Z { y q } k, k, j, j, k where, y k,j s the put bt o k th recurso o weght j replaces y k, j equato (8). By deg the m Z k, or the lag bt sequece, a archtecture cludg oe bt ull adders (FAs) ad hal adders (HAs) ca be mplemeted usg the methodology used by Vassls et al. [], kowg sets o Z k, or the lag bt cha. The multpler archtecture troduced by Vassls et al., was orgazed three stages: the rst ad secod stages they used carry-saved array, ad each stage had colums o FAs, HAs, ad OR gates. They troduced a hardware reducto procedure a way that t reduces the (6) (7) (8) umber o -bt adders a colum by OR gates. Frst, they cotemplated the recurso o the secod stage such that equato (9) s a put to the k th recurso ad k represets the word legth o the maxmum value o Y k, whch s calculated through smulato. There exst the couples (y k,j,y k,j) Y k j 0 or trplets (y k,j, y k,j,y k,j3 ) rom put bts o y k,j є{0,}, such that 0 < j, j, j 3 < k, s assged to the th colum,.e., q j,,k = q j,,k = or q j,,k = q j,,k = q j3,,k =, the summato o whch does ot geerate a carry or ay Y k є I k ={0,,,Y max,k- }. Sad otherwse, or the trplets t holds y y y Y I (0) whereas, or the couples t s: k y k, j k, j k, j k, j3 k k y y Y I (9) () where, I k s the set o vald put values. I order to mmze the umber o bts added to a colum, the largest umber o separate couples or trplets, produced by bts composed each o the Z k, set, that satsy the terms o equatos (0) ad (), respectvely. The umber o bts to be added a colum s mmzed whe the umber o bts cluded a specc couples or trplets s maxmzed. Thus, the put bts are grouped to approprate sets o couples ad trplets by dctatg equatos (0) ad (). The desg procedure troduced by [] uses equato (0), (), ad the couples (x,y) or trplets (x,y,z) o x,y,z є Z k, ad categorze them to sets ( o t ) ( ) C ad C d. Also, bts o Z k, are categorzed to set o dsjot trplets or couples, or each colum, called C, ad a set such that collects the remader o the bts that are ot member o ay o the trples or couples, called C. From the umber o possble C ad C sets that ca shape the sets o C, m ad C, ad mmze the summato, m c result o put bts added the th colum gve as S () are ppoted ad vetured the dervato o the archtecture o resdue multpler []. I order to clary the desg procedure the authors gave a example o a modulo-5 resdue multpler, Fg. (). The multplcato operads were chose to be A ad B, ad the dgt postos to whch the put bt product a b j cotrbute, are show Table (). Usg the thrd colum o ths table, the correspodg Z k=0, sets are cogured ad depcted Table (). I the rst step o the proposed multpler, by kowg the cotet o Z 0,, k, j k, j k k S C C c j Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.

4 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): ( t ) ( ) C C d the ad usg correspodg equatos [] are determed. gates. Accordg to deto [], a OR gate s sucet to add the bts o the couples or trplets o C, m ; hece, the FAs or HAs ca be replaced by OR gates. Ths s easble sce two or more bts caot be deed cocurretly ad because, carry geerato s ot requred ad s elmated. For more detals reer to []. 3. Parallel Prex Adder Fg.. Modulo-5 resdue multpler [] The secod step ths modular desg s to costruct the sets o C ad C show [] or correspodg colum. The al step s to select C ad C amog,m, m deret sets o C ad C. For example, colum =, the umber o bts to be processed s determed by C ( a b, a b, a b ) 0 0, ad C 0, where sets, m c S. Table : Sets o Z k=0,, or =0,,,... or a modulo-5 resdue multpler [] j j ( j ) Table : Iput assgmet to dgtal postos or a modulo-5 resdue multpler []. Z 0, Z 0, Z 0,0 a 0b a 0b a 0b 0 a b a b 0 a b a b 0 a b a b a b a b The orgazato o each colum s deed by creatg sets o C, m ad C, m. The bts added at the $$th colum are the carry bts rom colum (-) th colum accordg to the carry-save paradgm. Iput bts o set, ad bts created by two or three put OR C, m The modulo + addto s computed by A=X+Y+ -; where, X ad Y are + bt operads the rage o [0, ], such that, A= a a - a a 0, X= x x -... x x 0, ad Y=y y - y y 0, accordg to [8] [] ad R s deed as (r r - r r 0 ) ad s computed by X+Y + ; where, A= +. The computato s made by equato (3): R a a a a ( ) a 0 ad to calculate R equato (4) s used. A X Y S C (3) (4) I equato (4) S s the summato o bts th colum ad C s the abbrevato or carry out o colum -. Ths addto s llustrated Fg. (). x x - x x 0 y y - y y 0 s s - s s 0 c c - c c 0 a - a a - a a a 0 Fg. Calculato o A=X+Y+ -. As t s see ths Fg. (), the summato o bts each colum s computed by s x y, except the th colum whch s gve by equato s x y. Carry geerato due to the addto o each colum s traserred to ext colum ad s equal to c x y ad also carry traser rom th colum s computed by replacg dex by the last equato. To calculate the al result R, the ollowg terms have to be calculated. r a a s c G 0 0 0, where G, s the carry out o th colum whle calculatg A. For -, r ad r are equated by: Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.

5 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): r a G, s c G, r s c a G, G, where, s the carry to posto, the addto a a aa 0 c G,. The -bt addto Fg. () where S s beg added to C ca be computed usg ay carry-accelerate adder scheme lke: carry look ahead adders [3], parallel prex adders, ed-roud-carry, etc. [3] [8] [4] [5] [6] [7]. Techcally, we ca postpoe the calculato o C (carry that eter to last sgcat bt posto) to the al (last) stage o postoal carry trggerg. So, t s preveted rom oe ew precursor calculato o carry. C s the carry gog to posto whe C0= C=0, ad P ad G are varables that represet, geerate ad propagate expressos based o posto o geerato ad propagato sgal. The al carry to th posto s used calculatg s p c. The two varables P ad G are deped o all the gj ad pj- sgals where (0 j ). These recursve computatos ca be evaluated through precursor carry look-ahead operatos cells or parallels prex adders [3] as: G g P G, g x y ( x y ) P P p, P x y (x y ) The ed-aroud-carry s a G x y, where both G ad xy caot be equal to oe. Computato o c ads ca be obtaed drectly by S P C ad a p c. Hece, t s ot ecessary to calculate S P C ad s a a [8]. Eestathous adder s oe o the astest modulo addto troduced so ar. Ths adder s show Fg. (3) whch ca be used to perorm the modular multplcato o our cocer. Reer to [8] or more detal dervatos o the parallel prex adder. I ext secto the ovel modulo + resdue multpler s troduced. Fg. 3 Parallel prex adder [8]. Multplcatos hgher modules, based o reducto o partal products a gve module. I ths proposed archtecture the reducto o partal products are 4. Proposed Modulo + Multplcato A geeral block dagram or modulo M multpler s llustrated Fg. (4). The rst block s a partal product geerator. The secod block reers to pre-processg o partal products accordg to []. The thrd block represets a -bt bary log adder, usg oe o the adders lke rpple-carry adder, carry accelerate adder, parallel prex adder, carry skp adder, ed-aroud-carry adder, ad etc. [3] [8] [4] [7]. Two approaches ca be adopted or the proposed multpler archtecture. The rst approach s appled lower modules lke 5, 7 ad 9, where by usg truth table, a smpled desg s obtaed. Ths approach s called desg method I ad s preseted detals the ollowg secto. The secod approach s or preormg Fg. 4 Geeral block dagram o proposed RNS multpler. accordg to detos []. Hece, the XOR gates [6] ad OR gates [7], covetoally employed to geerate sum dgt are replaced by wred or gates whch have o delays. The gates show by a dot sde them are cosdered as wred OR gate. Wred OR gate s a gate where oly ad oly oe o ts puts has a value o oe ad the rest are zeros. I the secod part we use carry save adders ad ally a ed-aroud-carry parallel prex adder s used. Ths approach s reerred to as desg method II. 4. Desg Method I Desg method I s sutable or lower modules lke modulo 5, 7 ad 9. The ollowg ew modulo + multpler s a twoold structure ormed through a low complexty combatoal RNS multpler [], reducto combatoal crcut ad ast parallel prex + adders [0] [7] [8]. The ma cocer here s to gure out a Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.

6 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): way to use parallel prex structure order to add up the outputs o the rst stage o resdue bary umber multpler o Fg. (). Usg modulo-5 or llustratg modulo multpler by [] s used ths study. Cosderg that the operads A ad B are the puts to the rst block o the modular multpler, the partal products are classed to couple ad trplets. The classcato o couples ad trplets are maaged a way that the HAs ad FAs the th colum are replaced by wred OR gates stead o covetoal OR gates whch were used []. Cosequetly, the rst stage o ths ewly proposed multpler s same as [] ad t s llustrated Fg. (5). I order to obta desred result, the outputs o the rst stage must be the rage o modulo-5 order to use the Estathous parallel prex adder. Uortuately, the results are ot modulo rage. I order to use parallel prex adder stead o the adder used [], the outputs o Fg. (5) have to be coverted to modulo rage. Thereore, or all the combatos o puts, the put-output truth table show Table (3) s tabulated. Accordg to Table (3), or oly three deret put sets the outputs are ot the resdue rage ad exceed modulo-5. The correspodg combatos o puts are show bold aces Table (3). As a example, t s assumed that a a a 0 ad b b b 0 Fg. (7) are 0 ad 00, respectvely. The outputs A A A ad B B B o the rst stage or these sets 0 0 o puts are equal to ad 000, accordgly. Table 3: Truth table or possble combato o puts modulo-5 Fg. 6 Proposed reducto crcut modulo-5. Fg. 5 Frst stage o RNS multpler modulo-5. The detcato o these states cotrbute to the proposed combatoal crcut whch makes the use o parallel prex adder leu o adders used [] possble. The combatoal desged crcut s the secod stage o RNS multpler used proposed desg (see Fg. (6)). Ths combatoal crcut s desged to keep all the sets o put values modulo rage. Accordg to the truth table show Table (3), the outputs o all the put sets or A A A 0 ad B B B 0 are wth the modulo rage. Ater addg the secod stage to the rst that, the outputs wll ever go beyod the resdue rage s assured. Thereore, the Estathous parallel prex adder s used to perorm addto ad produce the al result o the RNS multpler (see Fg. (7)). It s otceable that the outputs exceeded the resdue rage, modulo-5. The outputs o the rst stage are the puts to the secod stage. That s the proposed combatoal crcut troduced. Usg these sets o puts, the outputs A A A 0 ad B B B 0 are evaluated as 0 ad 00, respectvely. Now, the set o outputs calculated are modulo-5 rage. Hece, these outputs are the puts to the Estathous parallel prex adder order to calculate the multplcato result. 4. Desg Method II The desg method I has a good perormace regardg delay ad area o the hardware or lower modules lke 5 to 9. Hece, aother desg s troduced whch s comparable to state-o-the-art structures lke that o the [4] [5] [6] [7]. Here, the proposed archtecture cossts o three parts. Frst part correspods to geerato o partal products ad reducto o the partal Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.

7 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): products to the gve module rage. To reduce the partal products wth the rage o module set, some parts the dea troduced by Vassls et al. [] ad or some other parts the Eetathou ad Vergoss algorthm s appled. Next the attempt s made to reduce the partal products to rows o sum ad carry operads usg carry save adders. Fally to obta the multplcato result a addto s perormed to add the two operads rom prevous stage. a 0b 0 a b a 0b 0 a b a b ab ab a0b a b 0 ab ab0 ab a0b a0a b +b HA 0 A 0 B 0 A B A a b c B c s s A 0 B 0 A B A B HA HA HA a b g c p ( g x, p x ) ( g y, p y ) Fg. 7 Proposed modulo-5 RNS multpler. The s partal product matrx s derved rom the tal partal product matrx Fg. (8), based o several observatos. Frst observato s, the tal partal product matrx ca be dvded to ve groups o A, B, C, D ad E as t s show Fg. (8). Fg. 8 Ital partal product matrx. Next, For each term o p,j belogg to groups B ad D, P,j + s calculated ad accordg to ts weght t s scattered amog the colums wth the weghts o 0 to - group A. Sce + =, the term p, s moved to colum wth weght o 0. Fally, each partal product C 0 S C S C S 0 g p p ( g, p ) c g, p ) g, p ) g ( x x ( y y p c r r 0 r r o the group E s verted ad repostoed at the (+j-) colum. Ths repostog takes place based o equato 5. Ths equato shows that repostog o a b a b (5) j each bt eeds a correcto actor o. I the rst partal product vector, there s oly oe such bt ad the secod partal product vector two bts must be traserred ad so o. Hece, the correcto actor or repostog the partal product matrx s gve by equato 6. COR j j j j (( ) ( ) ( ) ( a b ) j (6) The partal products o the group A g. (8) alog wth equato 6, results + operads. By usg carry save adders (CSA), reducto o the partal products to al summads Sum array ad Carry array becomes possble. Assumg that the carry out o $$th stage o CSA s c wth weght o, ths carry array ca be reduced to: c c c Hece, the output carry array at the most sgcat bt posto o each stage s used as put carry array to the ext stage. Sce a - stage (CSA) array, there exsts - carry out bts thereore there s a eed or a secod correcto actor. Ths correcto actor eeded or the verted (ECAs) ad s preseted by equato [7]. COR ( ) (7) The al correcto actor s computed by addg equatos 6 ad 7 order to d the total correcto gve by equato 8. COR COR COR (8) Ater all the partal products are traserred rom posto to to group A o Fg. (8), the reducto procedure troduced by [] becomes possble. Accordg to deto [], to mmze the umber o bts added each colum o group A, a OR gate s sucet to add the bts o the couples or trplets o C, m. Ater perormg partal product reducto, -bt Sum vector (S) ad -bt Carry vector (C) are ready to be added a al stage addto module. Accordg to Zmmerma [4] where S C S C C out ( ) ( ) ( ) 3 j j a b j j Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.

8 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): Table 5: by Partal-product matrx modulo-7 multplcato 3 0 pp 0 =a 3 b 0 + a b 4 + a 4 b pp =a b + a b 4 + a 4 b pp =a b + ab pp 3 =a 0 b 3 + a 4 b 3 + a 3 b 4 pp 4 =0 a b 0 + a 4 b + a b 4 a b + a 4 b 4 + a b 4 + a 4 b 3 a 0 b + a 4 b (a b 4 + a 4 b + a 3 b 3 ) 0 a b 0 + a 4 b a 0 b +a b 4 (a b 4 + a 4 b + a 3 b ) (a b 4 + a 4 b 3 + a b 3 ) a 0 b 0 +a 4 b 4 + a 3 b 4 + a 4 b (a b 4 + a 4 b + a b ) (a b 4 +a 4 b 3 + a 3 b ) (a b 3 + a 4 b 0 + a 0 b 4 ) 0 the costat the above equato ca be obtaed rom equato 8 whch s the costat 3. Hece the ew al partal product s the costat whch wll be added to the rest o the partal products. As a example, let s cosder modulo-7 multpler or the proposed archtecture here: Frst, the partal products o the colums 4 to 8 are traserred to approprate postos accordg to what s explaed above. Table (4) shows the partal products traser to matrx A. Table 4: Traser o partal products to approprate postos 3 0 a 3 b 0 a b a b a 0 b 3 a 4 b 3 a 3 b 4 a 4 b a b 4 a 4 b a b 4 a b 0 a b a 0 b a 4 b a b 4 a 4 b a b 4 (a 3 b 3 ) a b 0 a 0 b a 4 b a b 4 (a 3 b ) (a b 3 ) a 0 b 0 a 4 b 4 a 4 b 3 a 3 b 4 a 4 b a b 4 a 4 b a b 4 (a 3 b ) (a b ) (a b 3 + a 4 b 0 + a 0 b 4 ) The ext step s the reducto o partal products show Table (4) to our rows. At ths pot, the objectve s to dety the largest possble umber o dsjot couples or trplets, ormed by bts cotaed each o the Z k, sets, whch satsy codtos o the equatos 0 or, respectvely. By maxmzg the umber o bts the partcular couples or trples, the umber o bts to be added a colum s mmzed []. For example posto 0 the partal products o a 0 b 0, a 4 b 4, a 3 b 4 ad a 4 b satsy the codtos o equatos 0 or ; thereore, they are wred OR together ad sce oly ad oly oe o the partcpated partal products could have value o, hece, the wred OR gate s used stead o covetoal OR gate order to perorm logcal OR o the puts. As t was metoed prevously, a wred OR s a OR gate wth a dot sde o t. Aother example: posto 4 the partal products o a 4 b 0, a 0 b 4, ad a b 3 satsy the codtos equato 0 or : thereore, Fg. 9 The proposed archtecture or modulo-7 multpler. they are wred OR together ad the verted ad traserred to posto 0. Ad yet aother example where the partal products a b 4 ad a 4 b posto 0 satsy equato (), they ca be added by the partal product a b the same colum. Ater dog the requred mapulatos, a b a b a b s obtaed as sum 4 4 ad a b a b as carry whch goes to ext posto s 4 4 calculated. Ths approach s repeated or all the colums utl the partal product matrx s derved (see Table (5)). The block dagram o Table (5) s preseted Fg. (9). As t s show the gure partal products are mplemeted ether by wred OR gates or wth wred NOR gates. It s evdet that the proposed multpler out perorms the prevous multpler desgs ad t s well suted or VLSI mplemetato. 5. Area-Delay aalyss ad comparsos I the ollowg secto the area ad tme complexty o the proposed multplers are aalyzed. The two desg methods are troduced ad desg method I s explaed order to be used or lower modulo sets lke 5, 7 ad 9. Desg method II s a more geeral multpler ad ca be employed or hgher modulo sets. Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.

9 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): Table 6: Comparso o the proposed multpler agast [7] ad [] Stouratss RNS multpler [7] Vasslss RNS multpler [] Proposed RNS multpler Tme Area Tme Area Tme Area Modulo gate delay (s) Trasstors gate delay (s) Trasstors gate delay (s) Trasstors I both methods I ad II, complexty reducto [] s appled by put classcato to par ad trple groups, so that the maxmum sum o the elemets o every group does ot overshoot. I both desg methods troduced here, t was show that, oe ca use OR gate to replace a more complex hal adders or ull adders. Ths substtuto s possble because, two or more bts caot be smultaeously asserted, thereore, due to the deto, carry geerato s omtted []. I ths artcle we have doe exactly the same ad replaced hal adders ad ull adders by OR gates. I desg method I a combatoal crcut added to keep the elemets o each colum the resdual rage whch allowed the parallel prex adder used to compute the RNS multpler result. The perormace o the proposed RNS multpler wth respect to delay ad area s compared to [7] ad [] as preseted Table (6). The comparso o deret modules are computed ad the results dcate that the proposed archtecture s more optmzed compared to that o the [7], [] ad [7]. comparsos dcate that the proposed desg method I has tme ad area optmzato agast [7] ad []. For Modulo sets lke 5, 7 ad 9 proposed desg I s also superor to Vergos et al. [7]. They used ut gate model or qualtatve comparsos: cosdered all -put mootoc gates cout as oe, -put XOR/XNOR gate cout as two equvalets or both area ad delay [7]. Usg the same qualtatve comparso lower modulo-5, the delay ad area calculated rom [7] s 7 ad 35 logc gates cout respectvely, whereas the delay ad area or the ewly proposed desg method I s 3 ad 35 logc couts. Area s estmated umber o requred trasstors, whle tme s expressed gate delays. As emphaszed, desg method II s geeral proposed multpler or ay modulo sets. Employg the same strategy adopted by [7] or computg delay ad area, the area calculato s apportoed to three modules. The rst module s to calculate the area eeded or ormg partal products. To produce the partal products o Fg. (8), there s a eed or + AND (NAND) gates ad sce the wred OR gates are used ths proposed desg thereore the total area requred to produce partal products s gve by equato (9). A partal (9) Fg. 0 Tme comparso o proposed multpler agast [7] ad []. I order to quaty the area complexty o the archtecture, t s assumed that FA, HA, two put OR gate ad three put OR gate each have complexty o 8,, 6 ad 8 trasstors, respectvely []. The tme ad area comparso betwee that o the proposed structure ad [7] ad [] are show Fg. (0) ad Fg. (), each the order o modulo sets gve. The preormed Fg. Area comparso o proposed multpler agast [7] ad []. The secod module cossts o CSA tree, ad cosderg that each HA ad FA has area o 3 ad 7 respectvely. Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.

10 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): Lookg at gure (8) ad Table (5), the rst row o desg method II there s 3 umber o HAs; thereore, the area s 3. The remag rows have ( ) FAs hece, the area s 7(-). The total equvalet gate requred or partal products s gve by equato (0). A 3 7 ( ) CSA (0) The last module s the ed-aroud carry whch was computed [7] ad s equal to equato (). 9 A () adder log 6 Addg equatos (9), (0) ad (), would yeld the total area equvalet gates occuped by the proposed multpler ad ca be computed by equato (). 9 A proposed log 8 7 () whereas, the area o the proposed multpler by [7] s gve by equato (3). 9 A 8 [7] log (3) As t s evdet the proposed desg has a better perormace regardg area occupato o the hardware compared to [7]. Table (7) shows the savg area oered by proposed multplers or deret operad szes. Table 7: Area comparsos A Proposed A [7] Percet Savg Computato o delay s based o three stages, amely, the cotracto delay o partal products, the delay reducto o partal product va CAS adders ad ally the delay o verted EAC adder. The delay o partal product ormato ths proposed desg s oe tme ut, ad a worst case stuato aother tme ut s the delay o wred or gates. Thereore, the delay here has the same dervato as [7], the oly derece s that the delay or partal products here s tme ut whe + s a umber o Dadda sequece (6, 9, 3, 9, 8, 4, 63, ). ad tme ut otherwse. The delay o CSA parallel adders here s the same as [7]. At last, the tme delay o verted EAC adder s gve by whch T s same log as that 3 adder o the [7]. Addg up the tme delay o three stages o the proposed multpler would gve the total delay as: 8 =4 + s a umber Y= 4D(+)+ log +5 o Dadda sequece. 4D(+) + log +4 otherwse The oly derece betwee ths tme delay ad that o the [7] s whe + s a umber o Dadda sequece ad that s because ths desg wred OR gates are used. Table (8) shows the delay comparso betwee the proposed desg ad that o [7]. Table 8: Tme Comparsos T Proposed T [7] Cocluso Two ovel low complexty combatoal + RNS multplers Usg Parallel Prex Adders are proposed ths artcle. The proposed desgs use a sutable groupg o puts to couples or trplets a way that, the maxmum sum o elemet does ot exceed the uty. I order to be able to do the modular addto parallel, a ew proposed mplemetato s proposed. Comparsos agast the state-o-the-arts modular multpler archtectures show that: the proposed multpler I s more compact ad oers a hgher speed or lower modules ad desg method II s more compact ad has a comparable delay. The proposed RNS multpler ca be appled more ecetly practcal approaches specally, DSP systems where resdue umber systems are the ma course. Reereces [] A. Omod, ad B. Premkumar, Resdue Number Systems Theory ad mplemetato, College Press page 53-54, Chap [] M. A. Soderstrad, W. K. Jeks, G. A. Julle, ad F. J. Tayor, Resdue Number System Arthmetc: Moder Applcatos Dgtal Sgal Processg, IEEE Press, New York 986. [3] S.Tmarch, ad K. Nav: A Novel Modolo + Adder Scheme, computer Socety o Ira Computer Coerece 007(CSICC07), Shahd Behesht Uversty, Tehra, Ira 007. [4] N. Szabo, ad R. Taak, Resdue Arthmetc ad ts Applcato to Computer Techology, New York, LCCCN: , McGraw-Hll Book Compay 967. [5] R. Coway ad J. Nelso: Improved RNS FIR Flter Archtectures, IEEE Tras. O Crcut ad Systems-II: Express Bres, Vol. 5, No., Ja Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.

11 IJCSI Iteratoal Joural o Computer Scece Issues, Vol. 0, Issue, No 3, March 03 ISSN (Prt): ISSN (Ole): [6] K. c. Posch, R. Posch: Modulo Reducto Resdue Number Systems, IEEE Trasacto O Parallel Ad Dstrbuted Systems, Vol. 6 No.5, May 995. [7] L. Yag ad L. Hazo, Redudat Resdue Number System Based ERROR Correcto Codes, IEEE 54th o Vehcular Techology Coerece, Vol. 3, pp , Oct. 00. [8] J. Ramrez, et al., Fast RNS FPL-based Commucatos Recever Desg ad mplemetato, Proc. th It. Co. Feld Programmable logc, pp , 00. [9] R. Rvest, A. Shamr, ad l. Adlema, A Method or Obtag Dgtal Sgatures ad Publc Key Cryptosystems, Comm. ACM, Vol., o., pp. 0-6, Feb [0]G. A. Julle, Implemetato o Multplcato, Modulo a Prme Number, wth Applcato to Theoretc Trasorms, IEEE Trasacto o Computers, Vol.9,No.0, pp , Oct []Vassls Palouras, Kostata Karaga ad Thaos Stourats, A Low-Complexty Combatoral RNS Multpler, IEEE Tra. Crcut ad system-ii: Aalog ad Dgtal Sgal Processg, VOL.48, NO. 7, pp JUL. 00. []M. Soderstad ad Cvera, A Hgh Speed Low-Cost Modulo P Multpler wth RNS Arthmatc Applcato,Proc. IEEE,Vol 68, pp.59-53,apr [3]D. Radhakrsha, ad Y. Yua, A Fast RNS Galos Feld Multpler, IEEE Trasactos o Crcuts ad Systems, pp , 990. [4]A. A. Hasat, New Ecet Structure or a Modular Multpler or RNS, IEEE Trasacto o Computers, Vol. 49, pp.70-74, Feb [5]E. D. DClaudo, F. Pazza, ad G. Orlad, Fast Combatoral RNS Processors or DSP Applcatos, IEEE Tras. Comput. Vol. 44, pp , May 995. [6]A. Wrzyszcz, D. Mlord, ad E. Dagless, A New Approach to Fxed-Coecet Ier Product Computato over Fte Rgs, IEEE Tras. Computers, vol. 45, o., pp , Dec [7]T. Stourats, S. W. Km, ad A. Skavatzos, Full Adderbased Arthmetc Uts or Fte Iteger Rgs, IEEE Tras. Crcuts Syst. II, vol.40, pp , Nov [8]C. Estathou, HT. Vergos, D. Nkolos, Fast Parallel-Prex Modulo + Adders IEEE TRANSACTIONS ON COMPUTERS, VOL. 53, NO. 9, Sep [9]J. l. beuchat, A Famly o Modulo + Multpler, sep [0]D. J. Soudrs, V. Palouras, T. Stourats, ad C. E. Gouts, A VLSI Desg Methodology or RNS Full Adder-based Ier Product Archtectures, IEEE Tras. Crcuts Syst. II, vol. 44, pp , Apr []V. Palouras ad T. Stourats, Multucto Archtectures or RNS Processors, IEEE Tras. Crcuts Syst. II, vol. 46, pp , Aug []S. Tmarch, K. Nav, ad M. Hossezade, New Desg o RNS Subtractor or modulo +, d IEEE Iteratoal Coerece o Iormato ad Commucato Techologes: From Theory to Applcato, pp. 4-8 Apr [9] P. M. Kogge, ad H. S. Stoe, A Parallel Algorthms or the Ecet Soluto o a Geeral Class o Recurrece Equatos IEEE Tras. Computers, Vol., No. 8, pp , Aug [4]R. Zmmerma, Ecet VLSI Implemetato o Modulo ± Addto ad Multplcato, I Proc. o the 4 th IEEE Symposum o Computer Arthmetc, pp , Aprl 999. [5] C. Estathou, H. T. Vergos, G. Dmtrakopoulos, ad D. Nkolos, Ecet dmshed- modulo + ultplers, IEEE Tras. Comput., Vol. 54, No. 4, pp , 005. [6] H. T. Vergos, C. Estathou, Novel Modulo + Multpler, 9th EUROMICRO Coerece o Dgtal System Desg, pp , 006. [7] H. T. Vergos, C. Estathou, Desg o ecet modulo + multplers, IET Comput. Dgt. Tech.,Vol., No., pp , 007. Mohammad R. Reshadezhad He was bor Isaha, Ira, 959.He receved hs B.S. ad M.S. degree rom the Electrcal Egeerg Departmet o Uversty o Wscos, Mlwaukee, USA 98 ad 985,respectvely. He has bee posto o lecturer as aculty o computer egeerg Uversty o Isaha sce 99. He also receved the Ph.D Deggree computer archtecture rom Shahd Behesht Uversty, Tehra, Ira, 0. He s curretly Assstat Proessor Faculty o computer Egeerg o Isaha Uversty. Hs research terests are dgtal arthmetc, Naotechology cocerg CNFET, VLSI mplemetato, logc crcuts desgs ad Cryptography. Farshad Kabr Sama He receved hs B.S. ad M.S. degree computer egeerg (hardware) rom Uversty o Naja Abad, Ira ad Uversty o Arak, Ira 007 ad 00 respectvely. He s curretly workg as a lecturer ad researcher Faculty o electrcal ad computer egeerg departmet o Leja Uversty, Leja, Ira. Hs research terests maly ocus o computer arthmetc algorthms ad crcuts, mcroprocessor archtecture, ad VLSI hardware desgg. Copyrght (c) 03 Iteratoal Joural o Computer Scece Issues. All Rghts Reserved.