Fig. 2. torter. z(n) =

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1 A MEMORY POLYNOMIAL PREDISTORTER IMPLEMENTED USING TMS320C67XX Lei Ding, Hua Qian, Ning Chen, G. Tong Zhou School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA , USA. ABSTRACT x(n) Digital baseband predistortion is a highly cost effective approach to linearize modern RF power amplifiers (PAs). Traditionally, the PA is considered a memoryless nonlinear PSfrag replacements device. However, for wideband (such as WCDMA) and/or high power (such as base station) applications, PAs exhibit memory effects. Memory polynomial predistorter is shown to be a good choice for linearizing PAs with memory effects. In this paper, we investigate real-time implementation aspects of the memory polynomial predistorter. We implement the predistorter training algorithm on a Texas Instruments TMS320C67xx processor and evaluate the performance of the trained predistorter on our wideband digital predistortion testbed. 1. INTRODUCTION Recent transmission formats, such as wideband code division multiple access (WCDMA) and orthogonal frequency division multiplexing (OFDM), have high peak-to-average power ratios (PAPRs); i.e., large fluctuations in their signal envelopes. This characteristic makes these signals particularly sensitive to the nonlinearity created by the RF power amplifier (PA) in the transmitter. Nonlinearity generates out-of-band emission, also referred to as spectral regrowth, which interfere with adjacent channels. Nonlinearity also causes in-band distortion which degrades the bit error rate performance. One solution is to back off the PA so it operates within its linear region. However, for high PAPR signals, this results in very low efficiency for the PA, typically less than 10% [1]; i.e., more than 90% of the dc power turns into heat and is thus wasted. Another solution is to allow the PA to operate in its nonlinear region to improve the efficiency and use techniques to linearize the PA. Among all linearization techniques, digital predistortion is one of the most cost effective. It employs a predistorter in the baseband before digital-to-analog conversion, upconversion, and input to the PA (see Fig. 1). The predistorter is This work supported in part by the National Science Foundation under Grant No and by the Texas Instruments DSP Leadership University Program. Predistortion Predistorter Construction z(n) y(n)/g D/A A/D Up Down Fig. 1. Predistortion System Diagram constructed as the pre-inverse of the nonlinear PA. Ideally, the cascade of the two results in a linear gain to the original input. With the predistorter, the PA can be utilized up to its saturation point while still maintaining good linearity, thereby significantly increasing its efficiency. To construct the (adaptive) predistorter, a feedback path is often presented in the predistortion system. In the current literature, digital predistortion implementations mostly focus on memoryless PAs (e.g. [2], [3], [4]); i.e., the current output of the PA only depends on the current input. However, as the signal bandwidth widens, PAs begin to exhibit memory effects, which may be due to the frequency-dependent behaviors of the components in the biasing network or the thermal constants of the devices [5]. As a result, the PA becomes a nonlinear system with memory. To effectively linearize PAs with memory effects, predistorters also need to have memory structures. In [6],a memory polynomial predistorter is shown to be robust against several types of nonlinear systems with memory. In this paper, we study real-time implementation aspects of the memory polynomial predistortion system. PA 2. MEMORY POLYNOMIAL MODEL Here, the predistorter adopts the model of Kim and Konstantinou [7], k=1 q=0 a kq x(n q) x(n q) k 1, (1)

2 which we call a memory polynomial. The input x(n), output z(n) and coefficients a kq of the model are all complex valued in general. Note that if the maximum delay Q = 0, (1) reduces to a k0 x(n) x(n) k 1, (2) k=1 which is a conventional memoryless polynomial. A direct implementation of the predistorter model in (1) requires multiplications on the order of K 2 Q. However, an efficient implementation is possible by observing that (1) is equivalent to = x(n q) q=0 a kq x(n q) k 1 (3) k=1 x(n q) LUT q ( x(n q) ), (4) q=0 [8], where the nonlinear polynomial for each delay q is implemented by a lookup table (LUT) indexed by x(n q). Therefore, only Q complex multiplications per sample are needed. 3. INDIRECT LEARNING ARCHITECTURE PSfrag replacements x(n) The indirect learning architecture for the predis- Fig. 2. torter. Predistorter (Copy of A) FPGA/ASIC ẑ(n) z(n) e(n) D/A Predistorter Training (A) DSP Up y(n)/g A/D PA Down the predistorter determines the ability of the predistorter to response to changes in PA characteristics. Although these changes usually happen slowly, which may be due to temperature drift, aging, etc., a powerful DSP increases flexibility of the overall system. 4. PREDISTORTER CONSTRUCTION In the context of predistorter training (see the training block of Fig. 2), (1) becomes k=1 q=0 a kq y(n q) y(n q) k 1. (5) The indirect learning architecture [9] is used here to train the predistorter. This approach enables the predistorter to be constructed directly based on the input and output baseband data of the PA. Therefore, model assumption and parameter extraction of the PA are not necessary. Fig. 2 shows a block diagram of the predistorter training process. The feedback path labeled Predistorter Training (block A) has y(n)/g as its input, where G controls the intended gain of the linearized PA, and ẑ(n) as its output. Note that y(n) has been nominally matched with z(n); i.e., the relative delay and phase rotations have been taken care of. The actual predistorter is an exact copy of the feedback path (copy of A); it has x(n) as its input and z(n) as its output. Ideally, we would like y(n) = Gx(n), which renders ẑ(n) and the error term e(n) = 0. Given y(n) and z(n), our task is to find the parameters of block A, which yields the predistorter. The algorithm converges when the error energy e(n) 2 is minimized. In Fig. 2, the predistorter performs the same computation, such as (4), for every input sample at high-speed. This kind of task is well suited for field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). The predistorter training block, however, involves relatively complex computations, which require a powerful digital signal processor (DSP), such as the Texas Instruments (TI) TMS320C67xx. The time required to train Since z(n) is linear in the parameters a kq, the latter can be estimated by a simple least-squares method. By defining a new sequence r kq (n) = y(n q) y(n q) k 1, (6) we can rewrite (5) in matrix form as z = R a, (7) where z = [z(0),, z(n 1)] T, R = [R 0,, R Q ], R q = [r 1q,, r Kq ], r kq = [r kq (0),, r kq (N 1)] T, and a = [a 10,, a K0,, a 1Q,, a KQ ] T. The leastsquares solution for (7) is â = (R H R) 1 R H z, (8) where ( ) H denotes complex conjugate transpose. The accuracy and stability of the solution â are directly related to the numerical condition of the matrix R H R. A good indication of such condition is the condition number of the matrix [10, p. 258]; i.e., κ (R H R) = λ max λ min, (9) where λ max and λ min are, respectively, the largest and smallest eigenvalues of R H R. The matrix R H R generally has a

3 high condition number, which also means that there is large correlation between the columns of this matrix. There are two sources for this large correlation: The nonlinear polynomials, such as y, y y, y y 2, etc., are highly correlated. 2. The data sample y(n) with different time indices are correlated. PSfrag replacements The correlation due to the first source can be greatly reduced by using the orthogonal polynomial proposed in [11]. In this formulation, (5) becomes where with k=1 q=0 ψ k (y) = U lk = b kq ψ k (y(n q)), (10) k U lk y y l 1 (11) l=1 ( 1) l+k (k + l)! (l 1)!(l + 1)!(k l)!. (12) For a K-th order polynomial, U lk forms an upper triangular matrix U, which leads to the matrix form of (10), i.e., z = F b, (13) where F = [R 0 U,, R Q U]. The least-squares solution for b is then given by Condition Number (a) Q Fig. 3. Condition number of the correlation matrix with different Q values and different input signals: (a) threecarrier WCDMA with K = 5 conventional polynomials; (b) three-carrier WCDMA with K = 5 orthogonal polynomials; (c) a complex random signal (amplitude uniformly distributed in [0,1]) with K = 5 conventional polynomials; (d) a complex random signal (amplitude uniformly distributed in [0,1]) with K = 5 orthogonal polynomials. the orthogonal polynomial offers great advantages. For a three-carrier WCDMA signal, the benefit of using orthogonal polynomial decreases with the increase of the number of delay terms. However, a significant reduction of the condition number is still observed. (b) (d) 5. DSP IMPLEMENTATION (c) ˆb = (F H F) 1 F H z. (14) The orthogonal polynomial in [11] is derived for complex random signals with amplitude uniformly distributed between 0 and 1 (but is robust for non-uniformly distributed amplitudes as well). Therefore, to fully exploit the advantage of the orthogonal polynomial, the amplitude of y(n) should be scaled to the [0, 1] interval first before applying the ψ k () operation. The correlation from the second source can be alleviated by using a special training signal whose samples at different time indices are independent. However, in many cases, dedicated training is not feasible. In this case, the accuracy of the solution â can be improved by using higher precision floating point numbers, such as using 64-bit double precision instead of 32-bit single precision. Fig. 3 shows an example of the condition number of the correlation matrix with different Q values and different input signals. We see that if the input signal is random with uniformly distributed amplitude in [0,1], the condition number is not affected by the number of delay terms, and Because of the benefits of orthogonal polynomials, we focused on DSP implementation using orthogonal polynomials. To evaluate the real-time performance of the predistorter training algorithm, we selected TI TMS320C6711, which is a low-cost yet powerful floating point processor. We implemented the algorithm in C and generated the DSPexecutable code with level-3 optimization provided by the TI C-compiler Implementation Details Figure 4 shows the flowchart of the algorithm. The algorithm starts with acquiring the baseband input and output data samples of the PA. The matrix R 0 is then formed and multiplied with U to form the first K columns of F. The other columns of F are just shifted versions of the first K columns. Next, the upper triangular portion of the coefficients of the correlation matrix F H F are calculated. These coefficients are sufficient to define the whole matrix since the matrix is Hermitian. To obtain the solution for (14), we adopt the Cholesky decomposition approach, which is

4 very efficient in solving linear equations involving a Hermitian matrix [12]. Cholesky decomposition of F H F yields a lower-triangular matrix L such that L L H = F H F. (15) Substituting (15) into (14), we see that ˆb is the solution of L L H ˆb = F H z, (16) which can be obtained easily by using forward and back substitution [12, pp ] Performance Evaluation The computation requirement of the algorithm in the previous section is determined by two factors: the calculation of the correlation matrix and Cholesky decomposition. To give a quantitative measure of the complexity, we evaluate the floating point operations (flops) required by these two steps. For example, one complex multiplication involves six flops: four real multiplications, one real addition, and one real subtraction. It is straightforward to calculate the required number of flops once the C implementation is available. In our program, for a block of N data samples, the number of flops for obtaining F H F is approximately 4.5 K 2 (Q+1) 2 N. The number of flops for obtaining the Cholesky decomposition is approximately 1.5 K 3 (Q + 1) 3. Therefore, when N is large, the computations are dominated by obtaining the correlation matrix. Table 1 shows the CPU cycles and execution time required by the C6711 starter kit to train the predistorter. We see that longer data lengths, more delay taps, and higher precision implementation all increase the computation time, although they all help to improve the predistortion performance. In practice, tradeoffs need to be made. The execution time shown here can be further reduced by (i) using new generations of TMS320C67xx processor, which are able to operate at a higher clock rate, (ii) coding the most time consuming block; i.e., the calculation of the correlation matrix, in assembly. 6. TESTBED MEASUREMENTS In this section, we present experimental results from our digital predistortion testbed, whose configuration is shown in Fig. 5. In the testbed, the digital I/O instrument is a Celerity system with 150 MSPS 16-bit digital input and output capability. It sends out 14-bit digital IF data streams to the DAC board continuously and acquires 12-bit digital IF data samples from the ADC when needed. The DAC and ADC used here are, respectively, AD9772 and AD9430 from Analog Devices. The predistorter training algorithm is implemented on a TI C6711 starter kit, which connects with the Celerity system through a parallel port. A two-stage upconversion and downconversion chain were carefully assembled to avoid introducing extra distortions. In the experiment, the device under test (DUT) is a Siemens CGY0819 handset PA operating at the cellular band ( MHz). The input to the PA is a 3.6 MHz bandwidth signal centered at 836 MHz. We tested both memoryless and memory polynomial predistorters on the PA. To evaluate the effects of the data length on predistortion performance, we trained each predistorter using 5,000 and 20,000 data samples. We used 64-bit implementation for both the memoryless and memory polynomial predistorters. The results are shown in Fig. 6 and Fig. 7. We see that the memory polynomial predistorter achieved more spectral regrowth suppression than the memoryless predistorter. This may be due to the memory effects in the PA or the frequency response caused by the analog filters in the upconverter. Moreover, training with a longer data length helped to improve the performance of the memory polynomial predistorter. Since the memory polynomial involves more parameters (K(Q + 1)) than the memoryless case (K), it is expected that the memory polynomial model needs more data points to estimate. 7. CONCLUSIONS In this paper, we investigated the real-time implementation aspects of the memory polynomial predistorter. While the actual predistorter is suitable for a FPGA or ASIC, the predistorter training algorithm requires a powerful DSP. Our predistorter training was based on orthogonal polynomials and Cholesky decomposition. We evaluated the computation requirements of this algorithm and tested it on a TI TMS320C6711 starter kit. The trained predistorters performed well on our experimental predistortion testbed. 8. REFERENCES [1] A. Wright and O. Nesper, Multi-carrier WCDMA basestation design considerations - amplifier linearization and crest factor control, PMC-Sierra, Santa Clara, CA, Technology White Paper, Aug [2] P. B. Kenington, High-Linearity RF Amplifier Design. Boston, MA: Artech House, [3] J. K. Cavers, Amplifier linearization using a digital predistorter with fast adaptation and low memory requirements, IEEE Trans. Veh. Technol., vol. 39, no. 4, pp , Nov

5 [4] A. N. D Andrea, V. Lottici, and R. Reggiannini, RF power amplifier linearization through amplitude phase predistortion, IEEE Transactions on communications, vol. 44, no. 11, pp , November [5] J. H. K. Vuolevi, T. Rahkonen, and J. P. A. Manninen, Measurement technique for characterizing memory effects in RF power amplifiers, IEEE Trans. Microwave Theory Tech., vol. 49, no. 8, pp , Aug [6] L. Ding, G. T. Zhou, D. R. Morgan, Z. Ma, J. S. Kenney, J. Kim, and C. R. Giardina, A robust predistorter constructed using memory polynomials, IEEE Trans. Commun., Jan. 2004, to appear. [7] J. Kim and K. Konstantinou, Digital predistortion of wideband signals based on power amplifier model with memory, Electron. Lett., vol. 37, no. 23, pp , Nov [8] C. R. Giardina, J. Kim, and K. Konstantinou, System and method for predistorting a signal using current and past signal samples, U.S. Patent Application 09/ , July, START Acquire PA input and output baseband data samples Form Calculate Cholesky Decomposition of F H F F F H F [9] C. Eun and E. J. Powers, A new Volterra predistorter based on the indirect learning architecture, IEEE Trans. Signal Processing, vol. 45, no. 1, pp , Jan Obtain predistorter paramer ˆb [10] T. K. Moon and W. C. Stirling, Mathematical Methods and Algorithms for Signal Processing. Englewood Cliffs, NJ: Prentice Hall, Generate predistorter parameters and send it to FPGA/ASIC [11] R. Raich, H. Qian, and G. T. Zhou, Digital baseband predistortion of nonlinear power amplifiers using orthogonal polynomials, in Proc. IEEE Intl. Conf. Acoust., Speech, Signal Processing, Hong Kong, China, Apr. 2003, pp PSfrag replacements [12] D. S. Watkins, Fundamentals of Matrix Computations, 2nd ed. New York, NY: John Wiley & Sons, Linearization Requirements Met? END No Yes Fig. 4. Flow chart of the algorithm.

6 (a) K = 5, Q = 0 N=5000 N= CPU Cycles Execution Time (s) CPU Cycles Execution Time (s) 32-bit bit (b) K = 5, Q = 4 N=5000 N= CPU Cycles Execution Time (s) CPU Cycles Execution Time (s) 32-bit bit Table 1. Real-time performance of the predistorter training algorithm. D/A BPF1 BPF2 BPF3 PreAmp Celerity Digital I/O System LO1 LO2 DUT A/D LPF6 LPF5 BPF4 Atten TI C6711 Starter Kit Load Fig. 5. Block diagram of the testbed.

7 Ref -20 dbm Samp Log 8 db/ 20:31:48 Jan 8, 2004 Atten 5 db 1R Mkr MHz db * Trace/View Trace Clear Write Max Hold VAvg 100 V1 V2 V3 FC AA (b) 1 (a) (c) Min Hold View Blank Center 836 MHz #Res BW 30 khz VBW 30 khz Span 12 MHz Sweep ms (401 pts) More 1 of 2 Fig. 6. Measured PA output PSD: (a) without predistortion; (b) with K = 5 memoryless predistorter trained by 5,000 data samples; (c) with K = 5 memoryless predistorter trained by 20,000 data samples. (b) and (c) coincide. Ref -20 dbm Samp Log 8 db/ 20:28:27 Jan 8, 2004 Atten 5 db 1R Mkr MHz db * Trace/View Trace Clear Write Max Hold VAvg 100 V1 V2 V3 FC AA (c) 1 (b) (a) Min Hold View Blank Center 836 MHz #Res BW 30 khz VBW 30 khz Span 12 MHz Sweep ms (401 pts) More 1 of 2 C:\STATE055.STA file saved Fig. 7. Measured PA output PSD: (a) without predistortion; (b) with K = 5, Q = 4 memory polynomial predistorter trained by 5,000 data samples; (c) with K = 5, Q = 4 memory polynomial predistorter trained by 20,000 data samples.