Transcription

1 ISSN : (7) C ( ), E-l: ssolos@glco FPGA LUT FPGA EM : FPGA, LUT, EM,,, () FPGA (feldprogrble ge rrs) [, ] () [], () [] () [5] [6] FPGA LUT (Look-Up-Tbles) EM (Ebedded Meor locks) [7, 8] LUT ( 6),, [9] [] [0, ] CPL (Coplex Progrble Logc evces) ( 0) CPL, FPGA LUT, CPL, FPGA,, LUT,,, LUT - () [] FPGA = (, E), = {b 0, b E } E E, E = {<b q, b > b q, b } b 0, b E, E, E b q E Y(b q ) Y, Y = {,, N } [] b q E X = {x, 0

2 ISSN : (7) 0 x L } A = {,, M }, A, b q E A [] =, ), () Y = Y(), () = {T,, T R }, A, R = log M; = {,, R } ()-() () : ; K( ) A; s ; K( s ) s A; X h X (), <, s >; h, K( ) K( s ); h =,, H ) Y( ) Y, A, Y( ) = Y(b q ), b q E A, H ) H ) [] PAL H ) () [5], s A, = {,, I } (I M) K( ) R = log I r, = R U ( ) U FPGA,, LUT (LUTer, LUTer) EM (EMer) X LUTer RG T EMer Y Sr Clock LUTer U, FPGA U LUTer = (, X), () EMer () RG, Sr RG A, Clock LUTer = (T), () K( ) K( ), [0], U H ) U LUTer,, LUTer FPGA [7, 8]: LUT,,, LUT ; (V 0 ), (V) ( F )

3 ISSN : (7) 0, A A : ( T( ) ), ( T( ) ) C (6), C C K( ) R log (I ), (7) I c (7) F EM q F EMer F R F q /, (8) EM, EMer, N / (9) c F F, N (0) K( ) LUTer R K R C () () R C LUTer, 0 R K, U ( ) RG EMer), r ( LUTer),, r ( RC, r 0 (r,r C) () (7) () MX, M : R C () M rl R U LUTer : (T, X) (5) LUTer : (,x) (6) RG : M M (7) (7) MX LUTer : (T) (8)

4 ISSN : (7) 0 MX X LUTer RG T T EMer Y LUTer M Sr Clock LUTer U EMer () (T) (9), U, : A {,, I} A C 5 LUTer LUTer 6 (EMer) 7 (LUTer) 8, 9 ) [6] U () : x x ; x x x x x ; 5 6 x 6 x x 8 x x ; x58 x5x 6 x5x 6; 5 0; x x ; 6 7 x x x5 7 x x5x 6 x x5x 6 A {,,7,,, 5, 6, 7, 5 8, 9, 6 0 7,, U ( },, 0), ) : ; ; 7 8 ; 5 ; ) ; ; 7 () : n A A, n, U () M, R, T {T,, T}, {,, }, I 7, N 8, :

5 ISSN : (7) 0 ; ; ; ; ; ) ; U () T T T T * * * 9 U (),,, 5, 6,, 7 C, I C, R C, {, } C : K( ), K( ) 0, K( 7 ) 0, C,, 00 (7) K( ) 0000, K( ) 00, K( 5 ) 0, K( 6 ) 00 U ( ) LUTer LUTer (0) LUTer :, K( ), S, K( S ), X h, h, h,, 5 ( ) LUTer ( ) K s * ( ) K s X h U h h 000 x 0 x 6 0 x LUTer, h, 7 C h ( )

6 ISSN : (7) 0 LUTer ( ) 7 0 K s U K( s ) X h h h 0000 x x x5x6 000 x5x6 x, K( ), Y( ),, Y( ) Y, A, () r, K( ), EMer, 0 EMer EM, F T 0 {,, }, F ( q 6 ) U ( ) M, R, (8), F F T0, EM, F T0, F T 0 U ( ) N 7, 8, K( ) EMer },,,,, EMer ( ) { K( ) ( ) EMer ( ) Y U Y( K( ) ) **** *** * * LUTer LUT r, (5) LUTer, ) : T T T T T T Tx (6) LUTer ( ) : x (T) 5

7 ISSN : (7) 0, : TT T T TT T () M T T T T * 0 0 * * 0 [7, 8] [, ] LUT, FPGA,,, U LUT,,, [], (0) U ) LUT, U ) % 9 % EMer EM, 86 % [] U ) U ) %,, U ) ( 0 %) FPGA LUT FPGA,, Grou I gl Sses esgn wh FPGAs nd CPLs Aserd: Elsever, pp Sklrov I, Sklrov V, Sudnson A esgn of FPGA-bsed Herrchcl Fne Se Mchnes Tllnn: TUT Press, 0 86 pp e Mchel G Snhess nd Opzon of gl Crcus New York: McGrw Hll, pp 6

8 ISSN : (7) 0 rnov S Logc Snhess for Conrol Auo New York: Kluwer Acdec Publshers, 99 pp 5 // 998, rklov A, Trenko L Logc Snhess for FSM-bsed Conrol Uns erln: Sprnger, 009 pp 7 Aler Corporon FPGA, CPLI nd Srucured ASIC [ ] : hp://wwwlerco 8 Xlnx Inc FPGA, CPL Soluons [ ] : hp://wwwxlnxco 9 Scholl C Funconl ecoposon wh Applcon o FPGA Snhess Norwell: Kluwer Acdec Publshers, 00 9 pp 0,,, /, ,, CPL / //, Yng S Logc Snhess nd Opzon enchrks user gude Techncl Repor Norh Croln: MCNC, 99 pp References Grou, I (008), Sses esgn wh FPGAs nd CPLs, Elsever, Aserd, Neherlnds Sklrov, I, Sklrov, V nd Sudnson, A (0), esgn of FPGA-bsed Herrchcl Fne Se Mchnes, TUT Press, Tllnn, Eson e Mchel, G (99), Snhess nd Opzon of gl Crcus, McGrw Hll, New York, USA rnov, S (99), Logc Snhess for Conrol Auo, Kluwer Acdec Publshers, New York, USA 5 rklov, AA (998), Prncples of opzon logc of Moore FSM, Cbernecs nd Sses Anlss, no, pp rklov, A nd Trenko, L (009), Logc Snhess for FSM-bsed Conrol Uns, Sprnger, erln, Gern 7 Aler Corporon (0), FPGA, CPLI nd Srucured ASIC, vlble : hp://wwwlerco (Accessed 0 Aprl 0) 8 Xlnx Inc (0), FPGA, CPL Soluons, vlble : hp://wwwxlnxco (Accessed 0 Aprl 0) 9 Scholl, C (00), Funconl ecoposon wh Applcon o FPGA Snhess, Kluwer Acdec Publshers, Norwell, USA 0 rklov, AA, Trenko, LA nd Tsololo, SA (009), Opzon of Moore FSM pleened n FPGA bss, Cbernecs nd Sses Anlss, no 5, pp rklov, AA nd Tsololo, SA, (008), Opzon of Moore FSM pleened n CPL bss, Uprvljjushhe sse shn, no pp -8 Yng, S (99), Logc Snhess nd Opzon enchrks user gude Techncl Repor, MCNC, Norh Croln, USA : : 050, 7

9 ISSN : (7) 0 FPGA LUT FPGA EM : FPGA, LUT, EM,,, SA Tsololo onesk Nonl Techncl Unvers Opzng crcu of Moore FSM wh FPGA FPGA (feld-progrble ge rrs) re wdel used n he pleenon of coplex dgl sses One of he porn eleens of dgl sses s he conrol un (CU), whch s ofen pleened s Moore FSM Chrcersc feures of Moore FSM re exsence of clsses pseudoequvlen ses (PES) nd regulr nure oupu vrbles These feures re used o reduce hrdwre coss n he crcu of Moore FSM Modern FPGA eleens nclude LUT (look-up-bles) eleens nd EM (ebedded eor blocks) uns LUT eleens hve led nuber of npus (bou sx), whch necesses decoposon relzble funcons Ths n urn leds o decrese n perfornce nd ncrese n power consupon There re n ehods of opzon schees n he bss of Moore FSM CPL (coplex progrble logc devces) These ehods use he presence of lrge nuber of npus (up o 0) n crocells crsls CPL, whch llows up o hree sources of sus codes These ehods cn no be drecl used o pleen FPGA PL crcus becuse of he sll nuber of npus n LUT eleens In hs pper uhor propose odfcon of one of opzon echnques rgeng CPL The purpose of he sudes presened n hs work s he bl o reduce he nuber of LUT eleens of he hree clsses of source codes PES Proble solved n hs work s o develop ehod for he snhess of Moore FSM h reduce he nuber of LUT eleens n he crcu rggers he foron of excon funcons of eor In hs cse he conrol lgorh of he dgl sse s represened s grph-schee of lgorh The condons re gven for pplng he proposed ehod An exple s shown for s pplcon Kewords: FPGA, LUT, EM, Moore FSM, snhess, hrdwre opzon,,,, (, 58,, 800, ) CPL FPGA 8