Digital Phase-Locked Loop and its Realization

Transcription

1 Proceedings of the 9th WSEAS International Conference on APPLIE INFORMATICS AN COMMUNICATIONS (AIC '9) igital Phase-Loced Loop and its Realiation Tsai-Sheng Kao 1, Sheng-Chih Chen 2, Yuan-Chang Chang 1, Sheng-Yun Hou 1, and Chang-Jung Juan 1 1 epartment of Electronic Engineering, Hwa-Hsia Institute of Technology. No. 111 Gong Jhuan Road, Chung Ho, Taipei County 23568, Taiwan, R.O.C. TsaiShengKao@gmail.com 2 Graduate Program of igital Contens and Technologies, ChengChi University. No. 64, Sec. 2, ZhiNan Rd., Wenshan istrict, Taipei City 1165, Taiwan, R.O.C. Abstract: The realiation of a digital phase-loced loop (PLL) requires to choose a suitable phase detector and to design an appropriate loop filter; these tass are commonly nontrivial in most applications. In this paper, the PLL system is first formulated as a state estimation problem; then an extended Kalman filter (EKF) is applied to realie this PLL for estimating the sampling phase. Therefore, the phase detector and loop filter are simply realied by the EKF. The proposed PLL has a simple structure and low realiation complexity. Computer simulations for a conventional PLL system are given to compare with those for the proposed timing recovery system. Simulation results indicate that the proposed realiation can estimate the input phase rapidly without causing a large jittering. Key Words: igital phase-loced loop (PLL), state estimation, extended Kalman filter (EKF) 1 Introduction Phase-loced loop (PLL) which constitutes a basic building bloc for many synchroniers lie carrier recovery or timing recovery is essential in most digital communication systems. Owing to the continued advancement in VLSI, all digital phase-loced loop (PLL) has been under extensive investigation for several years [1, 2]. To realie a PLL system, however, the selection of a phase detector [3, 4, 5] is crucial and the design of a loop filter is nontrivial. A PLL is, in general, a nonlinear system due to the nonlinear behavior of the phase detector. Unfortunately, few studies have been published on modeling a phase detector. Hence, the loop filter design often ignores the dynamics of the phase detector, causing the performance of the PLL less reliable. The conventional loop filter design involves in selecting the order of the loop filter and determining its loop gains such that the performance of a PLL satisfies fast phase acquisition and small phase jitter. However, the two characteristics of conventional PLL systems with fixed loop gains are contradictory since fast phase acquisition requires wide loop bandwidth and small phase jitter requires narrow loop bandwidth [6, 7]. Moreover, the determination of the loop gains is difficult using the transfer function approach, especially when the order of the loop filter is high. A Kalman filter (KF) was realied as a loop filter to fulfill the above characteristics together with time-variant loop gains [8, 9, 1, 11], and these Kalman gains were shown to be equivalent to the time-variant loop gains of a PLL. The performance of this PLL bit synchronier is significantly improved by using these timevariant loop gains in place of the fixed gains of a conventional PLL. Although riessen [8] used a KF to realie the loop filter of a PLL, this realiation did not tae the phase detector into account and the timing information was assumed to be nown in advance. In this paper, we use an extended Kalman filter (EKF) to realie the loop filter as well as the phase detector of a PLL, and the loop gains are easily obtained via the extended Kalman filtering techniques. The proposed system has a simple structure and low realiation complexity. The rest of the paper is organied as follows. In section II, the channel model is described and the function of a PLL is briefly reviewed. In section III, we formulate the PLL system as a state estimation problem and apply an EKF to realie this PLL. In section IV, phase domain models of both a conventional PLL and the proposed EKF-based PLL are described. In section V, simulations are shown to verify the proposed PLL. Finally, conclusions are given in section V. ISSN: ISBN:

2 Proceedings of the 9th WSEAS International Conference on APPLIE INFORMATICS AN COMMUNICATIONS (AIC '9) 2 Channel Model and PLL System Overview The baseband model of a synchronous data transmission system is shown in Fig. 1. The information sequence {a } is independently chosen from the set of {1, } with equal probability, and the data bit a is transmitted through a transmission channel at time instant t = ( ɛ )T, where T is the bit interval and ɛ is the input phase, normalied with respect to T. Owing to the channel imperfections, an equalier is commonly included to eliminate the intersymbol interference. Thus, the overall impulse response h(t) encompasses the transmission channel and an equalier; the output of the equalier can then be described as: r(t) = a i h(t (i ɛ i )T ) n(t) (1) i= where n(t) is the filtered noise. Assume ɛ is slowly time-variant, and write the sampling data of (1) at time instant ˆt = (ˆɛ )T as: L r = a i h i ((ɛ ˆɛ )T ) n (2) i=l where r = r(( ˆɛ )T ), n = n(( ˆɛ )T ), and L is chosen such that the term, h i ((ɛ ˆɛ )T ) = h(it (ɛ ˆɛ )T ), is negligible for i > L. In a compact form, (2) is rewritten as: r = a T h((ɛ ˆɛ )T ) n = y n (3) where the data vector a = [a L a a L ] T, the channel parameter vector h((ɛ ˆɛ )T ) = [h L ((ɛ ˆɛ )T ) h ((ɛ ˆɛ )T ) h L ((ɛ ˆɛ )T )] T, and the superscript T denotes the transpose. Thus, y denotes the noise-free data of r. The PLL processes the measurement data r to adjust the sampling time ˆt such that the timing error e = t ˆt = (ɛ ˆɛ )T is approaching ero, where ˆɛ is the predicted estimate of ɛ. Specifically, the information sequence {a } is either nown as a prior in the training mode or replaced by its estimate {â } in the tracing mode, and this class of PLLs is classified as the data-aided (A) structure. 3 Extended Kalman Filter for a PLL System In this section, we formulate the PLL system as a state estimation problem, and an EKF is applied to realie this PLL for estimating the sampling phase due to the nonlinear relationship between the input phase and the noise-free data y. To establish the model [8], define the state vector x = [ɛ ɛ ] T, where ɛ is the timing offset; write the process equation as: x 1 = Φx v (4) [ ] 1 1 where the state transition matrix Φ = and 1 ] v = [ u w representing a ero mean phase jitter u and ero mean timing offset jitter w. Since the noise-free data y of the measurement equation (3) is a nonlinear function of the state vector x = [ɛ ɛ ] T, it is linearied about the predicted estimate ˆx of x as: y = a T h() H (x ˆx ) (5) The vector h() contains the samples of the overall channel impulse response without a phase error, i.e., h() = [h L () h () h L ()] T. Notably, the transpose of the Jacobian matrix plays the role of the measurement matrix in the regular Kalman filtering and is given by [ ] H = y y ɛ ɛ x = [ ] ˆx = a T h () (6) ɛ =ˆɛ where h () = [h L ((ɛ ˆɛ )T ) h ((ɛ ˆɛ )T ) h L ((ɛ ˆɛ )T )] T ɛ =ˆɛ and h i ((ɛ ˆɛ )T ) = h i((ɛ ˆɛ )T ) ɛ for i = L,...,,..., L. Thus, the EKF for a PLL system can be described as: { x1 = Φx v (7) = H (x ˆx ) n where the data = r a T h(). Furthermore, assume v and n are white Gaussian noise with ero mean and their corvariance matrices are given by { E[v v T Q, i = i ] = (8), i and E[n n i ] = { R, i =, i (9) where E[.] denotes the expectation operation. enote P = E[(x ˆx )(x ˆx ) T ] and P 1 = ISSN: ISBN:

3 H A = < A > G = < C Q = <? A >? <? E C G H > A? > G E G H C J I B A S = S E? P > G F C N > = L < L K L K = < A; : 9? > Proceedings of the 9th WSEAS International Conference on APPLIE INFORMATICS AN COMMUNICATIONS (AIC '9) a r(t) tˆ r â Figure 1: Model for the synchronous data transmission system E[(x 1 ˆx 1 )(x 1 ˆx 1 ) T ]. The extended Kalman filter algorithm for estimating the phase and timing offset of a PLL for is described in the following with the initial state vector ˆx and the corvarinace matrix P [12, 13]. The extended Kalman gain equation is K = P H T (H P H T R ) (1) The estimation equation is ˆx = ˆx K (r a T h()) (11) The error covariance equation is P = (I K H )P (12) The prediction equations are and ˆx 1 = Φˆx (13) P 1 = ΦP Φ T Q (14) The computational steps using equations (6) and (1-14) are depicted in Fig Phase omain Analyses of a PLL In this section, the proposed EKF approach is further shown to resemble a 2nd-order PLL with timevariant loop gains. Before doing this, we briefly describe a conventional 2nd-order PLL and then compare it with the proposed EKF-based PLL. The phase domain model of a conventional 2ndorder PLL is depicted in Fig. 3, which consisting of a phase detector, a loop filter and a numericalcontrolled oscillator (NCO). Although the phase detector is, in general, a nonlinear device, it is often mathematically linearied as a constant gain. That is, τ = K pd (ɛ ˆɛ ) (15) where τ denotes the phase detector output and K pd is called the phase detector gain. The conventional 2 #- #"!#3 & (#"#$ #(') * #$ ' 4!#" 5!)$ #") 1)6! 7!!" #$) &) 1 = = #" 8 =? B L M >!!" #$ % = <? > E = M O B$B = > & #"#$ #(') * #$ '," #- ) =. #$ /!'!1 > < = STA = Figure 2: Extended Kalman filter algorithm for the PLL design approach has to choose a suitable phase detector and determine the fixed constants K p and K i of the loop filter [14] such that the follows the input phase in some performance criteria. However, these tass are usually difficult and time-consuming because the nonlinear dynamics of the phase detector has been ignored. In this study, an EKF is used to completely describe the PLL with time-variant loop gains and these design parameters can be easily obtained by the Kalman filtering techniques. The phase domain model of the EKF-based PLL is derived as follows. By substituting (11) into ISSN: ISBN:

4 Proceedings of the 9th WSEAS International Conference on APPLIE INFORMATICS AN COMMUNICATIONS (AIC '9) ε ˆ ε τ p K 1 i ε ˆ ε α β Figure 3: Phase domain model for a conventional 2ndorder PLL Figure 4: PLL Phase domain model for an EKF-based the state estimation equation is given by ˆx 1 = Φˆx ΦK (r a T h()) (16) We further define K = [α β ] T, and then rewrite (16) in the following. For =, and ˆɛ 1 = ˆɛ ˆ ɛ α β (17) ˆ ɛ 1 = ˆ ɛ β (18) For = 1 and using (18), write ˆɛ 2 1 = ˆɛ 1 ˆ ɛ 1 α 1 1 β 1 1 = ˆɛ 1 ˆ ɛ β α 1 1 β 1 1 = ˆɛ 1 α 1 1 Σ 1 i=β i i (19) Finally, the estimate of ˆɛ is obtained recursively by ˆɛ = ˆɛ 2 α Σ i= β i i (2) The phase estimate equation (2) is updated by inputting the phase information through a filter with time-variant loop gains, α and β. An EKF that completely models the PLL and governs the phase update equation (2) is depicted in Fig Computer Simulations In this section, computer simulations for the conventional PLL system are given to compare with those for the proposed timing recovery system. The overall channel impulse response is assumed to be a raisecosine function with the roll-off factor α = and L = 1. The signal-to-noise ratio (SNR) is defined as 1 log E[ (r n ) 2 ]; in this example, SNR is set n 2 to be 2 db. First, assume a constant phase delay between the transmission time instant and the sampling time instant, i.e., ɛ =.2, and ɛ = for >. For the conventional PLL design, Mueller and Müller s phase detector [4] is adopted, that is, τ = r a r a and K pd = 2. After several simulation trails, set K p = and K i = for the loop filter. The result is depicted in Fig. 5 (a), and the converges for > 2 with a slightly large jittering. To have a smooth response, set K p = and K i = and Fig. 5 (b) shows the simulation result. The converges slowly for > 4. Notably, both fast phase acquisition and small jitter cannot be simultaneously met for a conventional PLL with fixed loop gains (a) (b) Figure 5: The responses of the conventional PLL system: (a) fast acquisition, and (b) small jitter ISSN: ISBN:

5 Proceedings of the 9th WSEAS International Conference on APPLIE INFORMATICS AN COMMUNICATIONS (AIC '9) For the EKF-based PLL, set the covariance matrices Q = 1 I and R =.1, where I is the identity matrix. The initial settings ˆx and P are eros and.1i, respectively. The estimated phase ˆɛ and timing offset ˆ ɛ are respectively plotted in Fig. 6(a) and (b). Note that the proposed PLL rapidly estimates the input phase and timing offset for 6 with a small jittering (a) (b) true timing offset estimated timing offset (a) (b) true timing offset estimated timing offset Figure 7: (a) The ˆɛ, and (b) the estimated timing offset ˆ ɛ Figure 6: (a) The ˆɛ, and (b) the estimated timing offset ˆ ɛ In the second simulation, the proposed PLL is further demonstrated to trac the input phase with a nonero timing offset; in this case, ɛ = ɛ ɛ, and ɛ =.2 for >. Figure 7(a) and (b) plot the ˆɛ and timing offset ˆ ɛ, and show that the estimated ones closely follow the true ones for 7. 6 Conclusions The EKF has been successfully applied for realiing a PLL, which completely describes the phase detector and loop filter. Thus, the time-variant loop gains can be obtained by the extended Kalman filtering techniques. In addition, the proposed timing recovery system has been compared with a conventional PLL system. Simulation results indicate that the proposed realiation can estimate the input phase rapidly without causing a large jittering. Acnowledgements: This wor was supported in part by National Science Council, Taiwan, under Grant No. NSC E References: [1] W. C. Lindsey and C. M. Chie, A survey of digital phase-loced loops, Proceedings of the IEEE, vol. 69, no. 4, Apr [2] J. W.M. Bergmans and H. Wong-Lam, A class of data-aided timing-recovery schemes, IEEE Trans. Commun., vol. 43, no. 4, pp , Mar [3] F. M. Gardner, A BPSK/QPSK timing error detector for sampled receiver, IEEE Trans. Commun., vol. COM-34, no. 5, pp , May [4] K. H. Mueller and M. Müller, Timing recovery in digital synchronous data receivers, IEEE Trans. Commun., vol. COM-24, no. 7, pp , May [5] A. M. Gottlieb, P. M. Crespo, J. L. ixon, and T. R. Hsing, The SP implementation of a new timing recovery technique for high-speed digital data transmission, in Proc. ICASSP, New Mexico, USA, Apr. 199, pp [6] F. M. Gardner, Phaseloc Techniques, Wiley- Interscience Publication, [7] S. C. Gupta, Phase-loced loops, Proceedings of the IEEE, vol. 63, pp , Feb ISSN: ISBN:

6 Proceedings of the 9th WSEAS International Conference on APPLIE INFORMATICS AN COMMUNICATIONS (AIC '9) [8] P. F. riessen, PLL bit synchronier with rapid acquisition using adaptive Kalman filtering techniques, IEEE Trans. Commun., vol. 42, no. 9, pp , Sept [9] G. S. Christiansen, Modeling of a PRML timing loop as A Kalman filter, in GlobeCom 94, 1994, pp [1] B. Chun, B. Kim, and Y. H. Lee, Adaptive carrier recovery using multi-order PLL for mobile communication applications, IEEE International Symposium on Circuits and Systems, vol.2, pp , [11] A. Patapoutuan, On phase-loced loops and Kalman filters, IEEE Trans. Commun., vol. 47, no. 5, pp , May [12] J. M. Mendel, Lesson in Estimation Theory for Signal Processing, Communication, and Control, Prentice-Hall, [13] Y. Bar-Shalom and X. R. Li, Estimation and Tracing: Principle, Techniques and Software, Artech House, Inc., 1993 [14] W. Li and J. Meiners, Introduction to phaseloced loop system modeling, Analog Applications Journal, pp. 5-1, May 2. ISSN: ISBN: