Driving Point Impedance Computation Applying Parallel Processing Techniques

Transcription

1 7th WSEAS Int. Con. on MATHEMATICAL METHODS and COMPUTATIONAL TECHNIQUES IN ELECTRICAL ENGINEERING, Soia, 27-29/10/05 (pp ) Driving Point Impedance Computation Applying Parallel Processing Techniques A. MEDINA, A. RAMOS-PAZ Facultad de Ingeniería Eléctrica, División de Estudios de Posgrado Universidad Michoacana de San Nicolás de Hidalgo Ediicio de la División del Posgrado de Ingeniería Eléctrica, Ciudad Universitaria, Morelia, Michoacán, MEXICO Abstract: - This contribution deals with the application o parallel processing techniques based on Parallel Processing Machine (PVM) and Multithreading to the Driving Point Impedances (DPI) o Electric Power Systems. It is demonstrated that the application o parallel processing techniques dramatically reduces the intensive computation eort required or the determination o the power system response represented by driving point impedances. Key-Words: - Driving Point Impedance, Parallel Processing, Parallel Virtual Machine (PVM), Multithreading. 1 Introduction In general, an intensive computation eort is required to reproduce the system response or a practical range o requencies or useul transient and harmonic analysis. The requency step used is directly proportional to the accuracy obtained. For practical applications, this inormation is urther processed so that the system response obtained with the driving point impedance is adequately reproduced at resonance requencies by a requency dependent equivalent, e.g. [1-3]. In this contribution two parallel processing platorms based on Multithreads [4] and PVM [5] are applied to the eicient computation o the system requency response. It is shown that as the complexity o the system increases, the application o parallel processing signiicantly reduces the computational eort required by a conventional sequential process to obtain the network requency response. This is achieved by increasing the process relative eiciency o the parallel processing. 2 Driving Point Impedance The power network requency response can be obtained by assembling, at any particular requency, its respective admittance or impedance matrix rom the individual system components. The transer unction between nodal currents and voltages appearing throughout the system busbars is represented, or any requency, by the matrix equation, I = Y V (1) The inverse o the requency admittance matrix the requency impedance matrix Z, where each diagonal element Z, impedance o node. Z is is known as driving point The combination o inductive and capacitive elements as seen rom a particular bus, can result in either series resonance or a parallel resonance. The result o a series resonance may be the presence o unexpected large amounts o harmonic currents lowing through certain network elements, whereas the result o parallel resonance may be the presence o excessive harmonic voltages across network elements [6][7]. 3 Parallel Processing Techniques Parallel processing can be deined as a orm o inormation processing where two or more processors in combination with some orm o inter-processor communication system, cooperate on the concurrent solution o a large problem [8]. The emergence o massive parallel processors and distributed computation have paved the way to the wide acceptance and application o parallel processing or the solution o problems o considerable magnitude in diverse ields.

2 7th WSEAS Int. Con. on MATHEMATICAL METHODS and COMPUTATIONAL TECHNIQUES IN ELECTRICAL ENGINEERING, Soia, 27-29/10/05 (pp ) 3.1 Parallel Virtual Machine PVM (Parallel Virtual Machine) [5] is a platorm that allows an heterogeneous network computer set to work as a large computer o multiple processors. Thus, a low cost and powerul virtual computer o multiple supercomputers can be created. PVM has several important advantages, e.g. Easy to set up. Many virtual machines can co-exist with the same hardware. The development o programs is based on message passing libraries. Supports C and Fortran. The sotware is very portable. The code source is available or ree. PVM enables users to exploit their existing computer hardware to solve much larger problems with minimal additional cost. It supports operating platorms such as Windows or LINUX. In PVM the inormation is transerred by mean a zip-send-reception-unzip protocol. This protocol is based on message passing libraries. 3.2 Multithreading Multithreading [4] is the application o lightweight subprocesses executed within a process sharing code and data segments, but with their own program counter, machine registers and stack. Global and static variables are common to all threads. 4 Parallel DPI calculation Scheme Proposed Conventionally, the computation o Z is carried-out by means o a sequential process where Z, is obtained at each requency. An accurate computation Z requires a small enough requency step size to o, be used, so that parallel and series systems resonances are appropriately reproduced. However, the requency step size is inversely proportional to the computational eort needed to obtain Z, over the entire requency range o analysis. However, the computation o Z, or = 0, 1, 2, n can take advantage rom the act that Z 0 is independent rom Z 1, which in turn is independent rom Z 2, etc. The above process independence makes ideal the application o parallel processing, since concurrent processes are used or the computation o Z over the requency range o interest. Figure 1 illustrates the parallel scheme proposed or the computation o Z. Here, a main process element collects all the inormation related to the electric network such as topology, elements and involved electric variables and parameters. This inormation is stored in a linked list rom a deined class, who contains the relevant inormation associated with each individual element. Start Data Collection Tasking distribution End Main Process Process Z 0 Z 1 Z 2 Z n Threads elements Figure 1. Proposed parallel scheme Once the electric network inormation has been collected, the main process element determines the requency range assigned to each thread or the computation o the system requency behavior, e.g. No. o requencies Frequency step Task by process element = No. o process elements (2) I the requency number is larger than the number o process elements in (2), then each process element computes more than one inverse o. However, i the number o threads is equal to the number o requencies, then each element process calculates one inverse o Y. On the other hand, i the number o element process is larger than the number requencies, then the additional threads are not used. Once the number o tasks to be carried-out by every process element is deined, the main element process sends a starting signal to the dierent threads involved in the process in the case o multithreads or executed every slave process in the case o PVM. Figure 2 illustrates the task assignment to process elements. Here, each process element builds-up the admittance matrix or a requency with the data stored in the linked list. Once the matrix has been assembled, the process element computes the inverse. The elements rom the inverse are sent to the shared memory to be stored in a common variable in the case o Multithreads or are sent to the master Y

3 7th WSEAS Int. Con. on MATHEMATICAL METHODS and COMPUTATIONAL TECHNIQUES IN ELECTRICAL ENGINEERING, Soia, 27-29/10/05 (pp ) processor (in the case o PVM) to be stored in a common variable. This variable is protected against overwriting using the mutual exclusivity mechanism, which prevents simultaneous inormation access rom multiple process elements. Start Gets initial, inal = initial Builds-up Y Calculates Y -1 Stores results in a common variable Every single process element builds-up the Y matrix using the relevant inormation o the stored circuit in a linked list o structures, which contains inormation on the reception and sending nodes, the resistance, inductance and capacitance values and inally a number representing the element arrangement. This number is used to build-up the impedance value on unction o the resistor, capacitor and inductance arrangement. Figure 4 illustrates the storage scheme used in this investigation. This scheme consists on an arrangement o pointers to a basic storage structure which contains three elements; an integer variable that represents the receiving node, a complex variable that stores the admittance value and a pointer to this structure. This pointer is used to link the dierent elements connected to a speciic busbar. Based on the storage scheme each thread builds-up the Y at the dierent requencies assigned. = + = inal End The process o biactorization is based on a LU procedure, where, a matrix is converted into the product o two matrices, a lower and an upper matrix respectively, e.g. Figure 2. Task assignment to process elements The process to calculate the inverse o Y is based on a LU biactorization process, a orward and backward process and the use o sparse matrices. The inverse o Y is build up by columns by mean a orward backward substitution process. For each column o Y a orward backward substitution process is needed, where vector b contains zero elements, with 1 in the position associated with the column to be calculated. Figure 3 illustrates the inverse process. Start i = 0 Vector b generation Set b i = 1 Y = LU (3) where the elements o the matrices L and U are calculated with (4) and (5) respectively. l = a l u i (4) u i i ik k k< i ai likuk k< i = i < l ii (5) Once the matrix is biactorizated, a orward backward substitution o (6) and (7) is used to obtain, by columns, the elements o the matrix inverse o Y. During this process a zero-valued vector is used, except or a 1 in the position o the column to be obtained. orward and backward substitutions i = n End n Y = b + l Y orward substitution (6) i i i = 0 i++ Figure 3. Inverse process o Y n 1 X = ly+ rx backward substitution (7) i ii i i = i

4 7th WSEAS Int. Con. on MATHEMATICAL METHODS and COMPUTATIONAL TECHNIQUES IN ELECTRICAL ENGINEERING, Soia, 27-29/10/05 (pp ) List representing row 0 List representing row 1 List representing row 2 Appendix I illustrates the models used or representation o the synchronous machine and the transormer [6]. GNUPLOT [9] was used or the graphical representation o the driving point impedance. Figure 4. Pointers vector to the linked lists List representing row n-1 Storage scheme using linked lists Beore starting the biactorization process an ordering scheme is used to generate the minimum number o non-zero elements. 5 Test Case For the case with PVM, the PVM3 library [5] was used whereas or the Multithreading case the PTHREAD library was applied [10]. The mutual exclusivity mechanism is applied to appropriately control the access rom multiple threads [10][11]. Figure 6 illustrates the impedance system seen rom node 2. It can be noticed that there are our points o parallel resonance, e.g. at 120, 180, 230 and 360 hz respectively. Figure 5 illustrates the test case to be analyzed. It contains ive nodes, seven transmission lines, two generation units, represented by voltage inections o 1.0 p.u. The test system data are r 1 =r 2 =r 3 =r 4 =r 5 =r 6 =10mΩ, l 1 =l 2 =l 3 =l 4 =l 5 =l 6 =20mH or the transmission lines, r 7 =20mΩ, l 7 =2mH, C 1 =200µF, l 8 =l 9 =0.69mH, C 2 =C 3 =300µF, l 10 =11.3mH and C 4 =100µF. The programming code was developed in C++ with multithreading [4]. For the case with PVM, the PVM3 library [10] was used. Two processors Mhz computer was used to executed the code associated with multithreads. The operative system used was Linux Ubuntu. The developed code reads a data ile containing the system coniguration and their parameters, the simulation data such as number o nodes, branches, harmonics, requency step and the number o threads to be used in the simulation. The parallel virtual machine used in this investigation was build using 3 two processors Mhz computers. Frequency Figure 6. System requency response, as seen rom node 2 Figure 7 illustrates the system requency response, represented by the DPI, given as the impedance magnitude versus requency, as seen rom node 4. Two parallel resonances take place at 120 and 350 Hz, respectively. A 0.1 Hz requency step size was used with a 60 Hz base requency C 1 r 7 r 1 l 1 l 7 C 2 l 8 r 6 r 4 C 3 l 9 l 2 r 2 r 3 l 4 l 6 l l 5 r 5 C 4 l 10 Figure 5. Test case Frequency Figure 7. System requency response, as seen rom node 4

5 7th WSEAS Int. Con. on MATHEMATICAL METHODS and COMPUTATIONAL TECHNIQUES IN ELECTRICAL ENGINEERING, Soia, 27-29/10/05 (pp ) Figure 8 illustrates the eect o the requency step in the driving point calculation. It can be observed that requency steps o 1.0und (und = undamental) and 0.5und do not identiy the parallel resonances associated with the analyzed electric power system, whereas the use o 0.1und and 0.01und identiy all resonances points associated with the electric power systems analyzed. Impedance Magnitud (Ohms) Harmonic Frequency Order Figure 8. Eect o the requency step in the DPI evaluation The parallel processing relative eiciency is computed as [12], E T 1 relative = (8) TP where, T 1 T p execution time with 1 process element. execution time with p process elements. Tables 1-2 illustrate the relative eiciency achieved with the application o parallel processing based on multithreading to the computation o the requency system response using two dierent requency steps. With = und (=60 Hz) no improvement is obtained in the relative eiciency or the DPI computation, since it remains in 1.0. With = 0.1 und the relative eiciency increases rom 1.0 to with ten harmonics (times the undamental requency) and to with orty harmonics, see Table I. For = 0.01 und the relative eiciency increases rom 1.0 to with ten harmonics and to with orty harmonics, see Table II. The application o a third thread does not increase the relative eiciency, since or this investigation a two processors computer was used. The relative eiciency increases in direct proportion to the size o the problem to be solved and the number o threads and processors used, as seen rom Tables 1-2. Table 1. Relative Eiciency with =0.1und Number o Number o harmonics threads Table 2. Relative Eiciency with =0.01und Number Number o harmonics o threads Table 3 illustrates the relative eiciency obtained with the use o 1-3 slave processors. It can be noted that relative eiciency increases with the increase o slave processors and requency step used. The maximum relative eiciency obtained is 2.97 or a =0.001 and with the use o 3 slave processors. Table 3. Relative Eiciency obtained with PVM and 3 slave processors Numper o slave Relative Eiciency Frequency Step processors Conclusions This contribution has introduced the application o parallel processing based on multithreading, to the ast calculation o driving point impedances in electric networks. In particular, this investigation has demonstrated that the application o parallel processing techniques signiicantly increases the relative eiciency or the computation o the requency dependent system response in the orm o driving point impedances, as seen by any system busbar. The eiciency will increase in direct proportion with the system dimension, the size o problem and the number o process elements used.

6 7th WSEAS Int. Con. on MATHEMATICAL METHODS and COMPUTATIONAL TECHNIQUES IN ELECTRICAL ENGINEERING, Soia, 27-29/10/05 (pp ) Acknowledgements The authors acknowledge the Universidad Michoacana de San Nicolás de Hidalgo (UMSNH) through the División de Estudios de Posgrado o the Facultad de Ingeniería Eléctrica the acilities granted to carry-out this investigation. A. Ramos-Paz acknowledges inancial support received by the UMSNH and CONACYT to carry-out his Doctoral studies. Reerences: [1] N.R. Watson, and J. Arrillaga, Frequency- Dependent System Equivalents or Harmonic Studies and Transient Convertor Simulation, IEEE Trans.on Power Delivery, Vol. 3, No.3, pp , July [2] A. Medina, J. Arrillaga, and N.R. Watson, Detivation o Multi-Harmonic Equivalent Models o Power Networks, Fourth International Conerence on Harmonics in Power Systems, Budapest, Hungary, Oct. 1990, pp [3] A. Abur, and H. Singh, Time Domain Modeling o External Systems or Electromagnetic Transients Programs, IEEE Trans. on Power Systems, Vol. 8, No. 2, pp , May, [4] Sun Microsystems, Inc. Multihreaded Programming Guide, [5] A. Geist, A. Beguelin, and J. Dongarra, J., PVM: Parallel Virtual Machine, MIT Press [6] J. Arrillaga. And B. C. Smith. Power System Harmonic Analysis. John Wiley and Sons. [7] IEEE Recommended Practice or Industrial and Commercial Power Systems. IEEE. [8] F. Alvarado, F.; R. Betancourt, G.T. Heydt Parallel Processing in Power Systems Computation, IEEE Transactions on Power Systems, Vol. 7 No. 2. pp [9] [online]. Avaliable: [10] Sun Microsystems, Inc. Multihreaded Programming Guide. [11] C.M. Pancake, Multithreaded Languages or Scientiic and Technical Computing, Proceedings o the IEEE, Vol.2 No. 81, pp [12] I. Foster, Designing and Building Parallel Programs Addison Wesley, Appendix I Power System Component Models Synchronous Machine Z = r h+ X h generator where X r h " d Transormer generator " d generator subtransient reactance. resistence harmonic order Z = r h+ X h where X r h t " d transormer short circuit reactance. resistence harmonic order