326 J. Comput. Sci. & Technol., May 2003, Vol.18, No.3 of single-output FPRM functions. The rest of the paper is organized as follows. In Section 2, p

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1 May 2003, Vol.18, No.3, pp J. Comput. Sci. & Technol. Power Minimization of FPRM Functions Based on Polarity Conversion XIA YinShui (ΛΠ ) 1, WU XunWei ( Ξ ) 2 and A. E. A. Almaini 1 1 School of Engineering, Napier University, 10 Colinton Road, Edinburgh EH10 5DT, UK 2 School of Information and Engineering Science, Ningbo University, Ningbo , P.R. China y.xia@napier.ac.uk; xunweiwu@mail.hz.zj.cn; a.almaini@napier.ac.uk Received April 12, 2002; revised October 11, Abstract For an n-variable Boolean function, there are 2 n fixed polarity Reed-Muller (FPRM) forms. In this paper, a frame of power dissipation estimation for FPRM functions is presented and the polarity conversion is introduced to minimize the power for FPRM functions. Based on searching the best polarity for low power dissipation, an optimal algorithm is proposed and implemented in C. The algorithm is tested on seven single output functions from MCNC benchmark circuits. The experimental results are shown in this paper. Keywords power dissipation, fixed polarity Reed-Muller function, logic synthesis, algorithm 1 Introduction Since CMOS technology is predominant in the realization of today's ICs and CMOS devices are intrinsically low-power consuming, CMOS has become the reference technology. Power dissipation in digital CMOS circuits is dominated by dynamic power dissipation, which results mainly from the charging and discharging of the node capacitances [1]. It can be modeled as (1): Power = K X i C i E i (1) where K is a constant which is determined by the technology, i is the node number, C i is the physical capacitance at the output of the node, and E i (referred to as the switching activity) is the average number of output transitions per clock cycle. The summation is taken over all nodes of the logic circuit. Both C i and E i can be optimized during design process. Up to now most researchers have focused on developing low-power techniques in AND/OR or NAND & NOR based circuits [2]. However, in certain applications, XOR realizations have advantages over the conventional AND/OR or NAND & NOR logic. XOR circuit is easier to test and may require fewer gates and interconnections [3;4]. However, applications of Reed-Muller circuits have so far not become popular due to the following two obstacles. 1) XOR gates used to have slow speed and require large silicon area to realize in comparison with OR gates. 2) The problem of optimization of Reed-Muller functions is difficult although there has been a gr eat deal of research in recent years [5;6]. With the development of new technologies and the advent of various field programmable gate array (FPGA) devices [7], the first obstacle has been solved. In programmable devices, the XOR gate is either easily realized in universal modules" or directly available. For the second obstacle, more recently, there has been some success in achieving area reduction by employing optimization techniques specifically targeted towards initial AND/XOR representations in the well known fixed polarity Reed-Muller expansion [5;6]. For low power optimization of FPRM functions, to the best of our knowledge, the only results in the literature are algorithms by Zhou and Wong [9] and Narayanan and Liu [10]. The former is for low power XOR gate decomposition, which is the special case of FPRM functions, and the latter is for the FPRM functions with the implementation of static logic. However, as will show later on, the algorithm in [10] is not optimal and can only be applied to some special FPRM functions. This paper proposes a frame to estimate power dissipation based on FPRM functions, discusses the effect of polarity on power dissipation and introduces an optimal algorithm for power minimization This work is supported in part by the National Natural Science Foundation of China under Grant No

2 326 J. Comput. Sci. & Technol., May 2003, Vol.18, No.3 of single-output FPRM functions. The rest of the paper is organized as follows. In Section 2, power estimation for FPRM functions is introduced. Section 3 presents an optimal algorithm. Finally, some experimental results are shown in Section 4 and conclusions are drawn in Section 5. 2 Power Estimation for FPRM Functions 2.1 Power Estimation Procedure Any n-variable Boolean function can be expressed canonically by the exclusive SOP form as follows. f(x n 1 ;x n 2; :::;x 0 ) = Φ 2X n 1 i=0 b i ß i (2) where the subscript i can be expressed in a binary form as i = (i n 1 i n 2 :::i 0 ), b i 2 f0; 1g, the ß- terms can be represented as ß i = _x n 1 _x n 2 ::: _x 0, and _x is a literal which can be x or μx, ρ 1; ij = 0 _x j = (3) _x j ; i j = 1 In (3), j is from 0 to n 1. The form in (2) is also known as the positive polarity Reed-Muller (PPRM) form if all the variables are in true forms. PPRM forms can be extended to FPRM forms with any fixed polarity p, p = (p n 1 p n 2 :::p 0 ), where variables can only be either true or complemented, but not both. If a binary bit of p, p j, is 0 (or 1), then the corresponding variable is in the true (or complemented) form. Hence, there are 2 n polarities for an n-variable function. Correspondingly, there are 2 n FPRM forms. Any FPRM form can be implemented by AND gates and XOR gates. Before technology mapping, conventionally, all multi-input AND gates and XOR gates need to be decomposed into a tree of two input gates. The tree is defined by the following definition. Definition 1. Let T = (V;E) represent a decomposition tree, and p r (v), for any v 2 V, denote the output signal probability of node v. Each node has two children. The primary inputs are called leaves of the tree and the primary output is called the root of the tree. Furthermore, each primary input signal to a tree is treated as a random variable and its probability is defined as follows. Definition 2. Signal probability for signal x is defined as the probability of x being 1. To estimate the power dissipation of a tree, according to (1), C i and E i need to be known. Each node in the tree corresponds to a two-input gate. Suppose C i is constant for each two-input gate. Then, the only parameter that needs to compute is E i. Under the assumptions of zero delay model with temporal and spatial independence [9;10], given input signal probabilities and a decomposition tree, the probabilities of internal signals can be computed according to the following definitions of XOR and AND operators. Definition 3. For XOR operator: f(x 1 ;x 0 ) = x 1 Φ x 0 = x 1 x 0 + x 1 x 0, and the probability of f(x 1 ;x 0 ) is [9] : P r;f = P r (p r;x1 ;p r;x0 ) = p r;x1 + p r;x0 2p r;x1 p r;x0 (4) Definition 4. For a two-input AND operator: f(x 1 ;x 0 ) = x 1 x 0, the probability of f(x 1 ;x 0 ) is [1] : P r;f = P r (p r;x1 ;p r;x0 ) = p r;x1 p r;x0 (5) The calculation of the corresponding switching activity depends on whether the circuit is implemented in dynamic logic or static logic. The main difference between them is that dynamic CMOS works using a precharging circuit. The output of a circuit can be precharged high or low then the result value is evaluated. There are two implementation models, which are precharged to 0 or 1 and evaluated to the result value. Take the former as an example, that is, if a gate output is first precharged to 0 and then evaluated, the switching activity for gate i will be E i = 2P r;i (6) For static logic, E i = 2P r;i (1 P r;i ) (7) Given an n-input FPRM function with primary input signals I = fx n 1 ;x n 2 ;:::;x 0 g and corresponding signal probabilities fp r;xn 1 ;p r;x n 2 ;:::, p r;x0 g, based on the above discussion, the procedure for the power estimation of an FPRM function is as follows. 1) Given an n-variable FPRM function and its primary input signal probability set, construct a tree of two input AND gates and XOR gates; 2) Compute the output probability for each gate using (4) and (5); 3) Compute the node switching activity using (6) or (7); 4) Compute the total power dissipation using (1).

3 XIA Y S et al.: Power Minimization of FPRM Functions 327 However, for a given FPRM function with the input signal probability set, how the function is decomposed can have a significant impact on the amount of power dissipation. This is referred to as low power gate decomposition. 2.2 Low Power Gate Decomposition Low power gate decomposition can be described as follows. Given input signal probabilities, construct a tree of two input gates such that the total switching activity is minimized. The problem of gate decomposition has been extensively studied [8 10]. In [8], AND gate decomposition was discussed. For dynamic logic, it is found that a modified Huffman's algorithm gives optimal solutions. The modified version of Huffman's algorithm is called Mini-Huffman algorithm and can be described as follows. Algorithm 1 (Mini-Huffman Algorithm) [8]. Start with all the input signals; combine the two signals of minimum probabilities and substitute the two signals with a new signal; continue the process until there remains only one signal. Take a simple example to explain the algorithm. Forthree inputs (x 2 ;x 1 ;x 0 ) with corresponding signal probabilities of 0.9, 0.45 and 0.1 respectively, Fig.1(a) shows the above algorithm applied to decompose a three-input AND gate into a tree of twoinput gates in dynamic logic. The switching activity is based on (6). In [9], the authors analyzed some optimal properties and proposed an algorithm to solve the problem of lower power XOR gate decomposition in dynamic logic as follows. greater than 0.5. Then, combine them pairwise from the largest to the smallest. Finally, iteratively combine the two signals with the smallest probabilities until there is only one signal. Fig.1(b) shows the decomposition based on Algorithm 2. The switching activity is Hence, an FPRM function with multiple variables can be implemented using trees of two-input AND gates and a tree of two-input XOR gates. Given the input signal probability set, the switching activity can be computed using the above algorithms. 3 Polarity-Based Power Minimization of FPRM Functions For an n-variable function, there are 2 n polarities and correspondingly there are 2 n FPRM forms, which results in different numbers of ß-terms. If implemented as a tree, then the different numbers of ß-terms will have different tree sizes and result in different power dissipation situations. Hence, power minimization of FPRM functions can be implemented by searching for the best polarity, which has the lowest switching activity, among 2 n polarities. Based on the analysis of XOR operation and assuming that both the signals and their complements are available, Narayanan and Liu claimed that they use the selection of polarity vectors to solve low power logic synthesis for XOR-based circuits. Algorithm 3 (Narayanan and Liu's Algorithm) [10]. Let k be the number of primary inputs to the XOR tree with probabilities greater than 0.5. If k is even, replace all k inputs with their respective complements. If k is odd, then replace any k 1 inputs with their respective complements. Then simply use the Huffman algorithm to build the optimal tree. However, this algorithm does not deal with the reduction of tree size and only works for some special cases of FPRM functions. For example, consider two five-variable problems, which share the same input signal probabilities: fp r;x4 ;p r;x3 ;p r;x2 ;p r;x1 ;p r;x0 g = f0:1; 0:3; 0:7; 0:8, 0:9g. (9): Two function forms are shown in (8) and Fig.1. (a) Multi-input AND gate decomposition in [8]. (b) Multi-input XOR gate decomposition in [9]. Algorithm 2 (Zhou and Wong's Algorithm) [9]. First, sort the input probabilities which are f(x 4 ;x 3 ;x 2 ;x 1 ; μx 0 ) = x 1 μx 0 Φ x 2 μx 0 Φ x 4 Φ x 4 x 3 μx 0 (8) f(x 4 ;x 3 ;x 2 ;x 1 ; μx 0 ) = x 1 μx 0 Φ x 2 μx 0 Φ x 4 x 1 Φ x 4 x 3 μx 0 (9) Obviously, Algorithm 3 works for the function in (8). If x 1 and x 2 in (8) are replaced by their

4 328 J. Comput. Sci. & Technol., May 2003, Vol.18, No.3 complements, then an alternative representation of the function is: f(x 4 ;x 3 ; μx 2 ; μx 1 ; μx 0 ) = μx 1 μx 0 Φ μx 2 μx 0 Φ x 4 Φ x 4 x 3 μx 0 (10) which has the same size and the same logic functionality as those in (8). However, if the same algorithm is applied to the function in (9), the function will be changed into: f(x 4 ;x 3 ; μx 2 ; μx 1 ; μx 0 ) = μx 1 μx 0 Φ μx 2 μx 0 Φ x 4 μx 1 Φ x 4 x 3 μx 0 (11) which has the functionality different from the function in (9). This is easily tested by applying the formula μx = 1 Φ x to x 2 and x 1 in (9). Then, the expression in (9) results in (12) f(x 4 ;x 3 ; μx 2 ; μx 1 ; μx 0 ) = μx 1 μx 0 Φ μx 2 μx 0 Φ x 4 Φ x 4 μx 1 Φ x 4 x 3 μx 0 (12) Hence, the algorithm does not work well with the function in (9). In addition, the algorithm only tries one of 2 n polarities because given input signal probabilities the selected polarity is fixed. For example, for a three-input problem shown in Fig.1, the selected polarity is zero while for a five-input problem, the selected polarity is 7. Therefore, the selected polarity may not be optimal. In order to find the best polarity, which has the lowest switching activity, among 2 n polarities, a polarity conversion algorithm is needed, which can convert an FPRM function from one polarity to another. 3.1 Polarity Conversion For area minimization, various methods have been developed, which can be classified into two categories [11] : 1) Gray code: Sequentially search 2 n polarities to find the best one which has the minimum number of products. Memory requirement is O(2 n ) while the computation time is O(4 n ). 2) Extended truth vector: Using an extended truth vector and a weight vector, obtain the number of products for 2 n different expansions simultaneously. Both memory requirement and the computation time are O(3 n ). Recently, an exact method was reported [6] to find the best polarity targeting area minimization based on on-set coefficients by gray code, which is suitable for large functions. Memory requirement and the computation time are O(M) and O(2 n M) respectively, where M is the average number of onset coefficients. This method is used here to implement function polarity conversion. For convenience, some definition is given as follows. Definition 5. Two integers can be expressed by binary n-tuples, i = fi n 1 i n 2 :::i 0 g; j = fj n 1 j n 2 :::j 0 g. If i k > j k for all k, 0 6 k 6 n 1, then i covers j or j is covered by i. Algorithm 4 (Wang's Algorithm) [6]. Given an on-set Reed-Muller coefficient set R p for an n- variable Boolean function with polarity p, a coefficient set R q with any other polarity q can be achieved through the following operations on R p itself, where p ^ q = r (^ is a bitwise operator). 1) For any coefficient i in the set R p, if i does not cover r, then i is an element of R p. Leave i in the set. If i covers r, search the set R p for the coefficient (i r). If there is such a coefficient, then delete coefficient (i r) from the set R p. Otherwise, if there is not such a coefficient, then add coefficient (i r) to the set R p. 2) The new set obtained in step 1) is the on-set Reed-Muller coefficient set with polarity q. Using the above polarity conversion algorithm, the low power implementation of FPRM functions can be described as follows. Low power FPRM function implementation: Given an n-input PPRM function with primary input signals I = fx n 1 ;x n 2 ;:::;x 0 g and corresponding signal probabilities fp r;xn 1, p ;:::;p r;xn 2 r;x 0 g, two input AND gates and two input XOR gates are used to construct a tree T = (V;E) with p r;xn 1, p ;:::, and p r;xn 2 r;x 0 as its leaves. Search for the best polarity such that (13) and (14) are minimized for dynamic logic and static logic respectively. For dynamic logic, For static logic, E SW T E SW T = X i2v = X i2v 2P r;i (13) 2P r;i (1 P r;i ) (14) Here E SW T is the total switching activity and P r;i is the signal probability of an internal node. 3.2 Proposed Algorithm Based on the above discussion, a new algorithm for minimizing FPRM function power dissipation is proposed as follows.

5 XIA Y S et al.: Power Minimization of FPRM Functions 329 Algorithm 5. Given an on-set Reed-Muller coefficient set R p of a single-output FPRM function with the input signal probability set under polarity p, let one real variable and one integer variable, SACost and AreaCost, represent the total switching activity and area cost (measured by the number of ß-terms) under polarity p, and let one real variable and two integer variables, BestSACost, BestArea- Cost and BestPolarity, represent the lowest total switching activity, area cost and the polarity corresponding to the lowest total switching activity, respectively. Then, for any i, 0 < i 6 2 n 1, carry out the following steps: 1) Generate a polarity q i in gray code order, that is adjacent to q i 1. Let r = q i ^ q i 1. 2) Pass R qi 1 and r to Algorithm 4 to get the new on-set coefficient set R qi. 3) Construct an optimal tree of two input AND gates using Algorithm 1 for each ß-term in the FPRM function. Compute the switching activity for all ANDtrees and store it into SACost and save the primary output signal probabilities of AND-trees into an array called ANDOutProb[ ]. 4) Taking the signal probabilities in ANDOutProb[ ] as the primary input signal probabilities, construct an optimal tree of two input XOR gates using Algorithm 2. Compute the switching activityofthe XOR-tree and add it to SACost. 5) If SACost is less than BestSACost, then Best- SACost, BestAreaCost and BestPolarity are substituted by SACost, AreaCost and q i respectively. 6) Output (BestPolarity ^ p) that is the best polarity with BestSACost and BestAreaCost. Example 1. A three-variable function, f(x 2 ;x 1, x 0 ), with corresponding input signal probabilities (0:1; 0:45; 0:9) is shown in two-level FPRM format in (15). f(x 2 ;x 1 ;x 0 ) = x 0 Φ x 1 x 0 Φ x 2 x 1 x 0 (15) Obviously, the function representation is under polarity 0. The on-set Reed-Muller coefficient set R 0 is (1, 3, 7). First, construct an optimal tree of two input AND gates using Algorithm 1 for each ß-term in the FPRM function and compute the switching activity for all AND-trees and store it into SACost and save the primary output signal probabilities of AND-trees into an array called ANDOutProb[ ]. For this example, ß 1 = x 0, ß 3 = x 1 x 0, ß 7 = x 2 x 1 x 0 and corresponding AND trees are shown in Fig.2(a). The switching activity is SACost = The primary output signal probabilities of AND-trees are ANDOutProb[0] = 0.9, ANDOutProb[1] = and ANDOutProb[2] = Then, take the signal probabilities in ANDOut- Prob[ ] as the primary input signal probabilities, construct an optimal tree of two input XOR gates using Algorithm 2, compute the switching activity of the XOR-tree and add it to SACost. The XOR tree is shown in Fig.2(b) and its switching activity is added to SACost. Let SACost, , under polarity 0 be BestSACost, BestAreaCost be 3 and polarity 0 be BestPolarity. Fig.2. Decomposition of AND trees and XOR tree. (a) AND trees. (b) XOR tree. Generate polarity 1 in gray code order, 001. Let r = 001 ^ 000 = 1. Pass R 0 = (1; 3; 7) and r = 1 to Algorithm 4 to get the new on-set coefficient set R 1 = (0; 1; 2; 3; 6; 7). Obtain SACost = Since SACost is smaller than BestSACost, update BestSACost = , BestAreaCost = 6 and Best- Polarity = 1. Repeat this procedure till polarity 7. Finally, find that the BestPolarity is polarity 2, BestSACost is and BestAreaCost is 3. 4 Experimental Results The proposed algorithm has been implemented in C and compiled by the GNU C compiler. The time complexity for mini-huffman is O(n log n) [9] while that for polarity conversion is O(M2 n ) [6]. Hence, the proposed algorithm has a time complexity of O(M2 n n log n) where n is the number of variables and M is the average number of on-set coefficients. The algorithm is tested on a personal computer with a PIII 550MHz CPU and 64MB RAM under Linux operating system. Seven single-output circuits with input size from 8 to 16 input variables from MCNC benchmarks are used to test the proposed algorithm.

6 330 J. Comput. Sci. & Technol., May 2003, Vol.18, No.3 The algorithm proposed in [12] is used to convert the test circuits directly from two-level PLA format to two-level FPRM format with polarity 0. Then, the proposed algorithm will work with the two-level FPRM format circuits. Given a set of input signal probabilities, the best polarity is searched and its corresponding switching activity and area are found, where area is measured by the number of ß-terms. Twenty one input signal probabilities are generated under randomly selected seed number 80, which are 0.15, 0.97, 0.48, 0.10, 0.24, 0.16, 0.60, 0.96, 0.78, 0.56, 0.26, 0.74, 0.53, 0.87, 0.37, 0.39, 0.37, 0.41, 0.08, 0.25, 0.47 respectively. For different input sizes, the input signal probabilities are chosen from the left to the right in the above list. For example, for three inputs (x 2, x 1, x 0 ), the signal probabilities are 0.48, 0.97, 0.15 while for four inputs (x 3 ;x 2 ;x 1 ;x 0 ), they are 0.10, 0.48, 0.97, 0.15, and so on. Table 1 shows the experimental results for seven circuits. To see the efficiency of the algorithm, the switching activity and area under polarity 0 are also listed in the same table for comparison. In Table 1, column 1 shows the circuit name while column 2 shows the number of inputs (IN#) and the number of product terms (p#); columns 3 and 4 show the switching activity (SA 0 ) and area (Area 0 is the number of ß- terms) under polarity 0 while columns 5, 6, 7 and 8 show the best polarity, switching activity (SA b ), area (Area b ) and CPU time for the best polarity using the proposed algorithm, respectively; columns 9 and 10 show the improvement percentage of the switching activity and area under the best polarity compared with the case of polarity 0. The improvement percentage of switching activities is defined as follows: Improvement = SA 0 SA b SA 0 % (16) while the area improvement is similarly defined in (17). Improvement = Area o Area b Area 0 (17) From the results reported in Table 1, it is found that the switching activities can be improved significantly for all seven circuits compared with those under polarity 0, and the improvement can be as high as 91.5%. The average reduction of switching activities is 73.2% while the average area reduction is 22.0% for all seven circuits. For five cases of seven circuits, both area and switching activity are reduced while for one case the switching activity reduction is traded off with the area increases. For each circuit, 10 sets of input probabilities are randomly generated and the above algorithm is run. For each instance X, let Opt(X) represent the optimal solution under the best polarity and S(X) be the solution with polarity 0. The following parameter defined in (18) is used to measure the performance of the algorithm. R = S(X) Opt(X) S(X) (18) From the definition in (18), obviously, the higher the rate R, the better the performance of the algorithm. For each circuit, among 10 problems, the maximum ratios and the average improvement ratios of switching activity and area are computed, Table 1. Best Polarity and Switching Activity for Low Power Decomposition Name IN#/p# Polarity 0 Best Polarity Improvement (%) SA 0 Area 0 Polarity SA b Area b Time (s) SA Area Newwill 8/ Newtag 8/ sym10 10/ :4 xor5 5/ ο sym 9/ life 9/ t481 16/ Average improvement (%) Table 2. Reduction Ratios of Area and Switching Activity Name MaxSWR (%) MaxAreaR (%) AvergSWR (%) AvergAreaR (%) Newill Newtag Sym : :4 xor sym life t

7 XIA Y S et al.: Power Minimization of FPRM Functions 331 which are represented by MaxSWR, MaxAreaR, AvergAreaR and AvergSWR, respectively. The results are shown in Table 2. 5 Conclusions A frame of power dissipation estimation for FPRM functions has been presented. Using the polarity conversion under the assumption that both signals and their complements are available, a solution to minimize power dissipation for single-output FPRM functions is proposed. The time complexity of the proposed algorithm is O(M2 n n log n). Although the dynamic logic is used to explain how the algorithm works, it should be pointed out that the algorithm can be applied to static logic as long as the calculation formula of switching activity in (6) is substituted by the one for static logic in (7). In our future work, the proposed algorithm will be extended to solve multioutput FPRM functions targeting low power. References [1] Roy K, Prasad S C. Low-Power CMOS VLSI Circuit Design. John Wiley & Sons, INC., USA, [2] Panda R, Najm F. Technology decomposition for lowpower synthesis. In IEEE Custom Integrated Circuits Conference, Santa Clara, California, USA, May 3-5, 1997, pp [3] Almaini A E A. Electronic Logic Systems. Third Edition, Prentice Hall, UK, [4] Reddy S. Easily testable realization for logic functions. IEEE Trans. Computers, 1972, (11): [5] Mckenzie L. Logic synthesis and optimization using Reed-Muller expansions [Dissertation]. Napier University, [6] Wang L. Automated synthesis and optimization of multilevel logic circuits [Dissertation]. Napier University, [7] Brown S, Francis R, Vranesic Z G. File-Programmable Gate Arrays. Kluwer Academic Publisher, Boston, [8] Tsai C, Marek-Dadowska M. Multilevel logic synthesis for arithmetic functions. ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 3 7, 1996, pp [9] Zhou H, Wong D F. Optimal low power XOR gate decomposition. ACM/IEEE Design Automation Conference, Los Angeles, USA, June 5 9, 2000, pp [10] Narayanan U, Liu C L. Low power logic synthesis for XOR based circuits. IEEE International Conference on Computer Aided Design, San Jose, USA, June 9 13, 1997, pp [11] Sasao T, Fujita M. Representations of Discrete Functions. Kluwer Academic Publishers, USA, [12] Wang L, Almaini A E A. Fast conversion algorithm for very large Boolean functions. Electronics Letters, 2000, 36(16): XIA YinShui received the B.S. degree in physics from Hangzhou University in 1984 and the M.S. degree in electronic engineering from Hangzhou University in Now he is a Ph.D. candidate in electronic engineering at Napier University. Prior to studying at Napier, he had been a visiting scholar at King's College London and worked as an associate professor and vice dean at the Department of Physics of the Ningbo University. His current research interests are in the area of computer-aided design of digital IC's, specially in the design of low power systems, algorithms for the automatic synthesis of low-power circuits. He has published over 30 papers in IEE proceedings, Electronics Letters, Journal of Electronics, etc. WU XunWei graduated from Physics Department, Hangzhou University in Now he is a professor and the executive director of the School of Information Science and Engineering, Ningbo University, China. He is the author of the book entitled Design Principles of Multiple-Valued Logic Circuits" and more than two hundred papers. Prof. Wu isa Senior Member of IEEE and the vice dean of MVL & FL Society, the China Computer Federation. His main research interests include multiple-valued logic circuit, digital circuits design at switch level, and low power digital circuits. A. E. A. Almaini is a professor of Electronic Engineering and head of the Digital Techniques Research Group which he founded at Napier University in Since then he published three text books, Electronic Logic Systems (3rd ed.), and over 60 papers on various aspects of logic designs in IEEE and IEE journals. His research interests include the synthesis and optimisation of logic circuits, electronic computer aided design, error control coding and medical electronics. He refereed for IEEE Transaction on Computers, IEEE Transaction on Circuits & Systems, IEE Proceedings on Computers & Digital Techniques, IEE Proceedings on Circuits Devices and Systems, IEE Electronic Letters, Microprocessors and Microsystems, International Journal of Electronics and the Computer Journal. Dr. Almaini is a Fellow of the IEE and, at different times, served as member of the IEE Professional Group on Circuits & Systems, Chairman of the IEE Professional Group on Microelectronics and Semiconductor Devices and member of the IEE Electronics and Communication Division.