An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles

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1 211 eon nternational Conferene on Networking an Computing An Algorithm to emove Asynhronous Ms in Ciruits with Cyles M. Nazrul slam Monal, Koji Nakano, an Yasuaki to Department of nformation Engineering, Hiroshima University 1-4 Kagamiyama, Higashi-Hiroshima, , Japan Astrat Fiel rogrammale Gate Arrays (FGAs) are a ominant implementation meium for igital iruits whih are use to eme a iruit esigne y users instantly. FGAs an e use for implementing parallel an harware algorithms. Most of FGAs have Configurale Logi Bloks (CLBs) to implement ominational an seuential iruits an lok AMs to implement anom Aess Memories (AMs) an ea nly Memories (Ms). Ciruit esign that minimizes the numer of yles is easy if we use asynhronous rea operations. However, most of FGAs support synhronous rea operations, ut o not support asynhronous rea operations. The main ontriution of this paper is to provie one of the potent approahes to resolve this prolem. We assume that a iruit using asynhronous Ms esigne y a non-expert or uikly esigne y an expert is given. ur goal is to onvert the iruit with asynhronous Ms into an euivalent iruit with synhronous ones. The resulting iruit with synhronous Ms an e emee into FGAs. nex Terms FGA, ea only memories, Asynhronous rea operations, Ciruit rewriting algorithm.. NTDUCTN An FGA is a programmale VL (Very Large ale ntegration) in whih a harware esigne y the users an e emee uikly. Typial FGAs onsist of an array of programmale logi loks (slies), memory loks, an programmale interonnets etween them. The logi lok ontains four-input logi funtions implemente y a LUT an/or several registers. Using four-input logi funtions, registers, an their interonnetions, any ominational iruit an seuential logi an e implemente. The memory lok is a ual-port AM whih an perform rea an/or write operations for a wor of ata to two istint or same aresses in the same time. Usually, the ual-port AM supports synhronous rea an synhronous write operations. The rea an write operations are performe at the rising eges. The ualport AM outputs ata of a speifie aress after the rising ege. imilarly ata is written to a speifie aress at the rising ege of if write enale is high. Design tools are availale to the users to eme their harware logi into the FGAs. ome iruit implementations are esrie [1], [2], [4], [9] to aelerate omputation. n this paper, we fous on the asynhronous an synhronous rea operations of memory loks as follows: Asynhronous rea operation The memory lok outputs the ata speifie y the aress given to the aress port. When the aress value is hange, the output ata is upate immeiately within some elay time. n other wors, the output ata port always outputs M [], whihis the ata store in the input aress value. ynhronous rea operation Even if the aress value is hange, the output ata is not upate. The output ata is upate ase on the aress value at the rising ege of. More speifially, the output ata port outputs M [ ],where is the aress ata at the previous point of rising ege. Let AMs an Ms enote Ms with asynhronous an synhronous rea operations, respetively. n general, the iruit esign is simpler an easier to the esigners, in partiular to the non-expert iruit esigners if AMs are availale. n asynhronous rea operation, the value of a speifie aress an e otaine immeiately. However, in synhronous rea operation, one yle is reuire to otain it. Nevertheless, lok AMs emee in most of the urrent FGAs o not support asynhronous rea operation for inreasing its operating freueny. A iruit implementation with AMs is etter than Ms implementation, eause of less power onsumption, easy to esign et. But it has some prolems like small in size so that it oes not support the esigner s eman, more expensive, an less speey [3], [5], [6]. To ut the istriution power, an asynhronous iruit esign in FGAs is very muh suitale, esrie in [7], [1], [11]. However, it is not supporte y the urrent FGAs. n the other han, a iruit implementation with Ms is ominating the moern igital iruit esign inustry, eause it supports the moern FGA arhiteture although it has some rawaks to esign like istriution, more power onsumption et [3], [6]. o we shoul use Ms when we nee a funtion of Ms. The main ontriution of this paper is to present a iruit rewriting approah that onverts an asynhronous iruit onsisting Cominational Ciruits (s), egisters (s), an Ms with asynhronous rea operations (AMs) into an euivalent synhronous iruit onsisting Cominational iruits (s), egisters (s), an Ms with synhronous rea operations (Ms). Note that, most of the urrent FGAs support synhronous rea operation, ut o not support asynhronous one. We are /11 $ EEE D 1.119/CNC

2 thinking the following senario to use our iruit rewriting algorithm: ffl An asynhronous iruit esigne y a non-expert, or uikly esigne y an expert is given. ffl ur iruit rewriting algorithm onvert it into an euivalent synhronous iruit. ffl The resulting synhronous iruit an e implemente in FGAs. n other wors, esigners an esign a iruit for FGAs uner the assumption of asynhronous rea operation, whih is simpler an easier than one with synhronous rea operation. For the reaer s enefit, we will show a simple example illustrating that the iruit esign is simpler if AMs are availale. uppose that for an input X, we nee to ompute X n = X n 1 + f (X n 1 ) for every n 1. We assume that the funtion f is ompute using a M. More speifially, we use a M suh that aress i is storing a value of f (i). Figure 1 (a) illustrates a iruit with an AM to ompute X 1 ;X 2 ;::: for input X.AnAMisusetoomputethe value of f (X n ) for a given X n. t shoul e lear that this iruit outputs X 1 ;X 2 ;::: in every yle. Figure 1 () shows a iruit with an M. ine one yle is neessary to rea the value of f (X n ) for input X n, we nee to insert a register to synhronize two inputs X n an f (X n ) of the aer as illustrate in the figure. This iruit outputs X 1 ;X 2 ;::: in every two yles. Hene, the iruit in Figure 1 () nees oule yles over the iruit in Figure 1 (a). Using our algorithm to the iruit in Figure 1 (a), we an otain the iruit in Figure 1 () automatially. n the iruit with an M in Figure 1 (), X 1 ;X 2 ;::: is output in every yle. Thus, the timings of the iruits in Figure 1 (a) an () are iential. n our previous paper [8], we have presente a iruit rewriting approah for iruits represente y a irete ayli graph (DAG), whih has no irete yle. Figure 2 (1) illustrates an example of a DAG. This graph has 3 input noes an 3 output noes, eah of whih orrespons to input ports an output ports of the iruit, respetively. The other internal noes orrespons to iruit elements suh as ominational iruits, registers, an Ms. The presente iruit rewriting approah onverts a iruit with ominational iruits, registers an AMs represente y a DAG into an euivalent AM-free iruit with ominational iruits, registers an Ms. However, the iruit rewriting approah presente in [8] has a strit restrition in terms of input iruits. t works only for a iruit whose unerlying graph is a DAG, illustrate in Figure 2 (1). Although most of pratial iruits have yles, it an not hanle suh iruits. The main ontriution of this paper is to moify the iruit rewriting algorithm, presente in [8] to proess pratial iruits with yles. More speifially, our new iruit rewriting algorithm an onvert any iruit represente y a irete reahale graph (DG), illustrate in Figure 2 (2). A irete reahale graph is a irete graph suh that, for every internal noe, there exists a irete path from an input noe to an A B C D G J M nput noes E H K N F L N A B C D G J M nput noes E H K N F L N utput noes utput noes (1) Direte Ayli Graph (DAG) (2) Direte eahale Graph (DG) Fig. 2. A irete ayli graph(dag) an a irete reahale graph(dg) output noe whih inlues it. Note that, one noe an/or one irete path may appear twie or more in a irete path. For example, (B; E; H; ; F; E; H; K; N; ) is a irete path. t shoul not have any iffiulty to onfirm that, every internal noe in Figure 2 (2) is inlue. Clearly, a lass of the DG inlues that of the DAG. Also, almost all pratial iruits an e represente y a DG. f there exists a noe that is not in the irete path from an input noe to an output noe, the irete graph is not a DG. However, the orresponing iruit element to suh noe makes no sense. Conseuently, we an say that our new iruit rewriting approah an hanle almost all pratial iruits with ominational iruits, registers, an AMs. This paper is organize as follows: etion riefly reviews the iruits an their euivaleny. n etion, we esrie our rewriting algorithm, iruit graph an also explain the euivaleny for our rewriting rules. For the reaer s enefits, etion V shows how our iruit rewriting algorithm works for iruit graphs. etion V presents the proof of the orretness of our rewriting algorithm. Finally etion V onlues this work.. CCUT AND THE EQUVALENCE Let us onsier a synhronous seuential iruit that onsists of input ports, output ports, ominational iruits (s), registers (s), ea nly Memories (Ms), a gloal input (), an a gloal input (). 78

3 X X X AM f (Xn) M f (Xn) M f (Xn) Xn Xn Xn (a) A iruit with an AM () A iruit with an M () The onverte iruit with an M y a non-expert Fig. 1. An example of iruits using an AM an an M A ominational iruit () is a network of funamental logi gates with no feeak. o, it an ompute Boolean funtions represente y Boolean formulas, suh as F = A B + B C an G = B C as illustrate in Figure 3. ne inputs are given, the outputs are ompute in small elay. -it register () A B C M AM F G Fig. 3. An example of a ominational iruit (). A register has a input an a input as illustrate in Figure 4. t an store fixe its of ata. f is 1, then the -it ata is initialize y. f is, the store ata is upate y the value given to the input port at every rising ege. The ata store in the register is always output from port. A M (ea nly Memory) has a (aress) input an a ata output as illustrate in Figure 4. t is storing 2 wors suh as M [], M [1], :::, M [2 1], where is the numer of aress its. We eal with two types of Ms in terms of rea operations as follows: Fig. 4. A register (), a synhronous M (M) an an asynhronous M (AM). ffl ffl ynhronous M (M) An M has a input an a input. f is 1 then the store value is initialize y. The rea operation is performe at every rising ege when is. The output is the value of M [] at the latest rising ege. Asynhronous M (AM) An AM has no input an no input. The value of M [] is ontinu- 79

4 ously output from port. The Figure 5 shows a timing iagram of reaing operations of the, M, AM an N (Negative egister). n the figure, time, 1, 2, ::: orrespon to rising eges of the perioi input. nitially gloal is 1 an it rops to just efore time. Data, 1, 2, ::: are given to the input port. The value of output, of an M is at time. Also, at time 1, 2, ::: the values of output, of an M are, 1, 2, ::: an M [ ], M [ 1 ], M [ 2 ], :::, respetively. For the AM, the ata M [ ], M [ 1 ], M [ 1 ], ::: are taken from the output port, immeiately at time, 1, 2, :::, respetively. n urrent FGAs, an M an e implemente in emee lok AMs. However, an AM is implemente in LUTs, whih are very ostly. Hene, we shoul use Ms when we nee a funtion of Ms. n the other han, AM is easy to use, eause we an get output ata from the AM immeiately. time ffl egister () Let i enote an input value given to an input port at time i (i ). The output seuene is esrie as follows: : h; ; 1 ; 2 ;:::i ffl ynhronous an Asynhronous Ms (Ms an AMs) Let M [j] enote the value store in aress j (j ) of the M. The output seuenes of M an AM are as follows: M: h;m[ ];M[ 1 ];M[ 2 ];:::i AM: hm [ ];M[ 1 ];M[ 2 ];M[ 3 ];:::i n this paper, we assume that a fully synhronous iruit has ata inputs, ata outputs, a gloal input, a gloal input, ominational iruits (s), registers (s), Ms, AMs, an their interonnets. The reaers shoul refer to Figure 6 for illustrating an example of a fully synhronous iruit. The gloal an the gloal are iretly onnete to the input ports an the input ports of all s an Ms. Also, we assume that a iruit has yles. ata input AM AM (M) () 1 2 M [] M [1] [2] (AM) M [] M [1 M [2] M [3] (N) Fig. 5. A timing hart of a register (), an M, an AM an a negative register (N). ata output We will esrie a ehavior of a iruit element using a seuene of output at every rising ege for the perioi ( is inverte into a fixe freueny), an initial (initially, is 1 an rops to efore the first rising ege) as illustrate in Figure 5. The ehavior of eah iruit element is esrie y the output seuenes as follows: ffl Cominational Ciruit () For simpliity, we assume 3-input 2-output ominational iruit whih is shown in Figure 3. There is no iffiulty to exten the efinition for general m-input n-output ominational iruit. We assume that, at time i (i ), a i, i,an i are given to the 3 input ports A, B, anc. Letf an g e the two funtions with three arguments that etermine the value of output ports F an G. The output seuenes of F an G are as follows: (F):hf (a ; ; );f(a 1 ; 1 ; 1 );f(a 2 ; 2 ; 2 );:::i (G):hg(a ; ; );g(a 1 ; 1 ; 1 );g(a 2 ; 2 ; 2 );:::i Fig. 6. An example of a fully synhronous iruit with yle an the orresponing iruit graph with potentiality. Let us efine euivalene of two fully synhronous iruits for the perioi an initial. We say that two iruits X an Y are an euivalent if, for any input seuene, the output seuenes are the same exept for first several outputs. For the reaer s enefit, we will show an example of the euivalene. Let us onsier a iruit +AM, that is, the output of is onnete to the input of AM as illustrate in Figure 7. We also onsier a iruit AM+, in whih the output of AM an the input of are onnete. For the perioi with initial, the output seuenes of M, +AM, an AM+ are as follows: M: h;m[ ];M[ 1 ];M[ 2 ];:::i +AM: hm [];M[ ];M[ 1 ];M[ 2 ];:::i 8

5 AM+: h;m[ ];M[ 1 ];M[ 2 ];:::i ine these three iruits have the same output in time 1, 2, :::, they are euivalent. Note that the outputs in time are not eual. n this paper, we ignore first several yles when we etermine the euivaleny of the iruits. uppose that a iruit X with AMs is given. The main ontriution of this paper is to show ffl a neessary onition suh that an AM-free iruit, Y an e generate, whih is euivalent to X, an ffl an algorithm to erive Y if the neessary onition is satisfie. We will introue a negative register (N), whih is a nonexistent evie use only for showing our algorithm to erive Y an relate proofs. This is originally introue in our previous paper [8]. eall that, a regular register lathes the input at the rising ege. A negative register lathes a future input. The Figure 5 also shows a timing iagram of a negative register (N). An N lathes the value of input at the rising ege of two yles later as illustrate in Figure 5. Thus, the N has the following output seuene for a perioi with an initial is as follows: N: h 1 ; 2 ; 3 ;:::i. n our algorithm to erive an AM-free iruit Y, iruits with Ns will e use as interim results.. CCUT GAH AND EWTNG ULE We simply use a irete graph to enote the interonnetions of a fully synhronous iruit. We all suh graph as a iruit graph. A iruit graph onsists of a set of noes an a set of irete eges for onneting two noes. Eah noe is laele y either (nput port), (utput port), (Cominational Ciruit), (egister), N (Negative egister), AM, or M. A noe with lael is onnete with one or more outgoing eges. A noe with lael is onnete with exatly one inoming ege. A noe with lael has one or more inoming eges an one or more outgoing eges. A noe with lael, N, AM, or M has one inoming an one outgoing ege. We also assume that a iruit graph is a irete reahale graph (DG), suh that for every internal noe, there exists a irete path from an input noe to an output noe whih inlues it. Figure 2 (2) illustrates an example of a DG. Note that noes with lael,, N, AM, or M has only one outgoing ege. The reaers may think that one outgoing ege is a too stringent restrition eause it oes not allow two or more fan-outs. However, we an implement multiple fan-outs y attahing a simple Cominational Ciruit () that just upliates the input. For example, a with one input port A an two output ports F an G suh that F = A an G = A is use to implement fan-out 2 as illustrate in Figure 8. For a given iruit X with AMs, we will show an algorithm to erive an AM-free an N-free iruit, Y y rewriting iruits. We assume that X is given as a iruit graph. We will efine rules to rewrite a iruit graph. The Fig. 8. F = A A G = A A ominational iruit to implement fan-out 2 iruit. reaers shoul refer to Figure 9 for illustrating the rules, where an enote preeessor an suessor noes respetively. The noes etween preeessor an suessor noes are rewritten as follows: ule AM noe is rewritten into M+N. ule 1 Ajaent an N noes are rewritten into NULL iruit, that is, they are remove. ule 2 +M is rewritten into M+. ule 3 f all the inoming eges of a noe are onnete to an noe, then all the s are remove to all the outgoing eges of the noe. ule 4 N+M is rewritten into M+N. ule 5 f one of the inoming eges of a noe is onnete to an N noe, then the N noe is remove, an noe is ae to all the other inoming eges, an the N noe is move to all the outgoing eges of the noe. The reaers shoul have no iffiulty to onfirm that, after applying one of the rewriting rules, an original iruit an the resulting iruit are euivalent. lease see [8] for the etails regaring the euivaleny. We are now in position to esrie the rewriting algorithm. uppose that an input iruit graph has noes with laels,,, AM, M, an. The following rewriting algorithm generates a iruit graph euivalent to the original iruit graph. Fin a minimum i suh that ule i an e applie to the urrent iruit graph. ewrite the iruit graph using suh ule i. This rewriting proeure is repeate until no more rewriting is possile. V. BEHAV F U CCUT EWTNG ALGTHM Let us oserve the ehavior of our iruit rewriting algorithm. ffl First, ule is applie to all AM noes, an they are rewritten into M+N. After that, ule is never applie. ffl ules 1 is applie an ajaent an N noes are remove whenever possile. ffl noes are move towar the output noes using ules 2 an 3 whenever possile. ffl N noes are move towar the output noes or are rotate in yles using ules 4 an 5. 81

6 -it register AM M = = AM -it register Fig. 7. M, +AM, an AM+. M N M N M AM ule ule 1 N N M ule2 M ule 4 N N ule 3 ule 5 N N Fig. 9. ules to rewrite a iruit graph. Let us see how our iruit rewriting algorithm works using an example of a iruit in Figure 1, whih shows the interim an resulting iruit graphs. First, ule is applie to the AM, it is onverte into M+N. After that, ule 3 is use to move the, an two s are generate. ule 5 is applie to move the N an it is upliate. Finally, ajaent 82

7 ule ule 3 ule 5 ule 5 ule 1 AM M M M M M 1 N N N 1 1 N N Fig. 1. nterim an resulting iruit graphs otaine y our rewriting algorithm for a iruit graph. an N are remove y ule 1. ur iruit rewriting algorithm may not terminate for a iruit graph that has no way to onvert an euivalent AMfree iruit. Figure 11 shows an example of suh iruit graph. t has a yle with two AMs an one. ntuitively, one is neessary to onvert an AM into an M. Thus, this iruit graph an not e onverte into an euivalent AMfree iruit. Let us see how our iruit rewriting algorithm works for the iruit graph in Figure 11. After applie ule an ule 1, the interim iruit graph has an N in the yle. ule 5 is applie to move the N, an a new is generate etween the noe an the noe. After that, the N jumps over the M y ule 4. ule 5 is applie again, an a new N is generate etween the noe an the noe. Again, the N jumps over the M y ule 4. The reaers shoul have no iffiulty to onfirm that, while the N is rotate in the yle, one new is generate etween the noe an the noe an one new N is generate etween the noe an the noe. ule 5 an ule 4 an e repeate applie in the same way. n general, after ule 5 an ule 4 applie 2n times, new n s an n N s are generate, an our iruit rewriting algorithm never terminates. For the purpose of larifying the onition suh that our rewriting algorithm an generate AM-free an N-free iruit graph, we efine the potentiality of the noes in a iruit graph. uppose that a noe v of a iruit graph has m ( ) inoming eges suh as (u 1 ;v); (u 2 ;v);:::;(u m ;v). Letus efine the potentiality p(v) of a noe v as follows: ffl f v is, then p(v) =. ffl f v is or M, then p(v) =p(u 1 ). ffl f v is AM or N then p(v) =p(u 1 ) 1. ffl f v is then p(v) =p(u 1 )+1. ffl f v is, then p(v) =min(p(u 1 );p(u 2 );:::;p(u m )). From the efinition, the potentiality of a noe an e etermine if the potentiality of all preeessor noes are etermine. Unfortunately, as we will show next, we may not etermine the potentiality of every noe y the aove efinition, if a iruit graph has a yle. Let us isuss the potentiality for a iruit graph with a yle using three iruits in Figure 12. Let the potentiality p(a) of the noe a e k. From the efinition of the potentiality, we an write the euations of potentiality for Figure 12 (1) as follows: p(a) =k, p() =min(p(a);p(e)), p() =p() +1, p() =p(), p(e) =p() +1, anp(f )=p(). From these euations, we have, p(e) =p()+1 = p()+2 an thus, p() = min(k; p() + 2). Hene, we an etermine the value of p() suh that p() =k. Further, we an etermine the potentiality of the other noes as follows: p() =p() = p(f ) = k +1,anp(e) = k +2. ntuitively, the euation p() = min(k; p() +2) means that the yle is a positive yle eause the yle e inreases the potentiality y +2. We an o the same isussion for Figure 12 (2) as follows: p(a) =k, p() =min(p(a);p(e)), p() =p() +1, p() =p(), p(e) =p() 1, anp(f )=p(). From these euations, we have, p() = min(k; p()). egarless the value of p(), this euation is satisfie. f this is the 83

8 ule, ule 1 ule5, ule 4 ule5, ule 4 ule5, ule 4 are applie 2(n 1) times n s AM AM M N M M M N M N N M M M N n Ns Fig. 11. Example of a iruit for whih our rewriting algorithm oes not terminate. ase, we assume that p() = k. We an then etermine the potentiality of the other noes as follows: p() = p() = p(f ) = k +1, an p(e) = k. imilarly, from the euation p() = min(k; p()), we an think that the yle is a zero yle. Figure 12 (3) shows an example of a negative yle. We have the euations as follows: p(a) =k, p() = min(p(a);p(e)), p() =p() 1, p() =p(), p(e) =p() 1, anp(f )=p(). From these euations, we have, p() = min(k; p() 2). f p() 6= k then p() = p() 2. Hene p() = k must e satisfie. f this is the ase, p() =min(k; k 2) = k 2, a ontraition. Therefore, p() = min(k; p() 2) has no solution. From this oservation, we efine the potentiality of a yle as follows: Let v ;v 1 ;:::;v m (= v ) e a yle suh that there is a irete ege (v i ;v i+1 )(» i» m 1). Weefinethe potentiality p (v i ) of noe v i (1» i» m) with respet to the yle starting v as follows: ffl p (v )=. ffl f v i+1 is or M, then p (v i+1 )=p (v i )(» i» m 1). ffl f v i+1 is AM or N then p (v i+1 )=p (v i ) 1(» i» m 1). ffl f v i+1 is then p (v i+1 )=p (v i )+1 (» i» m 1). We say that the potentiality of the yle is p (v m ). For example, the potentialities of the yles in Figure 12 (1), (2), an (3) are 2,, an -2, respetively. We have the following theorem. f a e f a N e N a N (1) positive yle (2) zero yle (3) negative yle Fig. 12. The potentiality for iruits with a yle Theorem 1: ur rewriting algorithm generates an AMfree an N-free iruit graph, euivalent to the original iruit graph, if all noes an all yles of a iruit graph have non-negative potentiality. n other wors, we an etermine a fully synhronous iruit that an e onverte into an AM-free iruit y evaluating the potentiality of all noes an all yles of the orresponing iruit graph. Also, the potentiality of all noes an all yles are non-negative, our rewriting algorithm generates an AM-free an N-free iruit graph, an the orresponing fully synhronous iruit is AM-free an f e 84

9 euivalent to the original fully synhronous iruit. V. F F THEEM 1 The main purpose of this setion is to show a proof of Theorem 1. We will show several lemmas for a proof of Theorem 1. First, let us oserve how the potentiality of noes is hange y our rewriting algorithm. We fous the potentiality of suessor noes. Let an enote the preeessor an suessor noes for ules, 1, 2 an 4. Also, let 1, 2, 3,an 1, 2 e the three preeessor an two suessor noes in ules 3 an 5. We ompute the potentiality of eah suessor noe oth efore an after applying the rules as follows. ule p() =p( ) 1. ule 1 p() =p( ). ule 2 p() =p( )+1. ule 3 p( 1 )=p( 2 ) = min(p( 1 )+1;p( 2 )+1;p( 3 )+ 1) = min(p( 1 ), p( 2 ), p( 3 )) + 1. ule 4 p() =p( ) 1. ule 5 p( 1 )=p( 2 ) = min(p( 1 ) 1;p( 2 );p( 3 )) = min(p( 1 );p( 2 )+1;p( 3 )+1) 1. Thus, the potentiality of every suessor noe is never hange y applying the rules. n every rule, noes an only e suessor noes. Thus, we have, Lemma 2: The potentiality of every noe of the resulting iruit graph is the same as that of the orresponing noe of the original iruit graph. imilarly, we an prove the following lemma: Lemma 3: The potentiality of every yle of the resulting iruit graph is the same as that of the orresponing yle of the original iruit graph. n a iruit graph, let asegmente a irete path u 1, u 2, :::, u m suh that, u 1 an u m are either,, M, or, an u 2, :::, u m 1 are either or N. Note that, if m =2 then it represents a null segment with u 1, u 2. We have the following lemma: Lemma 4: ne our iruit rewriting algorithm uses either ule 4 or ule 5 to move an N noe, it never applies ule 2 an ule 3 to move an noe. roof: f either ule 4 or ule 5 is applie an interim iruit, oth ule 2 an ule 3 annot e applie to it. f this is the ase, all s are either (1) in the segment of s ening at an noe, or (2) in the segment of s ening at an noe an another inoming ege of the noe is not onnete to (Figure 13). To apply ule 2 an ule 3 later, the non- noe in Figure 13 must e an noe. However, to e an noe, ule 2 an ule 3 must e use. Thus, oth ule 2 an ule 3 are never applie. We will prove that all Ns in a yle with non-negative potentiality will e remove y our rewriting algorithm. Lemma 5: uppose that all yles in a iruit graph have non-negative potentiality, an ule are repeately applie to remove all AMs. f a yle has m Ns, it also has at least m s. f either ule 2 or ule 3 is applie, the s are move an ajaent an N may e remove y ule 1. f either (1) (2) non- Fig. 13. llustration for the proof of Lemma 4 ule 4 an ule 5 is applie, the Ns are move. Note that, from Lemma 4, the s are never move, one either ule 4 an ule 5 is applie. n other wors, the Ns are move along the yle, while s are never move. Thus, at some point, all Ns in the yle will e remove y ule 1. Note that, if there exists a yle with negative potentiality, our iruit rewriting algorithm oes not terminate. As illustrate in Figure 11, an N moves along the yle an s an Ns are repeately generate. t shoul e lear that, there exists no way to generate an euivalent AM-free iruit for suh iruit. When our rewriting algorithm terminates an the resulting iruit graph is otaine, we have the following lemma: Lemma 6: Let u e an N noe an (u; v) e its outgoing ege in the resulting iruit graph. Noe v must e either N or noe. Also, all N noes must e in segments ening at noe. roof: f v is an, M, or noe then ules 1, 4, or 5 an e applie. ine no more rule an e applie to the resulting iruit graph, v must e either N or noes. ine the suessor of N noes must e N or noes, all N noes must e in segments ening at noe. A simple irete path is a irete path if it has no repeate noes. For example, in Figure 2 (2), (B; E; H; K; N; ) is a simple irete path, ut (B; E; H; ; F; E; H; K; N; ) is not. We say that noes are regular if it is on a simple irete path from an input noe to an output noe. Note that noes on a yle in a DG an e a non-regular noe. For example, noes F an are non-regular noes. From Lemma 6, we will prove that all regular M an noes in the resulting iruit graph have zero potentiality. Lemma 7: All regular M an noes in the resulting iruit graph have non-negative potentiality. roof: ine the resulting graph is AM-free, noes follows N noes an have negative potentiality. ine no segment ening at M or have N noes, their potentiality must e non-negative. imilarly, we have the following lemma. Lemma 8: All regular M an noes in a simple irete path from an input noe to an output noe in the 85

10 resulting iruit graph have non-positive potentiality. roof: We assume that the resulting iruit graph has a positive potentiality M or noe in a simple irete path from an input noe to an output noe, an show a ontraition. Let v e a first M or noe with negative potentiality, that is, all M an noes in all irete paths inoming to v have non-positive potentiality an M or noe v has positive potentiality. Case 1 v is an M noe Let (u; v) enote the inoming ege. f u is either or N, then ule 2 or ule 4 an e applie. ine no more rule an e applie to the resulting iruit graph, it must e either, M, or. f this is the ase, p(u) =an thus, p(v) =, a ontraition. Case 2 v is a noe Let (u 1 ;v); (u 2 ;v);:::;(u k ;v) (k 1) enote the inoming eges. From Lemma 6, none of u 1 ;u 2 ;:::;u k is an N noe. f all of them are noes, then ule 3 an e applie. Thus, at least one of them is not an noe. t follows that at least one of them is either, M, or noe. From the assumption, the potentiality of suh noe is nonpositive, Hene, the potentiality of v is non-positive, a ontraition. We are now in position to show the proof of Theorem 1. From Lemma 7 an 8, all M an noes in a simple irete path from an input noe to an output noe of the resulting iruit graph have zero potentiality. Hene, if the potentiality of one of the noes in the resulting iruit graph is negative, a segment ening at noe in the resulting graph shoul have N from Lemma 6. imilarly, if the potentiality of all the noes is non-negative, no segment ening at an output noe has N in the resulting iruit graph. From Lemma 2, the potentiality of noes oes not hange y our rewriting algorithm. Thus, from Lemma 5, if all output noes an all yles of a iruit graph have negative potentiality our rewriting algorithm generates the resulting iruit graph with N noes. This ompletes the proof of Theorem 1. As we have isusse, our iruit rewriting algorithm oes not terminate for a iruit graph with a negative yle. We an moify our iruit rewriting algorithm that always terminates as follows: First, we ompute the potentiality of every yles. f one of them is negative, we o not exeute our iruit rewriting algorithm. ine it is impossile to generate an euivalent AM-free iruit if this is the ase, it is not reasonale to exeute our iruit rewriting algorithm. AMs to support the urrent FGA arhiteture. t is not trivial to onvert the seuential iruits (yles inlue) with AMs into the euivalent fully synhronous iruits with no AMs for supporting the moern FGA. However, our algorithm an o it automatially. EFEENCE [1] J. Borim, Y. to, an K. Nakano. Aelerating the CKY parsing using FGAs. ECE Transations on nformation an ystems, E86- D(5):83 81, 23. [2] J. Borim, Y. to, an K. Nakano. nstane-speifi solutions to aelerate the CKY parsing for large ontext-free grammars. nternational Journal on Founations of Computer iene, 15(2):43 416, 24. [3].. C. Design of an FGA logi element for implementing asynhronous NULL onvention logi iruits. EEE Transations on very large sale integration (VL) system, 15(6): , June 27. [4] Y. to an K. Nakano. A harware-software ooperative approah for the exhaustive verifiation of the Collatz ojeture. n ro. of nternational ymposium on arallel an Distriute roessing with Appliations, pages 63 7, 29. [5]. Jens. Asynhronous iruit esign, a tutorial. [6] L. Lavagno an A. angiovanni-vinentelli. Algorithms for synthesis an testing of asynhronous iruits. Kluwer Aaemi, [7]. Manohar. eonfigurale asynhronous logi. n ro. of EEE Custom ntegate Ciruits Conferene, pages 13 2, 26. [8] M. N.. Monal, K. Nakano, an Y. to. A rewriting algorithm to generate arom-free fully synhronous iruits. n ro. of nternational Conferene on Networking an Computing, pages , Novemer 21. [9] K. Nakano an Y. Yamagishi. Harware n hoose k ounters with appliations to the partial exhaustive searh. ECE Transations on nformation an ystems, E88-D(7), 25. [1]. hota, K. Yoshiya, H. Masanori, an K. Mihitaka. An asynhronous fiel-programmale VL using LED/4-phase-ual-rail protool onverters. n The nternational Conferene on Engineering of eonfigurale ystems an Algorithms (EA), Monte Carlo esort, Las Vegas, Nevaa, UA, July 29. [11] J. Teifel an. Manohar. An asynhronous ataflow FGA arhiteture. EEE Transation on Computers, 53(11): , 24. V. CNCLUN n this paper, we have presente a rewriting algorithm an six rewriting rules to otain the euivalent iruits with ynhronous Ms (Ms) for the iruits with Asynhronous Ms (AMs) inluing yles. Using our rewriting algorithm, any seuential iruit with AMs represente y a irete reahale graph (DG) an e onverte into an euivalent fully synhronous seuential iruit with no 86